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VIPer20/SP/DIP |
® |
VIPer20A/ASP/ADIP |
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SMPS PRIMARY I.C. |
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TYPE |
VDSS |
In |
RDS(on) |
VIPer20/SP/DIP |
620V |
0.5 A |
16 Ω |
VIPer20A/ASP/ADIP |
700V |
0.5 A |
18 Ω |
■ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz
■CURRENT MODE CONTROL
■SOFT START AND SHUT DOWN CONTROL
■AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET “BLUE ANGEL” NORM (<1W TOTAL POWER CONSUMPTION)
■INTERNALLY TRIMMED ZENER REFERENCE
■UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS
■INTEGRATED START-UP SUPPLY
■AVALANCHE RUGGED
■OVERTEMPERATURE PROTECTION
■LOW STAND-BY CURRENT
■ADJUSTABLE CURRENT LIMITATION
BLOCK DIAGRAM
PENTAWATT HV |
PENTAWATT HV (022Y) |
10 |
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1 |
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PowerSO-10™ |
DIP-8 |
DESCRIPTION
VIPer20/20A, made using VIPower M0 Technology, combines on the same silicon chip a state-of-the-art PWM circuit together with an optimized high voltage avalanche rugged Vertical Power MOSFET (620V or 700V / 0.5A).
Typical applications cover off line power supplies with a secondary power capability of 10W in wide range condition and 20W in single range or with doubler configuration. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components.
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OSC |
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DRAIN |
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ON/OFF |
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OSCILLATOR |
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SECURITY |
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PWM |
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LATCH |
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LATCH |
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UVLO |
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S |
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VDD |
R/S |
FF |
Q |
R1 |
FF |
Q |
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LOGIC |
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R2 R3 |
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OVERTEMP. |
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DETECTOR |
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0.5V |
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0.5 V |
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1.7 |
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6 V/A |
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250 ns |
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μs |
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Blanking |
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delay |
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ERROR |
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CURRENT |
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AMPLIFIER |
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AMPLIFIER |
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13 V |
+ |
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4.5 V |
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COMP |
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SOURCE |
FC00491 |
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July 2002 |
1/25 |
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ABSOLUTE MAXIMUM RATING
Symbol |
Parameter |
Value |
Unit |
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Continuous Drain-Source Voltage (Tj=25 to 125°C) |
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VDS |
for VIPer20/SP/DIP |
-0.3 to 620 |
V |
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for VIPer20A/ASP/ADIP |
-0.3 to 700 |
V |
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ID |
Maximum Current |
Internally limited |
A |
VDD |
Supply Voltage |
0 to 15 |
V |
VOSC |
Voltage Range Input |
0 to VDD |
V |
VCOMP |
Voltage Range Input |
0 to 5 |
V |
ICOMP |
Maximum Continuous Current |
± 2 |
mA |
Vesd |
Electrostatic Discharge (R =1.5kΩ; C=100pF) |
4000 |
V |
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Avalanche Drain-Source Current, Repetitive or Not Repetitive |
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ID(AR) |
(TC=100°C; Pulse width limited by T j max; δ < 1%) |
0.5 |
A |
for VIPer20/SP/DIP |
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for VIPer20A/ASP/ADIP |
0.4 |
A |
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Ptot |
Power Dissipation at Tc=25ºC |
57 |
W |
Tj |
Junction Operating Temperature |
Internally limited |
°C |
Tstg |
Storage Temperature |
-65 to 150 |
°C |
THERMAL DATA
Symbol |
Parameter |
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PENTAWATT |
PowerSO-10™ (*) |
DIP-8 |
Unit |
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Rthj-pin |
Thermal Resistance Junction-pin |
Max |
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20 |
°C/W |
Rthj-case |
Thermal Resistance Junction-case |
Max |
2.0 |
2.0 |
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°C/W |
Rthj-amb. |
Thermal Resistance Ambient-case |
Max |
70 |
60 |
35 (#) |
°C/W |
(*) When mounted using the minimum recommended pad size on FR-4 board. |
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(#) On multylayer PCB. |
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CONNECTION DIAGRAMS (Top View) |
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PENTAWATT HV |
PENTAWATT HV (022Y) |
PowerSO-10™ |
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DIP-8 |
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OSC |
1 |
8 |
DRAIN |
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Vdd |
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DRAIN |
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SOURCE |
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DRAIN |
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COMP |
4 |
5 |
DRAIN |
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SC10540 |
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CURRENT AND VOLTAGE CONVENTIONS
IDD |
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ID |
VDD |
DRAIN |
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IOSC |
- |
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OSC |
+ |
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13V |
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VDD |
COMP SOURCE |
VDS |
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ICOMP |
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VOSC |
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VCOMP |
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FC00020 |
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2/25 |
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ORDERING NUMBERS
PENTAWATT HV |
PENTAWATT HV (022Y) |
PowerSO-10™ |
DIP-8 |
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VIPer20 |
VIPer20 (022Y) |
VIPer20SP |
VIPer20DIP |
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VIPer20A |
VIPer20A (022Y) |
VIPer20ASP |
VIPer20ADIP |
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PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power.
SOURCE Pin:
Power MOSFET source pin. Primary side circuit common ground connection.
VDD Pin:
This pin provides two functions:
-It corresponds to the low voltage supply of the
control part of the circuit. If VDD goes below 8V, the start-up current source is activated and the output power MOSFET is switched off until the
VDD voltage reaches 11V. During this phase, the internal current consumption is reduced,
the VDD pin sources a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again.
-This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference
voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V
and 12.5V will be put on VDD pin by transformer design, in order to stick the output of the transconductance amplifier to the high state. The COMP pin behaves as a constant current
source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control.
COMP PIN:
This pin provides two functions:
-It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its bandwidth can easily be adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin.
-When the COMP voltage goes below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever is the configuration) to provide a burst mode operation in case of negligible output power or open load condition.
OSC PIN:
An Rt-Ct network must be connected on that pin to define the switching frequency. Note that despite the connection of Rt to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It also provides a synchronization capability, when connected to an external frequency source.
3/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
AVALANCHE CHARACTERISTICS
Symbol |
Parameter |
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Max Value |
Unit |
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Avalanche Current, Repetitive or Not Repetitive |
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ID(AR) |
(pulse widht limited by Tj max; δ < 1%) |
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0.5 |
A |
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for VIPer20/SP/DIP |
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for VIPer20A/ASP/ADIP |
(see fig.12) |
0.4 |
A |
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E(ar) |
Single Pulse Avalanche Energy |
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10 |
mJ |
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(starting Tj =25ºC, I D=ID(ar)) |
(see fig.12) |
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ELECTRICAL CHARACTERISTICS (Tj=25°C; V DD=13V, unless otherwise specified) POWER SECTION
Symbol |
Parameter |
Test Conditions |
Min |
Typ |
Max |
Unit |
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ID=1mA; VCOMP=0V |
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BVDSS |
Drain-Source Voltage |
for VIPer20/SP/DIP |
620 |
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V |
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for VIPer20A/ASP/ADIP (see fig.5) |
700 |
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V |
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VCOMP=0V; Tj=125°C |
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IDSS |
Off-State Drain Current |
VDS=620V for VIPer20/SP/DIP |
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1.0 |
mA |
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VDS=700V for VIPer20A/ASP/ADIP |
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1.0 |
mA |
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ID=0.4A |
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13.5 |
16 |
Ω |
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for VIPer20/SP/DIP |
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15.5 |
18 |
Ω |
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RDS(on) |
Static Drain-Source |
for VIPer20A/ASP/ADIP |
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On Resistance |
ID=0.4A; Tj=100°C |
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for VIPer20/SP/DIP |
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29 |
Ω |
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for VIPer20A/ASP/ADIP |
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32 |
Ω |
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tf |
Fall Time |
ID=0.2A; VIN=300V (1) |
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100 |
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(See fig. 3) |
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tr |
Rise Time |
ID=.4A; VIN=300V (1) |
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50 |
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ns |
(See fig. 3) |
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Coss |
Output Capacitance |
VDS=25V |
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90 |
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pF |
(1) On Inductive Load, Clamped. |
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SUPPLY SECTION |
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Symbol |
Parameter |
Test Conditions |
Min |
Typ |
Max |
Unit |
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IDDch |
Start-Up Charging |
VDD=5V; VDS=35V |
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-2 |
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mA |
Current |
(see fig. 2 and fig. 15) |
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IDD0 |
Operating Supply Current |
VDD=12V; FSW=0kHz |
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12 |
16 |
mA |
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(see fig. 2) |
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IDD1 |
Operating Supply Current |
VDD=12V; Fsw=100kHz |
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13 |
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mA |
IDD2 |
Operating Supply Current |
VDD=12V; Fsw=200kHz |
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14 |
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mA |
VDDoff |
Undervoltage Shutdown |
(See fig. 2) |
7.5 |
8 |
9 |
V |
VDDon |
Undervoltage Reset |
(See fig. 2) |
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11 |
12 |
V |
VDDhyst |
Hysteresis Start-up |
(See fig. 2) |
2.4 |
3 |
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V |
4/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATOR SECTION
Symbol |
Parameter |
Test Conditions |
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Min |
Typ |
Max |
Unit |
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Rt=8.2KΩ; Ct=2.4nF |
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90 |
100 |
110 |
kHz |
FSW |
Oscillator Frequency |
VDD=9 to 15V; |
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Total Variation |
with Rt± 1%; Ct± 5% |
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(see fig. 6 and fig. 9) |
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VOSCih |
Oscillator Peak Voltage |
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7.1 |
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V |
VOSCil |
Oscillator Valley Voltage |
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3.7 |
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V |
ERROR AMPLIFIER SECTION |
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Symbol |
Parameter |
Test Conditions |
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Min |
Typ |
Max |
Unit |
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VDDreg |
VDD Regulation Point |
ICOMP=0mA |
(see fig. 1) |
12.6 |
13 |
13.4 |
V |
VDDreg |
Total Variation |
Tj=0 to 100°C |
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2 |
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% |
GBW |
Unity Gain Bandwidth |
From Input =VDD to Output = VCOMP |
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150 |
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kHz |
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COMP pin is open |
(see fig. 10) |
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AVOL |
Open Loop Voltage Gain |
COMP pin is open |
(see fig. 10) |
45 |
52 |
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dB |
Gm |
DC Transconductance |
VCOMP=2.5V |
(see fig. 1) |
1.1 |
1.5 |
1.9 |
mA/V |
VCOMPLO |
Output Low Level |
ICOMP= -400µA; VDD=14V |
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0.2 |
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V |
VCOMPHI |
Output High Level |
ICOMP=400µA; VDD=12V |
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4.5 |
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V |
ICOMPLO |
Output Low Current |
VCOMP=2.5V; VDD=14V |
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-600 |
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µA |
Capability |
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ICOMPHI |
Output High Current |
VCOMP=2.5V; VDD=12V |
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600 |
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µA |
Capability |
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PWM COMPARATOR SECTION |
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Symbol |
Parameter |
Test Conditions |
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Min |
Typ |
Max |
Unit |
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HID |
VCOMP / IDPEAK |
VCOMP=1 to 3 V |
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4.2 |
6 |
7.8 |
V/A |
VCOMPoff |
VCOMP Offset |
IDPEAK=10mA |
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0.5 |
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V |
IDpeak |
Peak Current Limitation |
VDD=12V; COMP pin open |
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0.5 |
0.67 |
0.9 |
A |
td |
Current Sense Delay to |
ID=1A |
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250 |
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ns |
Turn-Off |
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tb |
Blanking Time |
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250 |
360 |
ns |
ton(min) |
Minimum On Time |
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350 |
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ns |
SHUTDOWN AND OVERTEMPERATURE SECTION |
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Symbol |
Parameter |
Test Conditions |
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Min |
Typ |
Max |
Unit |
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VCOMPth |
Restart Threshold |
(see fig. 4) |
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0.5 |
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V |
tDISsu |
Disable Set Up Time |
(see fig. 4) |
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1.7 |
5 |
µs |
Ttsd |
Thermal Shutdown |
(See fig. 8) |
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140 |
170 |
190 |
°C |
Temperature |
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Thyst |
Thermal Shutdown |
(See fig. 8) |
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40 |
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°C |
Hysteresis |
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5/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 1: VDD Regulation Point
ICOMP |
Slope = |
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ICOMPHI |
Gm in mA/V |
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VDD |
0 |
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ICOMPLO |
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VDDreg |
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FC00150 |
Figure 3: Transition Time
ID
10% Ipeak
t
VDS
90% VD
10% VD
t
tf |
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tr |
FC00160
Figure 5: Breakdown Voltage Vs. Temperature
1.15 |
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FC00180 |
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BVDSS |
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(Normalized) |
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1.1 |
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1.05 |
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1 |
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0.95 |
20 |
40 |
60 |
80 |
100 |
120 |
0 |
Temperature (°C)
Figure 2: Undervoltage Lockout
IDD |
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IDD0 |
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VDDhyst |
VDS= 35 V |
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Fsw = 0 |
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VDDoff |
VDD |
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VDDon |
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IDDch |
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FC00170 |
Figure 4: Shut Down Action
VOSC |
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t |
VCOMP |
tDISsu |
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VCOMPth |
t |
ID
t
ENABLE |
ENABLE |
DISABLE
FC00060
Figure 6: Typical Frequency Variation
1 |
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FC00190 |
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(%) |
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0 |
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-1 |
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-2 |
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-3 |
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-4 |
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-5 |
20 |
40 |
60 |
80 |
100 |
120 |
140 |
0 |
Temperature (°C)
6/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 7: Start-Up Waveforms
Figure 8: Overtemperature Protection
TJ |
Ttsc |
Ttsd-Thyst |
t |
Vdd |
Vddon |
Vddoff |
t |
Id |
t
Vcomp
t |
SC10191 |
7/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 9: Oscillator
Rt |
VDD |
For Rt >1.2KW |
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and |
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OSC |
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Ct ³ 15nF if FSW £ 40KHz |
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2.3 |
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æ |
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550 |
ö |
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CLK |
FSW = |
----------- |
× è |
1 – |
--------------------- |
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R |
C |
t |
R |
t |
– 150ø |
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Ct |
Ω |
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t |
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~360 |
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FC00050 |
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Ct |
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Forbidden area |
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880
Ct(nF) =
Fsw(kHz)
22nF
15nF
Forbidden area
40kHz |
Fsw |
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Oscillator frequency vs Rt and Ct
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1,000 |
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FC00030 |
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Ct = 1.5 nF |
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500 |
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Ct = 2.7 nF |
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(kHz) |
300 |
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200 |
Ct = 4.7 nF |
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Frequency |
100 |
Ct = 10 nF |
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50 |
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30 |
2 |
3 |
5 |
10 |
20 |
30 |
50 |
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1 |
Rt (kΩ)
8/25