STMicroelectronics STY60NM50 Technical data

STY60NM50
N-CHANNEL 500V - 0.045- 60A Max247
Zener-Protected MDmesh™Power MOSFET
TYPE V
STY60NM50 500V < 0.05 60 A
TYPICAL RDS(on) = 0.045
HIGH dv/dt AND AVALANCHE CAPABILITIES
IMPROVED ESD CAPABILITY
LOW INPUT CAPACITANCE AND GATE
DSS
R
DS(on)
I
D
CHARGE
LOW GATE INPUT RESISTANCE
TIGHT PROCESS CONTROL
INDUSTRY’S LOWEST ON-RESISTANCE
DESCRIPTION
The MDmes h™ is a new revolutionary MOSFET technology that associates the Multiple Drain pro­cess with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar c ompetition’s products.
APPLICATIONS
The MDmesh™ family is very suitable for increasing power densi ty of high voltage converters allowing system miniaturization and higher efficiencies.
3
2
1
Max247
INTERNAL SCHE M ATIC DIAGRAM
ABSOLUTE M AXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 15 V/ns
T
stg
T
j
(•)Pulse width limited by safe operating area
Drain-source Voltage (VGS=0) Drain-gate Voltage (RGS=20kΩ) Gate- source Voltage ±30 V Drain Current (continuous) at TC= 25°C Drain Current (continuous) at TC= 100°C
()
Drain Current (pulsed) 240 A Total Dissipation at TC= 25°C Gate source ESD(HBM-C=100pF, R=15KΩ) 6KV Derating Factor 4.5 W/°C
Storage Temperature –65 to 150 °C Max. Operating Junction Temperature 150 °C
(1)ISD≤60A, di/dt 400A/µs, VDD≤ V
500 V 500 V
60 A
37.8 A
560 W
(BR)DSS,Tj≤TJMAX
1/8November 2003
STY60NM50
THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 0.22 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACT ERISTICS (TCASE = 25 °C UNLESS OTHERWISE S PECIFIED) OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T
max)
j
Single Pulse Avalanche Energy (starting T
Drain-source
= 25 °C, ID=IAR,VDD=35V)
j
ID= 250 µA, VGS= 0 500 V
30 A
1.4 J
Breakdown Voltage Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage Current (V
DS
=0)
=0)
V
= Max Rating
DS
= Max Rating, TC= 125 °C
V
DS
V
= ± 20V ± 10 µA
GS
10 µA
100 µA
ON (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage Static Drain-source On
V
DS=VGS,ID
VGS=10V,ID=30A
= 250µA
345V
0.045 0.05
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS>I
g
fs
ID= 30A
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance 980 pF Reverse Transfer
V
Capacitance
R
G
Gate Input Resistance f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV Open Drain
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
D(on)xRDS(on)max,
=25V,f=1MHz,VGS=0
DS
35 S
7500 pF
200 pF
1.5
2/8
STY60NM50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q Q Q
t
r
gs
gd
Turn-on Delay Time Rise Time 58 ns Total Gate Charge
g
Gate-Source Charge 53 nC Gate-Drain Charge 97 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
t
t
f c
Off-voltage Rise Time Fall Time 46 ns Cross-over Time 108 ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD(1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limitedby safe operating area.
Source-drain Current 60 A
(2)
Source-drain Current (pulsed) 240 A Forward On Voltage Reverse Recovery Time
Reverse Recovery Charge Reverse Recovery Current
Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
= 250V, ID= 30A
DD
= 4.7VGS=10V
R
G
(see test circuit, Figure 3) V
= 400V, ID= 60A,
DD
VGS=10V
V
=400V,ID= 60A,
DD
= 4.7Ω, VGS=10V
R
G
(see test circuit, Figure 5)
ISD= 60A, VGS=0
= 60A, di/dt = 100A/µs,
I
SD
VDD= 100 V, Tj= 25°C (see test circuit, Figure 5)
= 60A, di/dt = 100A/µs,
I
SD
V
= 100 V, Tj= 150°C
DD
(see test circuit, Figure 5)
51 ns
190 266 nC
51 ns
1.5 V
532
9.9 37
636
13.4 42
ns
µC
A
ns
µC
A
Thermal ImpedanceSafe Operating Area
3/8
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