STMicroelectronics STY30NK90Z Technical data
STY30NK90Z
N-CHANNEL 900V - 0.21Ω - 26A Max247
Zener-Protected SuperMESH™ MOSFET
Table 1: General Features
TYPE V
STY30NK90Z 900 V < 0.26 Ω 28 A 500 W
■ TYPICAL R
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
DSSRDS(on)ID
(on) = 0.25 Ω
DS
Pw
REPEATIBILITY
DESCRIPTION
The Sup erM ESH™ se ries is ob tai ned th ro ugh a n
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushin g on-resis tance sign ifican tly down, special
care is taken to en sur e a v er y good d v/ d t c ap ab i lity
for the most demanding applications. Such series
complements ST full range of high voltage MOSFETs i n cludi n g re vol u tion ar y MDme sh™ p r oduc t s.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR WELDING EQUIPMENT
Figure 1: Package
3
2
1
Max247
Figure 2: Internal Schematic Diagram
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STY30NK90Z Y30NK90Z Max247 TUBE
Rev.3
1/10January 2005
STY30NK90Z
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
V
V
V
I
DM
P
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
T
() Pulse width limited by safe operating area
(1) ISD ≤ 26A, di/dt ≤ 400A/µs, VDD ≤ V
(*) Limited only by maximum temperature allowed
Table 4: Thermal Data
Rthj-case Thermal Resistance Junction-case Max 0.277 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W
Drain-source Voltage (VGS = 0)
DS
Drain-gate Voltage (RGS = 20 kΩ)
DGR
Gate- source Voltage ± 30 V
GS
I
Drain Current (continuous) at TC = 25°C
D
Drain Current (continuous) at TC = 100°C
I
D
()
Drain Current (pulsed) 104 A
Total Dissipation at TC = 25°C
TOT
900 V
900 V
26 A
16 A
450 W
Derating Factor 3.57 W/°C
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6KV
Insulation Withstand Voltage (AC-RMS) from All Four
ISO
Terminals to External Heatsink
T
Operating Junction Temperature
j
Storage Temperature
stg
, Tj ≤ T
(BR)DSS
T
Maximum Lead Temperature For Soldering Purpose
l
JMAX.
2500 V
- 65 to 150 °C
300 °C
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
E
Avalanche Current, Repetitive or Not-Repetitive
AR
(pulse width limited by T
Single Pulse Avalanche Energy
AS
(starting T
= 25 °C, ID = IAR, VDD = 35 V)
j
max)
j
26 A
500 mJ
Table 6: GATE-SOURCE ZENER DIODE
Symbol Parameter Tes t Conditions Min. Typ. Max. Unit
BV
Gate-Source Breakdown
GSO
Voltage
Igs=± 1mA (Open Drain) 30 V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically bee n designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/10
STY30NK90Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On/Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
Gate-body Leakage
Current (V
= 0)
GS
= 0)
DS
Gate Threshold Voltage
Static Drain-source On
Resistance
ID = 1 mA, VGS = 0 900 V
= Max Rating
V
DS
= Max Rating, TC = 125 °C
V
DS
= ± 20V ±100 µA
V
GS
V
= VGS, ID = 150 µA
DS
3 3.75 4.5 V
10
100µAµA
VGS = 10V, ID = 14 A 0.21 0.26 Ω
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS = 15 V, ID= 14 A 26 S
g
fs
V
= 25V, f = 1 MHz, VGS = 0 12000
DS
852
166
VGS = 0V, VDS = 0V to 720 V 377 pF
V
= 450 V, ID = 13 A
DD
=4.7Ω VGS = 10 V
R
G
(see Figure 17)
V
= 720 V, ID = 26 A,
DD
= 10V
V
GS
(see Figure 20)
67
59
250
72
350
51
190
490
C
oss eq.
C
C
C
t
d(on)
t
d(off)
Q
Q
Q
Input Capacitance
iss
Output Capacitance
oss
Reverse Transfer
rss
Capacitance
(3) Equivalent Output
Capacitance
Turn-on Delay Time
Rise Time
t
r
Turn-off Delay Time
Fall Time
t
f
Total Gate Charge
g
Gate-Source Charge
gs
Gate-Drain Charge
gd
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
I
SDM
V
SD
Q
I
RRM
Q
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
Source-drain Current
SD
(2)
Source-drain Current (pulsed)
(1)
Forward On Voltage
t
rr
Reverse Recovery Time
Reverse Recovery Charge
rr
Reverse Recovery Current
t
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
V
.
DSS
ISD = 28 A, VGS = 0
I
SD
V
(see Figure 18)
I
SD
V
(see Figure 18)
= 26 A, di/dt = 100 A/µs
= 100 V, Tj = 25°C
DD
= 26 A, di/dt = 100 A/µs
= 100 V, Tj = 150°C
DD
18.9
36.6
1.33
25.2
37.8
when VDS increases from 0 to 80%
oss
28
112
2V
1
µs
µC
µs
µC
A
A
A
A
3/10
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