STMicroelectronics STM706, STM706P, STM708 Technical data

STM706, STM706P, STM708

3V Supervisor

FEATURES SUMMARY

■PRECISION VCC MONITOR

–STM706/708

T:3.00V ≤ VRST ≤ 3.15V

S:2.88V ≤ VRST ≤ 3.00V

R; STM706P: 2.59V ≤ VRST ≤ 2.70V

■RST AND RST OUTPUTS

■200ms (TYP) trec

■WATCHDOG TIMER - 1.6sec (TYP)

■MANUAL RESET INPUT (MR)

■POWER-FAIL COMPARATOR (PFI/PFO)

■LOW SUPPLY CURRENT - 40µA (TYP)

■GUARANTEED RST (RST) ASSERTION DOWN TO VCC = 1.0V

■OPERATING TEMPERATURE: –40°C to 85°C (Industrial Grade)

Table 1. Device Options

Figure 1. Packages

8

1

SO8 (M)

TSSOP8 3x3 (DS)

		Watchdog	Watchdog	Active-Low			Active-High	Manual	Power-fail
		Input	Output			(1)	RST(1)	Reset Input	Comparator
					RST
STM706
STM706P(2)
STM708
Note: 1.	Push-Pull Output
2.	The STM706P is identical to the STM706R, except its reset output is active-high.

July 2004

1/25

STM706/706P/708

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Logic Diagram (STM708). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. STM706/706P SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. STM706/706P TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. STM708 SO8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 7. STM708 TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 8. Block Diagram (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 9. Block Diagram (STM708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 10.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Push-button Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Watchdog Input (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Watchdog Output (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ensuring a Valid Reset Output Down to VCC = 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O . . . . . . . . . . . . . . . . . . . . . . . 9

TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 14.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 15.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 16.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 19.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 20.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 21.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 22.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 23.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 24.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 25.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 26.VCC to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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STM706/706P/708

Figure 27.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 28.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 29.Power-fail Comparator Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 30.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 31.Watchdog Timing (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 32.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . . 20 Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 20 Figure 33.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 21 Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 21

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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STM706/706P/708

SUMMARY DESCRIPTION

The STM70X SUPERVISORs are self-contained devices which provide microprocessor supervisory functions. A precision voltage reference and comparator monitors the VCC input for an out-of- tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM708) as well as a power-fail comparator to provide the sys-

tem with an early warning of impending power failure.

The STM706P is identical to the STM706R, except its reset output is active-high.

These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.

Figure 2. Logic Diagram (STM706/706P)

	VCC
WDI		WDO
MR	STM706	RST (RST)(1)
PFI		PFO

VSS

AI08841

Note: 1. For STM706P only.

Figure 3. Logic Diagram (STM708)

VCC

RST

MR

STM708 RST

PFI

PFO

VSS

AI08842

4/25

Table 2. Signal Names

			MR					Push-button Reset Input
		WDI						Watchdog Input
								Watchdog Output
	WDO
								Active-Low Reset Output
		RST
RST(1)								Active-High Reset Output
		VCC						Supply Voltage
			PFI					Power-fail Input
								Power-fail Output
		PFO
		VSS						Ground
			NC					No Connect

Note: 1. For STM706P/708 only.

STM706/706P/708

Figure 4. STM706/706P SO8 Connections

SO8

MR			1	8		WDO
VCC			2	7		RST(RST)(1)
VSS			3	6		WDI
PFI			4	5		PFO
					AI08837

Note: 1. For STM706P reset output is active-high.

Figure 6. STM708 SO8 Connections

				SO8
						RST
	MR		1	8
VCC
			2	7			RST
VSS			3	6		NC
PFI			4	5		PFO
					AI08839

Figure 5. STM706/706P TSSOP8 Connections

					TSSOP8
RST(RST)(1)								WDI
					1	8
	WDO				2	7		PFO
		MR			3	6		PFI
	VCC				4	5		VSS
							AI08838

Note: 1. For STM706P reset output is active-high.

Table 3. Pin Description

Figure 7. STM708 TSSOP8 Connections

					TSSOP8
	RST				1	8		NC
RST
					2	7		PFO
								PFI
		MR			3	6
VCC					4	5		VSS
							AI08840

Pin

STM706P

STM706

STM708

Name

Function

SO8

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

Push-button Reset Input.

A logic low on /MR asserts the reset output. Reset

1

3

1

3

1

3

remains asserted as long as MR is low and for trec after

MR

MR

returns high. This active-low input has an internal

pull-up. It can be driven from a TTL or CMOS logic line,

or shorted to ground with a switch. Leave open if

unused.

Watchdog Input.

If WDI remains high or low for 1.6sec, the internal

watchdog timer runs out and reset (or WDO) is

6

8

6

8

–

–

WDI

triggered. The internal watchdog timer clears while

reset is asserted or when WDI sees a rising or falling

edge.

The watchdog function cannot be disabled by allowing

the WDI pin to float.

Watchdog Output.

WDO goes low when a transition does not occur on

WDI within 1.6sec, and remains low until a transition

occurs on WDI (indicating the watchdog interrupt has

been serviced). WDO also goes low when VCC falls

8

2

8

2

–

–

WDO

below the reset threshold; however, unlike the reset

output, WDO goes high as soon as VCC exceeds the

reset threshold.

Note: For those devices with a

WDO

output, a

watchdog timeout will not trigger reset unless

WDO

is

connected to MR.

5/25

STM706/706P/708

Pin

STM706P

STM706

STM708

Name

Function

SO8

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

Active-Low Reset Output.

Pulses low for trec when triggered, and stays low

whenever VCC is below the reset threshold or when

MR

–

–

7

1

7

1

RST

is a logic low. It remains low for trec after either VCC

rises above the reset threshold, the watchdog triggers a

reset, or MR goes from low to high.

7

1

–

–

8

2

RST

Active-High Reset Output.

Inverse of RST.

2

4

2

4

2

4

VCC

Supply Voltage.

PFI Power-fail Input.

4

6

4

6

4

6

PFI

When PFI is less than VPFI,

PFO

goes low; otherwise,

PFO

remains high. Connect to ground if unused.

Power-fail Output.

PFO

5

7

5

7

5

7

PFO

When PFI is less than VPFI,

PFO

goes low; otherwise,

PFO

remains high. Leave open if unused.

3

5

3

5

3

5

VSS

Ground.

–

–

–

–

6

8

NC

No Connect.

Figure 8. Block Diagram (STM706/706P)

	WDI	WATCHDOG
WDI	Transitional			WDO
		TIMER
	Detector
VCC	VRST	COMPARE
	VCC
MR			trec	RST(RST)	(1)
			Generator
PFI	VPFI	COMPARE		PFO
				AI08829

Note: 1. For STM706P only.

6/25

STM706/706P/708

Figure 9. Block Diagram (STM708)

VCC	COMPARE
VRST
		RST
VCC
MR	trec	RST
	Generator
PFI	COMPARE
VPFI		PFO
		AI08830

Figure 10. Hardware Hookup

Unregulated		Regulator
		VIN	VCC		VCC
Voltage

0.1 F

STM70X

WDI(1)

(1)

R1

WDO

To Microprocessor IRQ

From Microprocessor

R2

PFI

PFO

To Microprocessor NMI

MR

RST

To Microprocessor Reset

Push-button

RST(2)

AI08843

Note: 1. For STM706/706P.

2. For STM706P/708.

7/25

STM706/706P/708

OPERATION

Reset Output

The STM70X SUPERVISOR asserts a reset signal to the MCU whenever VCC goes below the re-

set threshold (VRST), a watchdog time-out occurs (if WDO is connected to MR), or when the Push-

button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM706P/

708) for VCC < VRST down to VCC =1V for TA = 0°C to 85°C.

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at

least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer

clears. The reset timer starts when VCC returns above the reset threshold.

Push-button Reset Input

A logic low on MR asserts reset. Reset remains

asserted while MR is low, and for trec (see Figure 30., page 18) after it returns high. The MR input

has an internal 40kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used.

Watchdog Input (STM706/706P)

The watchdog timer can be used to detect an out- of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6sec), the Watchdog Output pin (WDO) is asserted. The internal 1.6sec timer is cleared by either:

1.a reset pulse, or

2.by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns.

See Figure 31., page 18 for STM706/706P.

The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting.

8/25

Watchdog Output (STM706/706P)

When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC exceeds the reset

threshold. WDO may be used to generate a reset pulse by connecting it to the MR input.

Power-fail Input/Output

The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 10., page 7) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM70X or the microprocessor drops below the minimum operating voltage.

If the comparator is unused, PFI should be con- nected to VSS and PFO left unconnected. PFO may be connected to MR on the STM70X so that a low voltage on PFI will generate a reset output.

Ensuring a Valid Reset Output Down to VCC = 0V

When VCC falls below 1V, the state of the RST output can no longer be guaranteed, and becomes essentially an open circuit. If a high value pulldown resistor is added to the RST pin, the output will be held low during this condition. A resistor value of approximately 100kΩ will be large enough to not load the output under operating conditions, but still sufficient to pull RST to ground during this low voltage condition (see Figure 11).

Figure 11. Reset Output Valid to Ground Circuit

STM70X

RST

R1

AI08844