STMicroelectronics STA335W Technical data

2.0-channel high-efficiency digital audio system

Features

■ Wide voltage supply range

– 5 V to 26 V (operating range) – 30 V (absolute maximum rating)

■ 2 channels of ternary PWM (stereo mode) (2 x

20 W into 8 Ω at 18 V)

■ 2.0 channels of 24-bit FFX

dynamic range

■ Selectable 32 to 192 kHz input sample rates

2

■ I

C control with selectable device address

■ Digital gain/attenuation +48 dB to -80 dB with

0.5 dB/step resolution

■ Soft volume update with programmable ratio

■ Individual channel and master gain/attenuation

■ Individual channel and master soft/hard mute

■ Automatic zero-detect mute

■ Automatic invalid input-detect mute

■ 2-channel I

■ Advanced AM interference frequency

2

S input data interface

switching and noise suppression modes

■ Selectable high- or low-bandwidth

noise-shaping topologies

■ Variable max power correction for lower

full-power THD

■ Selectable clock input ratio

100 dB SNR and

STA335W

PowerSSO-36 (slug down)

■ 96 kHz internal processing sample rate, 24 to

28-bit precision

■ Thermal overload and short-circuit protection

embedded

■ Video apps: 576 x Fs input mode supported

■ Fully compatible with STA335BW (on the

common registers).

Table 1. Device summary

Order code Package Packaging

STA335W PowerSSO-36 slug down Tube

STA335W13TR PowerSSO-36 slug down Tape and reel

August 2009 Rev 1 1/43

www.st.com

3

STA335W

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STA335W

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Description FFX STA335W

1 Description FFX

The STA335W is an integrated solution of digital audio processing, digital amplifier control, and FFX -power output stage, thereby creating a high-power single-chip FFX solution comprising high-quality, high-efficiency, all digital amplification.

STA335W is based on FFX (Full Flexible Amplification) processor.

The STA335W is part of the Sound Terminal streaming to the speaker, offering cost effectiveness, low power dissipation and sound enrichment.

The STA335W power section consists of two full-bridges. The two channels can provide up to 2 x 20 W of power.

The serial audio data input interface accepts all possible formats, including the popular I format. Two channels of FFX processing are provided. This high-quality conversion from PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic range.

1.1 Block diagram

TM

family that provides full digital audio

2

S

Figure 1. Block diagram

I2C

I2S

interface

Power

Volume

control

PLL

FFX

control

Protection

current/thermal

Logic

Regulators

Bias

Channel

1A

Channel

1B

Channel

2A

Channel

2B

PowerDigital DSP

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STA335W Pin connections

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (Top view)

GND_SUB

SA

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

D05AU1638

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

NC

2.2 Pin description

Table 2. Pin description

Pin Type Name Description

1 GND GND_SUB Substrate ground

2I SA I

3 I TEST_MODE This pin must be connected to ground (pull-down)

4 I/O VSS Internal reference at Vcc-3.3 V

5 I/O VCC_REG Internal Vcc reference

6 O OUT2B Output half bridge 2B

7 GND GND2 Power negative supply

8 Power VCC2 Power positive supply

9 O OUT2A Output half bridge 2A

10 O OUT1B Output half bridge 1B

2

C select address (pull-down)

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Pin connections STA335W

Table 2. Pin description (continued)

Pin Type Name Description

11 Power VCC1 Power positive supply

12 GND GND1 Power negative supply

13 O OUT1A Output half bridge 1A

14 GND GND_REG Internal ground reference

15 Power VDD Internal 3.3 V reference voltage

16 I CONFIG Paralleled mode command

17 O N.C. Not to be connected

18 O N.C. Not to be connected

19 O N.C. Not to be connected

20 I/O N.C. Not to be connected

21 Power VDD_DIG Digital supply voltage

22 GND GND_DIG Digital ground

23 I PWRDN Power down (pull-up)

24 Power VDD_PLL Positive supply for PLL

25 I FILTER_PLL Connection to PLL filter

26 GND GND_PLL Negative supply for PLL

27 I XTI PLL input clock

2

28 I BICKI I

29 I LRCKI I

30 I SDI I

S serial clock

2

S left/right clock

2

S serial data channels 1 and 2

31 I RESET Reset (pull-up)

32 O INT_LINE Fault interrupt

2

33 I/O SDA I

34 I SCL I

C serial data

2

C serial clock

35 GND GND_DIG Digital ground

36 Power VDD_DIG Digital supply voltage

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STA335W Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

V

VDD_DIG Digital supply voltage -0.3 4 V

VDD_PLL PLL supply voltage -0.3 4

T

Power supply voltage (VCCxA, VCCxB) -0.3 30 V

cc

Operating junction temperature -20 150 °C

op

Storage temperature -40 150 °C

stg

Warning: Stresses beyond those listed in Table 3 may cause

permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating conditions” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.

3.2 Thermal data

Table 4. Thermal data

R

th j-case

T

th-sdj

T

th-w

T

th-sdh

R

th j-amb

1. See Section 7: Package thermal characteristics on page 39 for details.

Thermal resistance junction-case (thermal pad) 1.5 °C/W

Thermal shut-down junction temperature 150 °C

Thermal warning temperature 130 °C

Thermal shut-down hysteresis 20 °C

Thermal resistance junction-ambient

Parameter Min Typ Max Unit

(1)

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Electrical specifications STA335W

3.3 Recommended operating conditions

Table 5. Recommended operating condition

Symbol Parameter Min Typ Max Unit

V

Power supply voltage (VCCxA, VCCxB) 5 26 V

cc

VDD_DIG Digital supply voltage 2.7 3.3 3.6 V

VDD_PLL PLL supply voltage 2.7 3.3 3.6 V

Ambient temperature -20 70 °C

T

amb

3.4 Electrical specifications for the digital section

Table 6. Electrical specifications - digital section

Symbol Parameter Conditions Min Typ Max Unit

Low level input current without

I

il

pull-up/down device

I

V

I

R

High level input current without

ih

pull-up/down device

Low level input voltage

il

High level input voltage

ih

Low level output voltage Iol=2 mA

ol

High level output voltage Ioh=2 mA

oh

Pull-up/down current 25 66 125 µA

pu

Equivalent pull-up/down

pu

resistance

Vi = 0 V 1 10 µA

Vi = VDD_DIG = 3.6 V

0.8 *

VDD_DIG

0.8 *

VDD_DIG

110µA

0.2 *

VDD_DIG

V

0.4 *

VDD_DIG

V

50 kΩ

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STA335W Electrical specifications

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC=18V, f=1kHz, f

Table 7. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

= 384 kHz, T

sw

= 25° C and RL = 8 Ω, unless otherwise specified.

amb

Po Output power BTL

THD = 1% 16

THD = 10% 20

R

dsON

Power Pchannel/Nchannel MOSFET (total bridge)

= 1.5 A 180 250 mΩ

l

d

gP Power Pchannel RdsON matching ld = 1.5 A 95 %

gN Power Nchannel RdsON matching l

= 1.5 A 95 %

d

Idss Power Pchannel/Nchannel leakage VCC = 20 V 10 μA

(1)

8 15 ns

15 30 ns

10 18 ns

I

LDT

I

HDT

V

Low current dead time (static) Resistive load

High current dead time (dynamic) Iload = 1.5 A

Rise time Resistive load

t

r

Fall time Resistive load

t

f

Supply voltage operating voltage 5 26 V

cc

Supply current from Vcc in power down PWRDN = 0 0.1 1 mA

PCM Input signal = -

I

vcc

Supply current from Vcc in operation

60 dBfs, Switching frequency

52 60 mA

= 384 kHz, No LC filters

I

vdd

Supply current FFX processing (reference only)

Ilim Overcurrent limit

Internal clock =

49.152 MHz

(2)

55 70 mA

3.0 3.8 A

W

Isc Short circuit protection Hi-Z output 4.0 4.2 A

UVL Under voltage protection 3.5 4.3 V

t

min

Output minimum pulse width No load 20 30 60 ns

DR Dynamic range 100 dB

Signal to noise ratio, ternary mode A-Weighted 100 dB

SNR

Signal to noise ratio binary mode 90 dB

FFX stereo mode, <5 kHz

PSSR Power supply rejection ratio

V

RIPPLE

= 1 V RMS

80 dB

Audio input = dither only

FFX stereo mode,

THD+N Total harmonic distortion + noise

Po = 1 W

0.2 %

f=1kHz

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Electrical specifications STA335W

Table 7. Electrical specifications - power section (continued)

Symbol Parameter Conditions Min Typ Max Unit

FFX stereo mode, <5 kHz

X

TA L K

Crosstalk

Peak efficiency, FFX mode

η

Peak efficiency,binary modes

1. Refer to Figure 5: Test circuit 1.

2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled refer to the Isc.

One channel driven at 1 W

Other channel measured

Po = 2 x 20 W into 8 Ω

Po = 2 x 9 W into 4 Ω + 1 x 20 W into 8 Ω

80 dB

90

%

87

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STA335W Electrical specifications

3.6 Power on/off sequence

Figure 3. Power-on sequence

VCC

VDD_Dig

XTI

Reset

2

C

I

PWDN

Note: no specific VCC and VDD_DIG turn is required

Don’t care

−

on sequence

TR

Don’t care

TC

CMD0 CMD1 CMD2

TR = minimum time between XTI master clock stable and Reset removal: 1 msec TC = minimum time between Reset removal and I

Note: clock stable means: f

max

- f

< 1 MHz

min

2

C program, sequence start: 1msec

Note: see Chapter 5.2.3: Serial data first bit, for additional info.

Figure 4. Power-off sequence for pop-free turn-off

VCC

VDD_Dig

XTI

Soft Mute

Reg. 0x07

Reg. 0x07 Data 0xFE

Data 0xFE

Soft EAPD

Reg. 0x05

Reg. 0x05 Bit 7 = 0

Bit 7 = 0

Don’t care

FE

Note: no specific VCC and VDD_DIG turn is required

Don’t care

−

off sequence

Don’t care

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Electrical specifications STA335W

3.7 Testing

3.7.1 Functional pin definition

Table 8. Functional pin definition

Pin name Number Logic value IC status

PWRDN 23

TWARN 20

EAPD 19

Figure 5. Test circuit 1

Low current dead time = MAX(DTr, DTf)

Duty cycle = 50%

INxY

0 Low consumption

1 Normal operation

0

A temperature warning is indicated by the external power stage

1 Normal operation

0

Low consumption for power stage All internal regulators are switched off

1 Normal operation

OUTxY

+Vcc

DTr DTf

M58

OUTxY

M57

gnd

R 8

Ω

V67

+

vdc = Vcc/2

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

Figure 6. Test circuit 2

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Duty cycle=A Duty cycle=B

M58

DTin(A)

INA

M57

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure

12/43

Q1

Q3

OUTA

Iout=1.5A

DTout(A)

C69

470nF

+V

CC

Rload=4Ω

C71 470nF

M64

OUTB

Q2

M63

Q4

DTout(B) DTin(B)

L68 10μL67 10μ

Iout=1.5A

C70

470nF

INB

D06AU1651

STA335W I2C bus specification

4 I2C bus specification

The STA335W supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. STA335W is always a slave device in all of its communications. It supports up to 400 kb/s rate (fast-mode bit rate). STA335W I

4.1 Communication protocol

4.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.

4.1.2 Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.

2

C is a slave only interface.

4.1.3 Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA335W and the bus master.

4.1.4 Data input

During the data input the STA335W samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

4.2 Device addressing

To start communication between the master and the STA335W, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode.

The seven most significant bits are the device address identifiers, corresponding to the I bus definition. In the STA335W the I the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and to 0 for write mode. After a START condition the STA335W identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.

2

C interface has two device addresses depending on

2

C

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