STMicroelectronics ST25R3914, ST25R3915 Datasheet

ST25R3914 ST25R3915

Automotive high performance HF reader / NFC initiator with 1 W output power supporting AAT

Datasheet - production data

QFN32 / VFQFPN32

Features

AEC-Q100 qualified

ISO 18092 (NFCIP-1) Active P2P

ISO14443A, ISO14443B, ISO15693 and FeliCa™

Support HBR up to 848 kbit/s PICC to PCD and PCD to PICC framing

Capacitive sensing - Wake-up

Automatic antenna tuning system providing tuning of antenna LC tank (ST25R3914 only)

Automatic modulation index adjustment

AM and PM demodulator channels with automatic selection

Up to 1 W in case of differential output

User selectable and automatic gain control

Transparent and Stream modes to implement MIFARE™ Classic compliant or other custom protocols

Possibility of driving two antennas in single ended mode

Oscillator input capable of operating with 13.56 or 27.12 MHz crystal with fast start-up

6 Mbit/s SPI with 96 bytes FIFO

Wide supply voltage range from 2.4 to 5.5 V

Wide temperature range: -40 °C to 125 °C

ST25R3914: VFQFPN32, 5 mm x 5 mm package with wettable flanks

ST25R3915: QFN32, 5 mm x 5 mm package

Description

The ST25R3914/5 are highly integrated NFC Initiators / HF Reader ICs for automotive applications, AEC-Q100 grade 1 qualified, including the analog front end (AFE) and a highly integrated data framing system for ISO 18092 (NFCIP-1) initiator, ISO 18092 (NFCIP-1) active target, ISO 14443A and B reader (including high bit rates), ISO 15693 reader and FeliCa™ reader. Implementation of other standard and custom protocols like MIFARE™ Classic is possible using the AFE and implementing framing in the external microcontroller (Stream and Transparent modes).

The ST25R3914/5 are positioned perfectly for the infrastructure side of the NFC system, where users need optimal RF performance and flexibility combined with low power.

Thanks to automatic antenna tuning (AAT) technology, the devices are optimized for applications with directly driven antennas. The ST25R3914/5 are alone in the domain of HF reader ICs as they contain two differential low impedance (1 Ohm) antenna drivers.

The ST25R3914/5 include several features that make them very suited for low power applications. They contain a low power capacitive sensor that can be used to detect the presence of a card without switching on the reader field. The presence of a card can also be detected by performing a measurement of amplitude or phase of signal on antenna LC tank, and comparing it to the stored reference. They also contain a low power RC oscillator and wake-up timer that can be used to wake up the system after a defined time period, and to check for the presence of a tag using one or more low power detection techniques (capacitive, phase or amplitude).

The ST25R3914/5 are designed to operate from a wide (2.4 to 5.5 V) power supply range; peripheral interface IO pins support power supply range from 1.65 to 5.5 V.

April 2021

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This is information on a product in full production.

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Contents	ST25R3914/5

Contents

1	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 9
	1.1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
		1.1.1	Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.1.2	Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.1.3	Phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.1.4	A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.1.5	External field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
		1.1.6	Quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.1.7	Power supply regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.1.8	POR and bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.1.9	RC oscillator and wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.1.10	ISO-14443 and NFCIP-1 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.1.11	FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
		1.1.12	Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
		1.1.13	SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12

1.2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.4 Wake-Up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.2.5 Quartz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.2.6 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.2.7 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2.8 Phase and amplitude detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2.9 External field detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.2.10 Power supply system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2.11 Communication with an external microcontroller . . . . . . . . . . . . . . . . . . 29 1.2.12 Direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.2.13 Start timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.2.14 Test access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.2.15 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.2.16 Reader operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1.2.17 FeliCa™ reader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1.2.18 NFCIP-1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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1.2.19 AM modulation depth: definition and calibration . . . . . . . . . . . . . . . . . . 60 1.2.20 Antenna tuning (ST25R3914 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.2.21 Stream mode and Transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

1.3.1 IO configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.3.2 IO configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.3.3 Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.3.4 Mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.3.5 Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.3.6 ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . 78 1.3.7 ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.3.8 ISO14443B and FeliCa settings register . . . . . . . . . . . . . . . . . . . . . . . . 80 1.3.9 Stream mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.3.10 Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 1.3.11 Receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1.3.12 Receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1.3.13 Receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 1.3.14 Receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 1.3.15 Mask receive timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.3.16 No-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.3.17 No-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.3.18 General purpose and no-response timer control register . . . . . . . . . . . 88 1.3.19 General purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.3.20 General purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.3.21 Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.3.22 Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.3.23 Mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . 91 1.3.24 Main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.3.25 Timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 1.3.26 Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 1.3.27 FIFO status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 1.3.28 FIFO status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 1.3.29 Collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 1.3.30 Number of transmitted bytes register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 95 1.3.31 Number of transmitted bytes register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 96 1.3.32 NFCIP Bit Rate Detection Display register . . . . . . . . . . . . . . . . . . . . . . 96 1.3.33 A/D converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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	1.3.34 Antenna Calibration Control register . . . . . . . . . . . . . . . . . .		. . . . . . . . . 97
	1.3.35	Antenna Calibration Target register . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 98
	1.3.36 Antenna Calibration Display register . . . . . . . . . . . . . . . . . .		. . . . . . . . . 98
	1.3.37 AM modulation depth control register . . . . . . . . . . . . . . . . .		. . . . . . . . . 99
	1.3.38 AM modulation depth display register . . . . . . . . . . . . . . . . .		. . . . . . . . . 99
	1.3.39 RFO AM modulated level definition register . . . . . . . . . . . .		. . . . . . . . 100
	1.3.40 RFO normal level definition register . . . . . . . . . . . . . . . . . .		. . . . . . . . 100
	1.3.41 External field detector threshold register . . . . . . . . . . . . . . .		. . . . . . . . 101
	1.3.42 Regulator voltage control register . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 102
	1.3.43 Regulator and timer display register . . . . . . . . . . . . . . . . . .		. . . . . . . . 103
	1.3.44	RSSI display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 104
	1.3.45 Gain reduction state register . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 105
	1.3.46	Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 105
	1.3.47	Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 106
	1.3.48	Auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 106
	1.3.49 Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 107
	1.3.50 Amplitude measurement configuration register . . . . . . . . . .		. . . . . . . . 108
	1.3.51 Amplitude measurement reference register . . . . . . . . . . . . .		. . . . . . . . 108
	1.3.52 Amplitude measurement auto-averaging display register . .		. . . . . . . . 109
	1.3.53 Amplitude measurement display register . . . . . . . . . . . . . . .		. . . . . . . . 109
	1.3.54 Phase measurement configuration register . . . . . . . . . . . . .		. . . . . . . . 110
	1.3.55 Phase measurement reference register . . . . . . . . . . . . . . .		. . . . . . . . 110
	1.3.56 Phase measurement auto-averaging display register . . . . .		. . . . . . . . 111
	1.3.57 Phase measurement display register . . . . . . . . . . . . . . . . .		. . . . . . . . 111
	1.3.58	Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 112
	1.3.59	Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 112
	1.3.60	Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 113
	1.3.61	Reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 113
	1.3.62	IC Identity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 114
2	Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 115
3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . 117

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 3.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 3.3 DC/AC characteristics for digital inputs and outputs . . . . . . . . . . . . . . . .118

3.3.1 CMOS inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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3.3.2 CMOS outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.5.1 Thermal resistance and maximum power dissipation . . . . . . . . . . . . . 121

4	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		122
	4.1	QFN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	122
	4.2	VFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	124
5	Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		126
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		127

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List of tables	ST25R3914/5

List of tables

Table 1. First and third stage zero setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2. Low pass control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. Receiver filter selection and gain range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Recommended blocking capacitor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Serial data interface (4-wire interface) signal lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. SPI operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 8. IRQ output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9. Direct commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 10. Timing parameters of NFC Field ON commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 11. Register preset bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 12. Analog test and observation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 13. Test access register - Tana signal selection of CSI and CSO pins . . . . . . . . . . . . . . . . . . 49 Table 14. FeliCa™ frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 15. Operation mode/bit rate setting for NFCIP-1 passive communication . . . . . . . . . . . . . . . . 55 Table 16. Operation mode/bit rate setting for NFCIP-1 active communication initiator . . . . . . . . . . . 57 Table 17. Setting mod bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 18. Registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 19. IO Configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 20. IO configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 21. Operation control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 22. Mode definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 23. Initiator operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 24. Target Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 25. Bit rate definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 26. Bit rate coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 27. ISO14443A and NFC 106kb/s settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 28. ISO14443A modulation pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 29. ISO14443B settings register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 30. ISO14443B and FeliCa settings register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 31. Minimum TR1 codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 32. Stream Mode Definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 33. Sub-carrier frequency definition for Sub-Carrier and BPSK stream mode . . . . . . . . . . . . . 81 Table 34. Definition of time period for Stream mode Tx modulator control. . . . . . . . . . . . . . . . . . . . . 81 Table 35. Auxiliary definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 36. Receiver configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 37. Receiver configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 38. Receiver configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 39. Receiver configuration register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 40. Mask receive timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 41. No-response timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 42. No-response timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 43. General purpose and no-response timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 44. Timer trigger sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 45. General purpose timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 46. General purpose timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 47. Mask main interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 48. Mask timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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Table 49. Mask error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 50. Main interrupt register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 51. Timer and NFC interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 52. Error and wake-up interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 53. FIFO status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 54. FIFO status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 55. Collision display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 56. Number of transmitted bytes register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 57. Number of transmitted bytes register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 58. NFCIP Bit Rate Detection Display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 59. A/D converter output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 60. Antenna Calibration Control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 61. Antenna Calibration Target register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 62. Antenna Calibration Display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 63. AM modulation depth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 64. AM modulation depth display register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 65. RFO AM modulated level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 66. RFO normal level definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 67. External field detector threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 68. Peer detection threshold as seen on RFI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 69. Collision avoidance threshold as seen on RFI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 70. Regulator voltage control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 71. Regulator and timer display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 72. Regulated voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 73. RSSI display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 74. RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 75. Gain reduction state register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 76. Auxiliary display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 77. Wake-up timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 78. Typical wake-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 79. Amplitude measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 80. Amplitude measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 81. Amplitude measurement auto-averaging display register. . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 82. Amplitude measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 83. Phase measurement configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 84. Phase measurement reference register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 85. Phase measurement auto-averaging display register . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 86. Phase measurement display register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 87. IC Identity register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 88. ST25R3914/5 pin definitions - QFN32 and VFQFPN32 packages. . . . . . . . . . . . . . . . . . 115 Table 89. Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 90. Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 91. Temperature ranges and storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 92. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 93. CMOS inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 94. CMOS outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 95. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 96. QFN32 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 97. VFQFPN32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 98. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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List of figures	ST25R3914/5

List of figures

Figure 1. ST25R3914/5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. Minimum configuration with single sided antenna driving (including EMC filter) . . . . . . . . 12 Figure 3. Minimum configuration with differential antenna driving (including EMC filter). . . . . . . . . . 13 Figure 4. Receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. Phase detector inputs and output in case of 90º phase shift . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 6. Phase detector inputs and output in case of 135º phase shift . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7. ST25R3914/5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8. Exchange of signals with microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9. SPI communication: writing a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 10. SPI communication: writing multiple bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11. SPI communication: reading a single byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 12. SPI communication: loading of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 13. SPI communication: reading of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 14. SPI communication: direct command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 15. SPI communication: direct command chaining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 16. SPI general timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 17. SPI read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 18. Direct command NFC Initial Field ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 19. Direct command NFC Response Field ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 20. ISO14443A states for PCD and PICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 21. Selection of MRT and NRT for a given FDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 22. Flowchart for ISO14443A anticollision with ST25R3914/5 . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 23. Transport frame format according to NFCIP-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 24. Connection of tuning capacitors to the antenna LC tank . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 25. Example of sub-carrier stream mode for scf = 01b and scp = 10b . . . . . . . . . . . . . . . . . . . 68 Figure 26. Example of BPSK stream mode for scf = 01b and scp = 10b. . . . . . . . . . . . . . . . . . . . . . . 68

Figure 27. Example of Tx in Stream Mode for stx = 000b and OOK modulation . . . . . . . . . . . . . . . . . 69 Figure 28. ST25R3914/5 QFN32 and VFQFPN32 pinouts(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 29. TCASE vs. power dissipation for different copper areas at Tamb = 25 °C . . . . . . . . . . . 121 Figure 30. RthCA vs. copper area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 31. QFN32 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 32. VFQFPN32 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 33. VFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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ST25R3914/5	Functional overview

1 Functional overview

The ST25R3914/5 are suitable for a wide range of applications, among them

Access control

NFC infrastructure

Ticketing

1.1Block diagram

The block diagram is shown in Figure 1.

Figure 1. ST25R3914/5 block diagram

	VDD_IO	XTO	XTI	VDD
		XTAL			POR
				Regulators	and
		oscillator
					Bias
		Logic				RFO1
					Transmitter
						RFO2
		FIFO
SPI					Phase and
	Level	Control		A/D
IRQ					amplitude
	shifters	logic		converter	detector
MCU_CLK
		SPI			Receiver	RFI1
						RFI2
TRIMx
(only on		Framing
ST25R3914)
					External
	RC	Wake-Up			field
					detector
	oscillator	timer
					Capacitive	CSI
	ST25R3914/5				sensor	CSO
						MS42453V1
			DS11837 Rev 5			9/129

Functional overview	ST25R3914/5

1.1.1Transmitter

The transmitter incorporates drivers that drive external antenna through pins RFO1 and RFO2. Single sided and differential driving is possible. The transmitter block additionally contains a sub-block that modulates transmitted signal (OOK or configurable AM modulation).

The ST25R3914/5 transmitter is intended to directly drive antennas (without 50 Ω cable, usually antenna is on the same PCB). Operation with 50 Ω cable is also possible, but in that case some of the advanced features are not available.

By applying FFh to register 27h, the output drivers are in tristate.

1.1.2Receiver

The receiver detects transponder modulation superimposed on the 13.56 MHz carrier signal. The receiver contains two receive chains (one for AM and another for PM demodulation) composed of a peak detector followed by two gain and filtering stages and a final digitizer stage. The filter characteristics are adjusted to optimize performance for each mode and bit rate (sub-carrier frequencies from 212 kHz to 6.8 MHz are supported). The receiver chain inputs are the RFI1 and RFI2 pins. The receiver chain incorporates several features that enable reliable operation in challenging phase and noise conditions.

1.1.3Phase and amplitude detector

The phase detector is observing the phase difference between the transmitter output signals (RFO1 and RFO2) and the receiver input signals (RFI1 and RFI2). The amplitude detector is observing the amplitude of the receiver input signals (RFI1 and RFI2) via self-mixing. The amplitude of the receiver input signals (RFI1 and RFI2) is directly proportional to the amplitude of the antenna LC tank signal.

The phase detector and the amplitude detector can be used for the following purposes:

PM demodulation, by observing RFI1 and RFI2 phase variation

average phase difference between RFOx pins and RFIx pins is used to check and optimize antenna tuning

amplitude of signal present on RFI1 and RFI2 pins is used to check and optimize antenna tuning

1.1.4A/D converter

The ST25R3914/5 contain a built in Analog to Digital (A/D) converter. Its input can be multiplexed from different sources and is used in several applications, such as measurement of RF amplitude and phase, or calibration of modulation depth. The result of the A/D conversion is stored in the A/D converter output register and can be read via SPI.

1.1.5External field detector

The External field detector is a low power blockused in NFC mode to detect the presence of an external RF field. It supports two different detection thresholds, Peer Detection Threshold and Collision Avoidance Threshold. The Peer Detection Threshold is used in the NFCIP-1 target mode to detect the presence of an initiator field, and is also used in active communication initiator mode to detect the activation of the target field. The Collision Avoidance Threshold is used to detect the presence of an RF field during the NFCIP-1 RF Collision Avoidance procedure.

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1.1.6Quartz crystal oscillator

The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. At start-up the transconductance of the oscillator is increased to achieve a fast start-up. The start-up time varies with crystal type, temperature and other parameters, hence the oscillator amplitude is observed and an interrupt is sent when stable oscillator operation is reached.

The oscillator block also provides a clock signal to the external microcontroller (MCU_CLK), according to the settings in the IO configuration register 1.

1.1.7Power supply regulators

Integrated power supply regulators ensure a high power supply rejection ratio for the complete reader system. If the reader system PSRR has to be improved, the command Adjust Regulators is sent. As a result of this command, the power supply level of VDD is measured in maximum load conditions and the regulated voltage reference is set 250 mV below this measured level to assure a stable regulated supply. The resulting regulated voltage is stored in the Regulator and timer display register. It is also possible to define regulated voltage by writing to the Regulator voltage control register. To decouple any noise sources from different parts of the IC there are three regulators integrated with separated external blocking capacitors (the regulated voltage of all of them is the same in 3.3 V supply mode). One regulator is for the analog blocks, one for the digital blocks, and one for the antenna drivers.

This block additionally generates a reference voltage for the analog processing (AGD - analog ground). This voltage also has an associated external buffer capacitor.

1.1.8POR and bias

This block provides the bias current and the reference voltages to all other blocks. It also incorporates a power on reset (POR) circuit that provides a reset at power-up and at low supply voltage levels.

1.1.9RC oscillator and wake-up timer

The ST25R3914/5 includes several possibilities of low power detection of card presence (phase measurement, amplitude measurement). The RC oscillator and the register configurable wake-up timer are used to schedule the periodic card presence detection.

1.1.10ISO-14443 and NFCIP-1 framing

This block performs framing for receive and transmit according to the selected ISO mode and bit rate settings.

In reception it takes the demodulated sub-carrier signal from the receiver. It recognizes the SOF, EOF and data bits, performs parity and CRC check, organizes the received data in bytes and places them in the FIFO.

During transmit, it operates inversely, it takes bytes from the FIFO, generates parity and CRC bits, adds SOF and EOF and performs final encoding before passing the modulation signal to the transmitter.

In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal (the receiver output), is directly sent to the MISO pin, and the signal applied to the MOSI pin is directly used to modulate the transmitter.

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Functional overview	ST25R3914/5

1.1.11FIFO

The ST25R3914/5 contain a 96-byte FIFO. Depending on the mode, it contains either data that has been received or data to be transmitted.

1.1.12Control logic

The control logic contains I/O registers that define operation of device.

1.1.13SPI

A 4-wire serial peripheral interface (SPI) is used for communication between the external microcontroller and the ST25R3914/5.

1.2Application information

The minimum configurations required to operate the ST25R3914/5 are shown in Figure 2 and Figure 3.

Figure 2. Minimum configuration with single sided antenna driving (including EMC filter)

1.65 to 5.5 V	2.4 to 5.5 V
	VDD_IO	VDD	AGD
	/SS
MCU	MISO		VSS
	MOSI		VSP_A
	SCLK
	IRQ		VSN_A
	MCU_CLK
	XTI		VSP_D
			VSN_D
	XTO		VSP_RF	Antenna
			VSN_RF
	TRIM1_x / NC			coil
	TRIM2_x / NC		RF01
			RF02
			RFI1
	ST25R3914/5		RFI2
				MS42455V1

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Figure 3. Minimum configuration with differential antenna driving (including EMC filter)

1.65 to 5.5 V	2.4 to 5.5 V
	VDD_IO	VDD	AGD
	/SS
MCU	MISO		VSS
	MOSI		VSP_A
	SCLK
	IRQ		VSN_A
	MCU_CLK
	XTI		VSP_D
			VSN_D
	XTO		VSP_RF
	TRIM1_x / NC		VSN_RF	Antenna
				coil
	TRIM2_x / NC
			RF01
			RF02
			RFI1
			RFI2
	ST25R3914/5
				MS42456V1

1.2.1Operating modes

The ST25R3914/5 operating mode is defined by the contents of the Operation control register.

At power-up all bits of the Operation control register are set to 0, the ST25R3914/5 are in Power-down mode. In this mode AFE static power consumption is minimized, only the POR and part of the bias are active, while the regulators are transparent and are not operating. The SPI is still functional in this mode so all settings of ISO mode definition and configuration registers can be done.

Control bit en (bit 7 of the Operation control register) is controlling the quartz crystal oscillator and regulators. When this bit is set, the device enters in Ready mode. In this mode the quartz crystal oscillator and regulators are enabled. An interrupt is sent to inform the microcontroller when the oscillator frequency is stable.

Enable of receiver and transmitter are separated so it is possible to operate one without switching on the other (control bits rx_en and tx_en). In some cases this may be useful, if the reader field has to be maintained and there is no transponder response expected, the receiver can be switched-off to save current. Another example is the NFCIP-1 active communication receive mode in which the RF field is generated by the initiator and only the receiver operates.

Asserting the Operation control register bit wu while the other bits are set to 0 puts the ST25R3914/5 into the Wake-Up mode that is used to perform low power detection of card presence. In this mode the low power RC oscillator and register configurable Wake-Up timer

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are used to schedule periodic measurement(s). When a difference of the measured value vs. the predefined reference is detected an interrupt is sent to wake-up the microcontroller.

1.2.2Transmitter

The transmitter contains two identical push-pull driver blocks connected to the pins RFO1 and RFO2. These drivers are differentially driving the external antenna LC tank. It is also possible to operate only one of the two drivers by setting the IO configuration register 1 bit single to 1. Each driver is composed of eight segments having binary weighted output resistance. The MSB segment typical ON resistance is 2 Ω, when all segments are turned on; the output resistance is typically 1 Ω. All segments are turned on to define the normal transmission (non-modulated) level. It is also possible to switch off certain segments when driving the non-modulated level to reduce the amplitude of the signal on the antenna and/or to reduce the antenna Q factor without making any hardware changes. The RFO normal level definition register defines which segments are turned on to define the normal transmission (non-modulated) level. Default setting is that all segments are turned on.

Using the single driver mode the number of the antenna LC tank components (and therefore the cost) is halved, but also the output power is reduced. In single mode it is possible to connect two antenna LC tanks to the two RFO outputs and multiplex between them by controlling the IO configuration register 1 bit rfo2.

In order to transmit the data the transmitter output level needs to be modulated. Both AM and OOK modulation are supported. The type of modulation is defined by setting the bit tr_am in the Auxiliary definition register.

During the OOK modulation (for example ISO14443A) the transmitter drivers stop driving the carrier frequency. As consequence the amplitude of the antenna LC tank oscillation decays, the time constant of the decay is defined with the LC tank Q factor. The decay time in case of OOK modulation can be shortened by asserting the Auxiliary definition register bit ook_hr. When this bit is set to logic one the drivers are put in tristate during the OOK modulation.

AM modulation (for example ISO14443B) is done by increasing the output driver impedance during the modulation time. This is done by reducing the number of driver segments that are turned on. The AM modulated level can be automatically adjusted to the target modulation depth by defining the target modulation depth in the AM modulation depth control register and sending the Calibrate Modulation Depth direct command. Refer to Section 1.2.19: AM modulation depth: definition and calibration for further details.

Slow transmitter ramping

When the transmitter is enabled it starts to drive the antenna LC tank with full power, the ramping of the field emitted by antenna is defined by antenna LC tank Q factor.

However there are some reader systems where the reader field has to ramp up with a longer transition time when it is enabled. The STIF (Syndicat des transports d'Ile de France) specification requires a transition time from 10% to 90% of field longer than or equal to

10 μs.The ST25R3914/5 supports that feature. It is realized by collapsing VSP_RF regulated voltage when transmitter is disabled and ramping it when transmitter is enabled. Typical transition time is 15 μs at 3 V supply and 20 μs at 5 V supply.

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Procedure to implement the slow transition:

1.When transmitter is disabled set IO configuration register 2 bit slow_up to 1. Keep this state for at least 2 ms to allow discharge of VSP_RF.

2.Enable transmitter, its output will ramp slowly.

3.Before sending any command set the bit slow_up back to 0.

1.2.3Receiver

The receiver performs demodulation of the transponder sub-carrier modulation that is superimposed on the 13.56 MHz carrier frequency. It performs AM and/or PM demodulation, amplification, band-pass filtering and digitalization of sub-carrier signals. Additionally it performs RSSI measurement, automatic gain control (AGC) and Squelch.

In typical applications the receiver inputs RFI1 and RFI2 are outputs of capacitor dividers connected directly to the terminals of the antenna coil. This concept ensures that the two input signals are in phase with the voltage on the antenna coil. The design of the capacitive divider must ensure that the RFI1 and RFI2 input signal peak values do not exceed the

V supply voltage level.

The receiver comprises two complete receive channels, one for the AM demodulation and another one for the PM demodulation. In case both channels are active the selection of the channel used for reception framing is done automatically by the receive framing logic. The receiver is switched on when Operation control register bit rx_en is set to one. Additionally the Operation control register contains bits rx_chn and rx_man; rx_chn defines whether both, AM and PM, demodulation channels will be active or only one of them, while bit rx_man defines the channel selection mode in case both channels are active (automatic or manual). Operation of the receiver is controlled by four receiver configuration registers.

The operation of the receiver is additionally controlled by the signal rx_on that is set high when a modulated signal is expected on the receiver input. This signal is used to control RSSI and AGC and also enables processing of the receiver output by the framing logic.

Signal rx_on is automatically set to high after the Mask Receive Timer expires. Signal rx_on can also be directly controlled by the controller by sending direct commands Mask Receive Data and Unmask Receive Data. Figure 4 details the receiver block diagram.

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Figure 4. Receiver block diagram

	AM	rec1<7:6>
		rec2<6:5>
	Demodulator
	Mixer
						rec4<7:4>
		rec3<7:5>				AGC	RSSI_AM<3:0>
		M
		U				Squelch
						RSSI
RF_IN1		X
	Peak detector
							Digital sub-carrier
					RX_on
RF_IN2					sg_on	rec4<3:0>
		rec3<4:2>				AGC	RSSI_PM<3:0>
	PM					Squelch
	Demodulator					RSSI
	Mixer
							Digital sub-carrier
		rec3<2:0>	rec1<5:3>
	Demodulation	AC coupling	Low-pass	High-pass	Digitizing
	stage	+ 1st gain stage	+ 2nd gain stage	+ 3rd gain stage	stage
							MS42452V1

Demodulation stage

The first stage performs demodulation of the transponder sub-carrier signal, superimposed on the HF field carrier. Two different blocks are implemented for AM demodulation:

Peak detector

AM demodulator mixer.

The choice of the used demodulator is made by the Receiver configuration register 1 bit amd_sel.

The peak detector performs AM demodulation using a peak follower. Both the positive and negative peaks are tracked to suppress any common mode signal. The peak detector is limited in speed; it can operate for sub-carrier frequencies up to fc / 8 (1700 kHz). Its demodulation gain is G = 0.7. Its input is taken from one demodulator input only (usually RFI1).

The AM demodulator mixer uses synchronous rectification of both receiver inputs (RFI1 and RFI2). Its gain is G = 0.55.

By default the Peak detector is used, for data rates fc/8 and higher use of mixer is automatically preset by sending the direct command Analog Preset.

PM demodulation is also done by a mixer. The PM demodulator mixer has differential outputs with 60 mV differential signal for 1% phase change (16.67 mV / °). Its operation is optimized for sub-carrier frequencies up to fc / 8 (1700 kHz).

In case the demodulation is done externally, it is possible to multiplex the LF signals applied to pins RFI1 and RFI2 directly to the gain and filtering stage by selecting the Receiver configuration register 2 bit lf_en.

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Filtering and gain stages

The receiver chain has band pass filtering characteristics. Filtering is optimized to pass sub-carrier frequencies while rejecting carrier frequency and low frequency noise and DC component. Filtering and gain is implemented in three stages, where the first and the last stage have first order high pass characteristics, and the second stage has second order low pass characteristic.

Gain and filtering characteristics can be optimized by writing the Receiver configuration register 1 (filtering), the Receiver configuration register 3 (gain in first stage) and the Receiver configuration register 4 (gain in second and third stage).

The gain of the first stage is about 20 dB and can be reduced in six 2.5 dB steps. There is also a special boost mode available, which boosts the maximum gain by additional 5.5 dB. The first stage gain can only be modified by writing Receiver configuration register 3. The default setting of this register is the minimum gain. The default first stage zero is set at 60 kHz, it can also be lowered to 40 kHz or to 12 kHz by writing option bits in the Receiver configuration register 1. The control of the first and third stage zeros is done with common control bits (see Table 1).

Table 1. First and third stage zero setting

rec1<2> h200	rec1<1> h80	rec1<0> z12k	First stage zero	Third stage zero
0	0	0	60 kHz	400 kHz
1	0	0	60 kHz	200 kHz
0	1	0	40 kHz	80 kHz
0	0	1	12 kHz	200 kHz
0	1	1	12 kHz	80 kHz
1	0	1	12 kHz	200 kHz
	Others		Not used

The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. The gain of these two stages is included in the AGC and Squelch loops. It can also be manually set in Receiver configuration register 4. Sending of direct command Reset Rx Gain is necessary to reset the AGC, Squelch and RSSI block. Sending this command clears the current Squelch setting and loads the gain reduction configuration from Receiver configuration register 4 into the internal shadow registers of the AGC and Squelch block. The second stage has a second order low pass filtering characteristic, the pass band is adjusted according to the sub-carrier frequency using the bits lp2 to lp0 of the Receiver configuration register 1.

See Table 2 for -1 dB cut-off frequency for different settings.

Table 2. Low pass control

rec1<5> lp2	rec1<4> lp1	rec1<3> lp0	-1 dB point
0	0	0	1200 kHz
0	0	1	600 kHz
0	1	0	300 kHz

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		Table 2. Low pass control (continued)
	rec1<5> lp2	rec1<4> lp1	rec1<3> lp0	-1 dB point
	1	0	0	2 MHz
	1	0	1	7 MHz
		Others		Not used

Table 3 provides information on the recommended filter settings. For all supported operation modes and receive bit rates there is an automatic preset defined, additionally some alternatives are listed. Automatic preset is done by sending direct command Analog Preset. There is no automatic preset for Stream and Transparent modes. Since the selection ofthe filter characteristics also modifies gain, the gain range for different filter settings is also listed.

Table 3. Receiver filter selection and gain range

<![if ! IE]> <![endif]>rec1<5:3>lp<2:0>	<![if ! IE]> <![endif]>rec1<2>h200		<![if ! IE]> <![endif]>rec1<0>z12k			Gain (dB)
		<![if ! IE]> <![endif]>rec1<1>h80									Comments
				Max	Min1		Max1		Min	With
				all	Max23		Min23		all	boost
000	0	0	0	43.4	28.0		26.4		11.0	49.8	Automatic preset for ISO14443A fc / 128 and NFC
											Forum Type 1 Tag
000	1	0	0	44.0	29.0		27.5		12.0	49.7	Automatic preset for ISO14443B fc / 128
											ISO14443 fc / 64
001	1	0	0	44.3	29		27.0		11.7	49.8	Recommended for 424/484 kHz sub-carrier
000	0	1	0	41.1	25.8		23.6		8.3	46.8	Alternative choice for ISO14443 fc / 32 and fc / 16
100	0	1	0	32.0	17.0		17.2		2.0	37.6	Automatic preset for ISO14443 fc / 32 and fc / 16
											Alternative choice for fc / 8 (1.7 kb/s)
100	0	0	0	32.0	17.0		17.2		2.0	37.6	Alternative choice for fc / 8 (1.7 kb/s)
000	0	1	1	41.1	25.8		23.6		8.3	46.8	Automatic preset FeliCa™ (fc / 64, fc / 32)
											Alternative choice for ISO14443 fc / 32 and fc / 16
101	0	1	0	30.0	20.0		12.0		2.0	34.0	Alternative choice for fc / 8 and fc / 4
101	1	0	0	30.0	20.0		12.0		2.0	34.0	Automatic preset for fc / 8 and fc / 4
000	1	0	1	36.5	21.5		24.9		9.9	41.5	Automatic preset for NFCIP-1 (initiator and target)

Digitizing stage

The digitizing stage produces a digital representation of the sub-carrier signal coming from the receiver. This digital signal is then processed by the receiver framing logic. The digitizing stage consists of a window comparator with adjustable digitizing window (five possible settings, 3 dB steps, adjustment range from ±33 mV to ±120 mV). Adjustment of the digitizing window is included in the AGC and Squelch loops. In addition, the digitizing window can also be set manually in the Receiver configuration register 4.

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AGC, Squelch and RSSI

As mentioned above, the second and third gain stage gain and the digitizing stage window are included in the AGC and Squelch loops. Eleven settings are available. The default state features minimum digitizer window and maximum gain. The first four steps increase the digitizer window in 3 dB steps, the next six steps additionally reduce the gain in the second and third gain stage, again in 3 dB steps. The initial setting with whom Squelch and AGC start is defined in Receiver configuration register 4. The Gain reduction state register displays the actual state of gain that results from Squelch, AGC and initial settings in Receiver configuration register 4. During bit anticollision like Type A, the AGC should be disabled.

Squelch

This feature is designed for operation of the receiver in noisy conditions. The noise can come from tags (caused by the processing of reader commands), or it can come from a noisy environment. This noise may be misinterpreted as start of transponder response, resulting in decoding errors.

During execution of the Squelch procedure the output of the digitizing comparator is observed. In case there are more than two transitions on this output in a 50 μs time period, the receiver gain is reduced by 3 dB, and the output is observed during the next 50 μs. This procedure is repeated until the number of transitions in 50 μs is lower or equal to two, or until the maximum gain reduction is reached. This gain reduction can be cleared sending the direct command Reset Rx Gain.

There are two possibilities of performing squelch: automatic mode and using the direct command Squelch.

1.Automatic mode is enabled in case bit sqm_dyn in the Receiver configuration register 2 is set. It is activated automatically 18.88 μs after end of Tx and is terminated when the Mask Receive timer expires. This mode is primarily intended to suppress noise generated by tag processing during the time when a tag response is not expected (covered by Mask Receive timer).

2.Command Squelch is accepted in case it is sent when signal rx_on is low. It can be used when the time window in which noise is present is known by the controller.

AGC (automatic gain control)

AGC is used to reduce gain to keep the receiver chain out of saturation. With gain properly adjusted the demodulation process is also less influenced by system noise.

AGC action starts when signal rx_on is asserted high and is reset when it is reset to low. At the high to low transitions of the rx_on signal the state of the receiver gain is stored in the Gain reduction state register. Reading this register at a later stage gives information on the gain setting used during last reception.

When AGC is switched on the receiver gain is reduced so that the input to the digitizer stage is not saturated. The AGC system comprises a comparator with a window 3.5 times larger than that of the digitizing window comparator. When the AGC function is enabled the gain is reduced until there are no transitions on the output of its window comparator. This procedure ensures that the input to the digitizing window comparator is less than 3.5 times larger than its threshold.

AGC operation is controlled by the control bits agc_en, agc_m and agc_fast in the Receiver configuration register 2. Bit agc_en enables the AGC operation, bit agc_m defines the AGC mode, and bit agc_alg defines the AGC algorithm.

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Two AGC modes are available. The AGC can operate during the complete Rx process (as long as signal rx_on is high), or it can be enabled only during the first eight sub-carrier pulses.

Two AGC algorithms are available. The AGC can either start by presetting code 4h (max digitizer window, max gain) or by resetting the code to 0h (min digitizer window, max gain).

The algorithm with preset code is faster, therefore it is recommended for protocols with short SOF (like ISO14443A fc / 128).

Default AGC settings are:

AGC is enabled

AGC operates during complete Rx process

algorithm with preset is used.

RSSI

The receiver also performs the RSSI (received signal strength indicator) measurement for both channels. The RSSI measurement is started after the rising edge of rx_on. It stays active as long as signal rx_on is high, it is frozen while rx_on is low. The RSSI is a peak hold system, and the value can only increase from the initial zero value. Every time the AGC reduces the gain the RSSI measurement is reset and starts from zero. Result of RSSI measurements is a 4-bit value that can be observed by reading the RSSI display register. The LSB step is 2.8 dB, and the maximum code is Dh (13d).

Since the RSSI measurement is of peak hold type the RSSI measurement result does not follow any variations in the signal strength (the highest value will be kept). In order to follow RSSI variations it is possible to reset the RSSI bits and restart the measurement by sending the direct command Clear RSSI.

Receiver in NFCIP-1 active communication mode

There are several features built into the receiver to enable reliable reception of active NFCIP-1 communication. All these settings are automatically preset by sending the direct command Analog Preset after the NFCIP-1 mode has been configured. In addition to the filtering options, there are two NFCIP-1 active communication mode specific configuration bits stored in the Receiver configuration register 3.

Bit lim enables clipping circuits that are positioned after the first and second gain stages. The function of the clipping circuits is to limit the signal level for the following filtering stage (when the NFCIP-1 peer is close the input signal level can be quite high).

Bit rg_nfc forces gain reduction of second and third filtering stage to -6 dB while keeping the digitizer comparator window at maximum level.

1.2.4Wake-Up mode

Asserting the Operation control register bit wu while the other bits are set to 0 puts the ST25R3914/5 in Wake-Up mode, used to perform low power detection of card presence. The ST25R3914/5 include several possibilities of low power detection of a card presence ( phase measurement, amplitude measurement). An integrated low power 32 kHz RC oscillator and a register configurable Wake-Up timer are used to schedule periodic detection.

Usually the presence of a card is detected by a so-called polling loop. In this process the reader field is periodically turned on and the controller checks whether a card is present

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using RF commands. This procedure consumes a lot of energy since the reader field has to be turned on for 5 ms before a command can be issued.

Low power detection of card presence is performed by detecting a change in the reader environment, produced by a card. When a change is detected, an interrupt is sent to the controller. As a result, the controller can perform a regular polling loop.

In the Wake-Up mode the ST25R3914/5 periodically perform the configured reader environment measurements and sends an IRQ to the controller when a difference to the configured reference value is detected.

Detection of card presence can be done by performing phase, amplitude and capacitive sensor measurements.

Presence of a card close to the reader antenna coil produces a change of the antenna LC tank signal phase and amplitude. The reader field activation time needed to perform the phase or the amplitude measurement is extremely short (~20 μs) compared to the activation time needed to send a protocol activation command.

Additionally the power level during the measurement can be lower than the power level during normal operation since the card does not have to be powered to produce a coupling effect. The emitted power can be reduced by changing the RFO normal level definition register.

The registers on locations from 31h to 3Dh are dedicated to Wake-Up timer configuration and display. The Wake-up timer control register is the main Wake-Up mode configuration register. The timeout period between the successive detections and the measurements are selected in this register. Timeouts in the range from 10 to 800 ms are available, 100 ms is the default value. Any combination of available measurements can be selected (one, two or all of them).

The next twelve registers (32h to 3Dh) are configuring the three possible detection measurements and storing the results, four registers are used for each measurement.

An IRQ is sent when the difference between a measured value and the reference value is larger than the configured threshold value. There are two possible definitions for the reference value:

1.The ST25R3914/5 can calculate the reference based on previous measurements (auto-averaging)

2.The controller determines the reference and stores it in a register

The first register in the series of four is the Amplitude measurement configuration register. The difference to the reference value that triggers the IRQ, the method of reference value definition and the weight of the last measurement result in case of auto-averaging are defined in this register. The next register is storing the reference value in case the reference is defined by the controller. The following two registers are display registers. The first one stores the auto-averaging reference, and the second one stores the result of the last measurement.

The Wake-Up mode configuration registers have to be configured before the Wake-Up mode is entered. Any modification of the Wake-Up mode configuration while it is active may result in unpredictable behavior.

Auto-averaging

In case of auto-averaging the reference value is recalculated after every measurement as

NewAverage = OldAverage + (MeasuredValue - OldAverage) / Weight

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The calculation is done on 13 bits to have sufficient precision.The auto-averaging process is initialized when the Wake-Up mode is entered for the first time after initialization (at powerup or after Set Default command). The initial value is taken from the measurement display registers (for example Amplitude measurement display register) until the content of this register is not zero.

Every Measurement Configuration register contains a bit that defines whether the measurement that causes an interrupt is taken in account for the average value calculation (for example bit am_aam of the Amplitude measurement configuration register).

1.2.5Quartz crystal oscillator

The quartz crystal oscillator can operate with 13.56 MHz and 27.12 MHz crystals. The operation of quartz crystal oscillator is enabled when the Operation control register bit en is set to one. An interrupt is sent to inform the microcontroller when the oscillator frequency is stable (see Section 1.3.24: Main interrupt register).

The status of oscillator can be observed by observing the Auxiliary display register bit osc_ok. This bit is set to ‘1’ when oscillator frequency is stable.

The oscillator is based on an inverter stage supplied by a controlled current source. A feedback loop is controlling the bias current in order to regulate amplitude on XTI pin to 1 Vpp.

This feedback assures reliable operation even in case of low quality crystals, with Rs up to 50 Ω. To enable a fast reader start-up an interrupt is sent when the oscillator amplitude exceeds 750 mVpp.

Division by two ensures that 13.56 MHz signal has a duty cycle of 50%, which is better for the transmitter performance (no PW distortion). Use of 27.12 MHz crystal is therefore recommended for better performance.

In case of 13.56 MHz crystal, the bias current of stage that is digitizing oscillator signal is increased to assure as low PW distortion as possible.

The oscillator output is also used to drive a clock signal output pin MCU_CLK) that can be used by the external microcontroller. The MCU_CLK pin is configured in the IO configuration register 2.

1.2.6Timers

	The ST25R3914/5 contains several timers that eliminate the need to run counters in the
	controller, thus reducing the effort of the controller code implementation and improve
	portability of code to different controllers.
	Every timer has one or more associated configuration registers in which the timeout
	duration and different operating modes are defined. These configuration registers have to
	be set while the corresponding timer is not running. Any modification of timer configuration
	while the timer is active may result in unpredictable behavior.
	All timers except the Wake-Up timer are stopped by direct command Clear.
Note:	In case bit nrt_emv in the General purpose and no-response timer control register is set to
	one, the No-response timer is not stopped

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Mask receive timer and No-response timer

Mask receive timer and No-response timer are both automatically started at the end of transmission (at the end of EOF).

Mask receive timer

The Mask receive timer is blocking the receiver and reception process in framing logic by keeping the rx_on signal low after the end of Tx during the time the tag reply is not expected.

While the Mask Receive timer is running, the Squelch is automatically turned on (if enabled). Mask Receive timer does not produce an IRQ.

The Mask Receive timer timeout is configured in the Mask receive timer register.

In the NFCIP-1 active communication mode the Mask Receive timer is started when the peer NFC device (a device with whom communication is going on) switches on its field.

The Mask Receive timer has a special use in the low power Initial NFC Target Mode. After the initiator field has been detected the controller turns on the oscillator, regulator and receiver. Mask Receive timer is started by sending direct command Start Mask Receive Timer. After the Mask Receive Timer expires the receiver output starts to be observed to detect start of the initiator message. In this mode the Mask Receive timer clock is additionally divided by eight it (one count is 512/fc) to cover range up to about 9.6 ms.

No-response timer

As its name indicates, this timer is intended to observe whether a tag response is detected in a configured time started by end of transmission. The I_nre flag in the Timer and NFC interrupt register is signaling interrupt events resulting from this timer timeout.

The No-response timer is configured by writing the two registers No-response timer register 1 and No-response timer register 2. Operation options of the No-response timer are defined by setting bits nrt_emv and nrt_step in the General purpose and no-response timer control register.

Bit nrt_step configures the time step of the No-response timer. Two steps are available, 64/fc (4.72 μs) to cover range up to 309 ms, and 4096/fc, covering the range up to 19.8 s.

Bit nrt_emv controls the timer operation mode:

When this bit is set to 0 (default mode) the IRQ is produced in case the No-response timer expires before a start of a tag reply is detected and rx_on is forced to low to stop receiver process. In the opposite case, when start of a tag reply is detected before timeout, the timer is stopped, and no IRQ is produced.

When this bit is set to 1 the timer unconditionally produces an IRQ when it expires, it is also not stopped by direct command Clear. This means that IRQ is independent of the fact whether or not a tag reply was detected. In case at the moment of timeout a tag reply is being processed no other action is taken, in the opposite case, when no tag response is being processed additionally the signal rx_on is forced to low to stop receive process.

The No-response timer can also be started using direct command Start No-Response Timer. The intention of this command is to extend the No-response timer timeout beyond the range defined in the No-response timer control registers. In case this command is sent while the timer is running, it is reset and restarted. In NFCIP-1 active communication mode the Noresponse timer cannot be started using the direct command.

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	In case this timer expires before the peer NFC device (a device with whom communication
	is going on) switches on its field an interrupt is sent.
	In all modes, where timer is set to nonzero value, it is a must that M_txe is not set and
	interrupt I_txe is read via SPI for synchronization between transmitter and timer.
	General Purpose timer
	The triggering of the General Purpose timer is configured by setting the General purpose
	and no-response timer control register. It can be used to survey the duration of the reception
	process (triggering by start of reception, after SOF) or to time out the PCD to PICC
	response time (triggered by end of reception, after EOF). In the NFCIP-1 active
	communication mode it is used to timeout the field switching off. In all cases an IRQ is sent
	when it expires.
	The General Purpose timer can also be started by sending the direct command Start
	General Purpose Timer. In case this command is sent while the timer is running, it is reset
	and restarted.
	Wake-Up timer
	Wake timer is primarily used in the Wake-Up mode (see Section 1.2.4: Wake-Up mode).
	Additionally it can be used by sending a direct command Start Wake-Up Timer. This
	command is accepted in any operation mode except Wake-Up mode. When this command
	is sent the RC oscillator used as clock source for Wake-Up timer is started, timeout is
	defined by setting in the Wake-up timer control register. When the timer expires, an IRQ with
	the I_wt flag in the Error and wake-up interrupt register is sent.
	Wake-Up timer is useful in the Low Power operation mode, in which other timers cannot be
	used (in the Low Power operation mode the crystal oscillator, which is clock source for the
	other timers, is not running).
Note:	The tolerance of Wake-Up timer timeout is defined by tolerance of the RC oscillator.
1.2.7	A/D converter
	The ST25R3914/5 contain an 8-bit successive approximation A/D converter, whose inputs
	can be multiplexed from different sources to be used in several direct commands and
	adjustment procedures. The result of the last A/D conversion is stored in the A/D converter
	output register.
	The A/D converter has two operating modes, absolute and relative.
	In absolute mode the low reference is 0 V and the high reference is 2 V. This means
	that A/D converter input range is from 0 to 2 V, 00h code means input is 0 V or lower,
	FFh means that input is 2 V - 1 LSB or higher (LSB is 7.8125 mV).
	In relative mode low reference is 1/6 of VSP_A and high reference is 5/6 of VSP_A, so
	the input range is from 1/6 to 5/6 VSP_A.
	Relative mode is only used in phase measurement (phase detector output is proportional to
	power supply). In all other cases absolute mode is used.
1.2.8	Phase and amplitude detector
	This block is used to provide input to A/D converter to perform measurements of amplitude
	and phase, expected by direct commands Measure Amplitude and Measure Phase. Several

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phase and amplitude measurements are also performed by direct commands Calibrate Modulation Depth and Calibrate Antenna (ST25R3914 only).

Phase detector

The phase detector is observing phase difference between the transmitter output signals (RFO1 and RFO2) and the receiver input signals RFI1 and RFI2, which are proportional to the signal on the antenna LC tank. These signals are first elaborated by digitizing comparators, then digitized signals are processed by a phase detector with a strong low pass filter to get average phase difference.

The phase detector output is inversely proportional to the phase difference between the two inputs. The 90° phase shift results in VSP_A/2 output voltage, in case both inputs are in phase output voltage is VSP_A, in case they are in opposite phase output voltage is 0 V. During execution of direct command Measure Phase this output is multiplexed to A/D converter input (A/D converter is in relative mode during execution of command Measure Phase). Since the A/D converter range is from 1/6 to 5/6 VSP_A the actual phase detector range is from 30º to 150º.

Figure 5 and Figure 6 show the two inputs and the output of phase detector, respectively, in case of 90º and 135º shifts.

Figure 5. Phase detector inputs and output in case of 90º phase shift

VSP_A

Input 1

0

VSP_A

Input 2

0

VSP_A

Output VSP_A/2

0

MS42426V1

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Figure 6. Phase detector inputs and output in case of 135º phase shift

VSP_A

Input 1

0

VSP_A

Input 2

0

VSP_A

Output VSP_A/2

0

MS42427V1

Amplitude detector

Signals from pins RFI1 and RFI2 are used as inputs to the self-mixing stage. The output of this stage is a DC voltage proportional to amplitude of signal on pins RFI1 and RFI2. During execution of direct command Measure Amplitude this output is multiplexed to A/D converter input.

1.2.9External field detector

The External Field Detector is used to detect the presence of an external device generating an RF field. It is automatically switched on in NFCIP-1 active communication modes; it can also be used in other modes. The External field detector supports two different detection thresholds, Peer Detection Threshold and Collision Avoidance Threshold. The two thresholds can be independently set by writing the External field detector threshold register. The actual state of the External field detector output can be checked by reading the Auxiliary display register. Input to this block is the signal from the RFI1 pin.

Peer detection threshold

This threshold is used to detect the field emitted by peer NFC device with whom NFC communication is going on (initiator field in case the ST25R3914/5 is the target and the opposite, target field in case the ST25R3914/5 is the initiator). It can be selected in the range from 75 to 800 mVpp. When this threshold is enabled the External Field Detector is in low power mode. An interrupt is generated when an external field is detected and also when it is switched off. With such implementation it can also be used to detect the moment when the external field disappears. This is useful to detect the moment when the peer NFC device (it can be either an initiator or a target) has stopped emitting an RF field.

The External Field Detector is automatically enabled in the low power Peer Detection mode when NFCIP-1 mode (initiator or target) is selected in the Bit rate definition register.

Additionally it can be enabled by setting bit en_fd in the Auxiliary definition register.

Collision Avoidance threshold

This threshold is used during the RF Collision Avoidance sequence that is executed by sending NFC Field ON commands (see NFC Field ON commands). It can be selected in the range from 25 to 800 mVpp.

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1.2.10Power supply system

The ST25R3914/5 (Figure 7) features two positive supply pins, VDD and VDD_IO.

VDD is the main power supply pin. It supplies the ST25R3914/5 blocks through three regulators (VSP_A, VSP_D and VSP_RF).

VDD range from 2.4 to 5.5 V is supported.

VDD_IO is used to define supply level for digital communication pins (/SS, MISO, MOSI, SCLK, IRQ, MCU_CLK). Digital communication pins interface with ST25R3914/5 logic through level shifters, therefore the internal supply voltage can be either higher or lower than VDD_IO. VDD_IO range from 1.65 to 5.5 V is supported.

Figure 7. ST25R3914/5 power supply

					VDD
	EN
	sup3V
					1 kΩ
	VSP_D	Power-down	VSP_A	VSP_RF	VSP_RF
	REG	support	REG	REG
			50 Ω		VSP_A
	BGR				VSP_D
					AGD
	and
	AGC
	RV<3:0>
	AUTOREG				reg 2Bh
	reg 2Ah
	adjust				MS42462V1

Figure 7 shows the building blocks of the ST25R3914/5 power supply system and the signals that control it.

The power supply system contains three regulators, a power-down support block, a block generating analog reference voltage (AGD) and a block performing automatic power supply adjustment procedure. The three regulators are providing supply to analog blocks (VSP_A), logic (VSP_D) and transmitter (VSP_RF). The use of VSP_A and VSP_D regulators is mandatory at 5 V power supply to provide regulated voltage to analog and logic blocks that only use 3.3 V devices. The use of VSP_A and VSP_D regulators at 3 V supply and VSP_RF regulator at any supply voltage is recommended to improve system PSRR.

Regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having good PSRR. All regulator pins also have corresponding negative supply pins that are externally connected to ground potential (VSS). The reason for separation is in decoupling of noise induced by voltage drops on the internal power supply lines.

Figure 2 and Figure 3 show typical ST25R3914/5 application schematics with all regulators used. All regulator pins and AGD voltage are buffered with capacitors. Recommended blocking capacitor values are detailed in Table 4.

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		Table 4. Recommended blocking capacitor values
	Pins		Recommended capacitors
	AGD - VSS		1 μF, in parallel with 10 nF
	VSP_A - VSN_A		2.2 μF, in parallel with 10 nF
	VSP_D - VSN_D		2.2 μF, in parallel with 10 nF
	VSP_RF - VSN_RF		2.2 μF, in parallel with 10 nF

Regulators have two basic operation modes depending on supply voltage, 3.3 V supply mode (max 3.6 V) and 5 V supply mode (max 5.5 V). The supply mode is set by writing bit sup3 V in the IO configuration register 2. Default setting is 5 V, hence this bit has to be set to one after power-up in case of 3.3 V supply.

In 3.3

3.4 V,

VSP_D

V mode all regulators are set to the same regulated voltage in range from 2.4 V to

while in 5 V only the VSP_RF can be set in range from 3.9 V to 5.1 V, while VSP_A and are fixed to 3.4 V.

The regulators are operating when signal en is high (en is configuration bit in Operation control register. When signal en is low the ST25R3914/5 isare in low power Power-down mode. In this mode consumption of the power supply system is also minimized.

VSP_RF regulator

The intention of this regulator is to improve PSRR of the transmitter (the noise of the transmitter power supply is emitted and fed back to the receiver). The VSP_RF regulator operation is controlled and observed by writing and reading two regulator registers:

Regulator voltage control register controls the regulator mode and regulated voltage. Bit reg_s controls regulator mode. In case it is set to 0 (default state) the regulated voltage is set using direct command Adjust Regulators. When bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_1 of the same register. The regulated voltage adjustment range depends on the power supply mode. In case of 5 V supply mode the adjustment range is between 3.9 and 5.1 V in steps of 120 mV, in case of 3.3 V supply mode the adjustment range is from 2.4 to 3.4 V with steps of 100 mV. Default regulated voltage is the maximum one (5.1 V and 3.4 V, respectively, in case of 5 V and 3.3 V supply mode).

Regulator and timer display register is a read only register that displays actual regulated voltage when regulator is operating. It is especially useful in case of automatic mode, since the actual regulated voltage, which is the result of direct command Adjust Regulators, can be observed.

The VSP_RF regulator also includes a current limiter that limits the regulator typically to current of 200 mArms in normal operation (500 mA in case of short). In case the transmitter output current higher the 200 mArms is required, VSP_RF regulator cannot be used to supply the transmitter, VSP_RF has to be externally connected to VDD (connection of VSP_RF to supply voltage higher than VDD is not allowed).

The voltage drop of the transmitter current is the main source of the ST25R3914/5 power dissipation. This voltage drop is composed of drop in the transmitter driver and in the drop on VSP_RF regulator. Due to this it is recommended to set regulated voltage using direct command Adjust Regulators. It results in good power supply rejection ration with relatively low dissipated power due to regulator voltage drop.

In Power-down mode the VSP_RF regulator is not operating.

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VSP_RF pin is connected to VDD through a 1 kΩ resistor.

Connection through resistors ensures smooth power-up of the system and a smooth transition from Power-down mode to other operating modes.

VSP_A and VSP_D regulators

VSP_A and VSP_D regulators are used to supply, respectively, the ST25R3914/5 analog and digital blocks. In 3.3 V mode, VSP_A and VSP_D regulator are set to the same regulated voltage as the VSP_RF regulator, in 5 V mode VSP_A and VSP_D regulated voltage is fixed to 3.4 V.

The use of VSP_A and VSP_D regulators is obligatory in 5 V mode since analog and digital blocks supplied with these two pins contain low voltage transistors that support maximum supply voltage of 3.6 V. In 3.3 V supply mode the use of regulators is strongly recommended to improve PSRR of analog processing.

For low cost applications it is possible to disable the VSP_D regulator and to supply digital blocks through external short between VSP_A and VSP_D (configuration bit vspd_off in the IO configuration register 2. In case VSP_D regulator is disabled VSP_D can alternatively be supplied from VDD (in 3.3 V mode only) if VSP_A is not more than 300 mV lower than VDD.

Power-down support block

In the Power-down mode the regulators are disabled to save current. In this mode a low power Power-down support block that maintains the VSP_D and VSP_A in below 3.6 V is enabled. Typical regulated voltage in this mode is 3.1 V at 5 V supply and 2.2 V at 3 V supply. When 3.3 V supply mode is set the Power-down support block is disabled, its output is connected to VDD through 1 kΩ resistor.

Typical consumption of Power-down support block is 600 nA at 5 V supply.

Measurement of supply voltages

Using direct command Measure Power Supply it is possible to measure VDD and regulated voltages VSP_A, VSP_D, and VSP_RF.

1.2.11Communication with an external microcontroller

The ST25R3914/5 are slave devices and the external microcontroller initiates all communication. Communication is performed by a 4-wire serial peripheral interface (SPI). The ST25R3914/5 send an interrupt request (pin IRQ) to the microcontroller, which can use clock signal available on pin MCU_CLK when the oscillator is running.

Serial peripheral interface (SPI)

While signal /SS is high the SPI interface is in reset, while it is low the SPI is enabled. It is recommended to keep /SS high whenever the SPI is not in use. MOSI is sampled at the falling edge of SCLK. All communication is done in blocks of 8 bits (bytes). First two bits of first byte transmitted after high to low transition of /SS define SPI operation mode.

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		Table 5. Serial data interface (4-wire interface) signal lines
	Name		Signal	Signal level	Description
	/SS		Digital input		SPI Enable (active low)
	MOSI		Digital input	CMOS	Serial data input
	MISO		Digital output with tristate		Serial data output
	SCLK		Digital input		Clock for serial communication

MSB bit is always transmitted first (valid for address and data).

Read and Write modes support address auto-incrementing. This means that if some additional data bytes are sent/read after the address and first data byte, they are written to/read from addresses incremented by ‘1’. Figure 8 defines possible modes.

Figure 8. Exchange of signals with microcontroller

	Separate SPI input and			Bidirectional data
	output signals to MCU			IO signal to MCU
<![if ! IE]> <![endif]>ST25R3914/5	MOSI	MOSI	<![if ! IE]> <![endif]>ST25R3914/5	MOSI
				I/O
	MISO	MISO		MISO
				MS42457V1

MISO output is usually in tristate, it is only driven when output data is available. Due to this the MOSI and the MISO can be externally shorted to create a bidirectional signal.

During the time the MISO output is in tristate, it is possible to switch on a 10 kΩ pull down by activating option bits miso_pd1 and miso_pd2 in the IO configuration register 2.

Table 6 provides information on the SPI operation modes. Reading and writing of registers is possible in any ST25R3914/5 operation mode. FIFO operations are possible in case en (bit 7 of the Operation control register) is set and Xtal oscillator frequency is stable.

Table 6. SPI operation modes

		Pattern (communication bits)
Mode	Mode				Trailer				Related data
	M1	M0	C5	C4	C3	C2	C1	C0
Register Write	0	0	A5	A4	A3	A2	A1	A0	Data byte (or more bytes in case of
Register Read	0	1	A5	A4	A3	A2	A1	A0	auto-incrementing)

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