ST MICROELECTRONICS SMD 4047 Datasheet
CD4047BC
Low Power Monostable/Astable Multivibrator
CD4047BC Low Power Monostable/Astable Multivibrator
October 1987
Revised May 1999
General Description
The CD4047B is capable of operating in either the
monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor
(between pins 2 and 3) to determine the output pulse width
in the monostable mode, an d the output frequency in the
astable mode.
Astable operation i s ena bl ed b y a hi gh level on the astable
input or low level on the astable
quency (at 50% duty cycle) at Q and Q
mined by the timing c omponents. A frequency tw ice that of
Q is available at the Oscillator Outp ut; a 50 % duty cyc le is
not guaranteed.
Monostable operati on is obtained when t he device is triggered by LOW-to-HIGH transition at + trigger input or
HIGH-to-LOW transition at − trigger input. The device can
be retriggered by applying a simulta neous LOW-to-HIGH
transition to both the + trigger and retrigger inputs.
A high level on Reset input resets the outputs Q to LOW, Q
to HIGH.
input. The output fre-
outputs is deter-
Features
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 V
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
SPECIAL FEATURES
■ Low power consumption: special CMOS oscillator
configuration
■ Monostable (one-shot) or astable (free-running)
operation
DD
(typ.)
■ True and complemented buffered outputs
■ Only one external R and C required
MONOSTABLE MULTIVIBRATOR FEATURES
■ Positive- or negative-edge trigger
■ Output pulse width independent of trigger pulse duration
■ Retriggerable option for pulse width expansion
■ Long pulse widths poss ible u sing s mall RC c ompon ent s
by means of external counter provision
■ Fast recovery time essentially independent of pulse
width
■ Pulse-width accuracy maintained at duty cycles
approaching 100%
ASTABLE MULTIVIBRATOR FEATURES
■ Free-running or gatable operating modes
■ 50% duty cycle
■ Oscillator output available
■ Good astable frequency stability
typical= ±2% + 0.03%/°C @ 100 kHz
frequency= ±0.5% + 0.015% /°C @ 10 kHz
deviation (circuits trimmed to frequency V
±10%)
= 10V
DD
Applications
• Frequency discriminators
• Timing circuits
• Time-delay applications
• Envelope detection
• Frequency multiplication
• Frequency division
Ordering Code:
Order Number Package Number Package Description
CD4047BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4047BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
© 1999 Fairchild Semiconductor Corporation DS005969.prf www.fairchildsemi.com
Connection Diagram
Pin Assignments for SOIC and DIP
CD4047BC
Top View
Function Table
Terminal Connections Output Pulse Typical Ou tput
Function
Astable Multivibrator
Free-Running 4, 5, 6, 14 7, 8, 9, 12 10, 11, 13 t
True Gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13 t
Complement Gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13
Monostable Multivibrator
Positive-Edge Trigger 4, 14 5, 6, 7, 9, 12 8 10, 11
Negative-Edge Trigger 4, 8, 14 5, 7, 9, 12 6 10, 11 t
Retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11
External Countdown (Note 1) 14 5, 6, 7, 8, 9, 12 Figure 1 Figure 1 Figure 1
Note 1: External re s is to r between terminals 2 a nd 3. External capacitor between terminals 1 and 3.
To V
DD
To V
SS
Input Pulse
To Pulse Width
From Period or
(10, 11) = 4.40 RC
A
(13) = 2.20 RC
A
(10, 11) = 2.48 RC
M
Typical Implementation of External Countdown Option
t
= (N − 1) tA + (tM + tA/2)
EXT
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FIGURE 1.
Block Diagram
Logic Diagram
CD4047BC
*Special input prote ction circuit to permit larger input-voltage swi ngs.
3 www.fairchildsemi.com
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