Page 1
®
REGULA TING P ULSE WIDTH MODULA TO RS
COMPLETE PWM POWER CONTROL CIRCUITRY
UNCOMMITTED OUTPUTS FOR SINGLEENDED OR PUSH PULL APPLICATIONS
LOW STANDBY CURRENT 8mA TYPICAL
OPERATION UP TO 300KHz
1% MAXIMUM TEMPERATURE VARIATION
OF REFERENCE VOLTAGE
SG3524
DESCRIPTION
The SG3524 incorporates on a single monolithic
chip all the function required for the construction
of regulating power suppies inverters or switching
regulators. They can also be used as the control
element for high power-output applications. The
SG3524 family was designed for switching regulators of either polarity, transformer-coupled dcto-dc converters, transformerless voltage doublers and polarity converter applications
employing fixed-frequency, pulse-width modulation techniques. The dual alternating outputs allows either single-ended or push-pull applications.
BLOCK DIAGRAM
DIP16 SO16
ORDERING NUMBERS:
SG3524P (SO16)
Each device includes an on-ship reference, error
amplifier, programmable oscillator, pulse-steering
flip flop, two uncommitted output transistors, a
high-gain comparator, and current-limiting and
shut-down circuitry.
SG3524N (DIP16)
July 2000
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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SG3524
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
IN
I
C
I
R
I
T
P
tot
T
stg
T
op
Supply Voltage 40 V
Collector Output Current 100 mA
Reference Output Current 50 mA
Current Through CT Terminal – 5 mA
Total Power Dissipation at T
= 70°C1000mW
amb
Storage Temperature Range – 65 to 150 °C
Operating Ambient Temperature Range: 0 to 70 °C
PIN CONNECTION
(Top view)
THERMAL DATA
Symbol Parameter DIP16 SO16 Unit
R
th j-amb
R
th j-alumina
(*) Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20mm;
0.65mm thickness with infinite heatsink.
Thermal Resistance Junction-ambient Max.
Thermal Resistance Junction-alumina (*) Max.
80
–
50
–
°C/W
°C/W
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SG3524
ELECTRICAL CHARACTERISTICS
70°C, V
= 20V, and f = 20KHz).
IN
(unless otherwise stated, these specifications apply for Tj = 0 to
Symbol Parameter Test Condition Min. Typ. Max. Unit
REFERENCE SECTION
REF
REF
REF
Output Voltage 4.6 5 5.4 V
Line Regulation VIN = 8 to 40V 10 30 mV
Load Regulation IL = 0 to 20mA 20 50 mV
V
∆V
∆V
Ripple Rejection f = 120Hz, Tj = 25°C66dB
Short Circuit Current Limit V
∆V
/∆T Temperature Stability Over Operating Temperature range 0.3 1 %
REF
∆V
Long Term Stability Tj = 125°C, t = 1000Hrs 20 mV
REF
= 0, Tj = 25°C 100 mA
REF
OSCILLATOR SECTION
f
MAX
Maximum Frequency CT = 0.001µF, RT = 2KΩ 300 KHz
Initial Accuracy R
Voltage Stability V
and CT Constant 5 %
T
= 8 to 40V, Tj = 25°C1%
IN
∆f/∆T Temperature Stability Over Operating Temperature Range 2 %
Output Amplitude Pin 3, T
= 25°C 3.5 V
j
Output Pulse Width CT = 0.01µF, Tj = 25°C0.5µs
ERROR AMPLIFIER SECTION
V
G
CMV Common Mode Voltage T
Input Offset Voltage VCM = 2.5V 2 10 mV
OS
Input Bias Current 2 10 µA
I
b
Open Loop Voltage Gain 60 80 dB
V
= 25°C1.83.4V
j
CMR Common Mode Rejection Tj = 25°C70dB
B Small Signal Bandwidth A
V
Output Voltage Tj = 25°C0.53.8V
O
= 0dB, Tj = 25°C 3 MHz
V
COMPARATOR SECTION
Duty-cycle % Each Output On 0 45 %
V
Input Threshold Zero Duty-cycle 1 V
IT
Maximum Duty-cycle 3.5 V
Input Bias Current 1 µA
I
b
CURRENT LIMITING SECTION
Sense Voltage Pin 9 = 2V with Error Amp. Set for
180 200 220 mV
Max. Out.
Tj = 25°C
Sense Voltage T.C. 0.2 mV/°C
CMV Common Mode Voltage –1 1
OUTPUT SECTION
(each output)
Collector-emitter Voltage 40 V
Collector Leackage Curr. V
Saturation Voltage I
= 40V 0.1 50 µA
CE
= 50mA 1 2 V
C
Emitter Output Voltage VIN = 20V 17 18 V
Rise Time RC = 2KΩ, Tj = 25°C0.2µs
t
r
Fall Time RC = 2KΩ, Tj = 25°C0.1µs
t
f
I
(*) Total Standby Current VIN = 40V 8 10 mA
q
(*) Excluding oscillator charging current, error and current limit dividers, and with outputs open.
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SG3524
Figure 1:
Figure 3:
Open-loop Voltage Amplification of
Error Amplifier vs. Frequency
Output Dead Time vs. Timing
Capacitance Value.
Figure 2:
Figure 4:
Oscillator Frequency vs. Timing
Components.
Output Saturation Voltage vs. load
Current.
Figure 5:
4/9
Open Loop Test Circuit.
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SG3524
PRINCIPLES OF OPERATION
The SG3524 is a fixed frequency pulse-withmodulation voltage regulator control circuit. The
regulator operates at a frequency that is programmed by one timing resistor (R
ing capacitor (C
charging current for C
voltage ramp at C
). RT established a constant
T
. This results in a linear
T
, which is fed to the compara-
T
) and one tim-
T
tor providing linear control of the output pulse
width by the error amplifier. the SG3524 contains,
an on-board 5V regulator that serves as a reference as well as powering the SG3524’s internal
control circuitry and is also useful in supplying external support functions. This reference voltage is
lowered externally by a resistor divider to provide
a reference within the common mode range the
error amplifier or an external reference may be
used. The power supply output is sensed by a
second resistor divider network to generale a
feedback signal to error amplifier. The amplifier
output voltage is then compared to the linear voltage ramp at C
. The resulting modulated pulse
T
out of the high-gain comparator is then steered to
the appropriate output pass trans istors (Q
or QB)
A
by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse
to assure both output are never on simultaneously during the transition times. The width of the
blanking pulse is controlled by the value of C
T
The outputs may be applied in a push-pull configuration in which their frequency is half that of
the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to
that of the oscillator. The output of the error amplifier shares a common input to the comparator
with the current limiting at shutdown circuitry and
can be overridden by signals from either of these
inputs. This common point is also available externally and may be employed to control the gain of,
or to compensate, the error amplifier, or to provide additional control to the regulator.
RECOMMENDED OPERATIN G CONDITIONS
Supply voltage V
Reference Output Current 0 to 20mA
Current trough C
Timing Resistor, R
Timing Capacitor, C
IN
Terminal - 0.03 to -2mA
T
T
T
8 to 40V
1.8 to 100KΩ
0.001 to 0.1µF
TYPICAL APPLICATIONS DATA
OSCILLATOR
The oscillator controls the frequency of the
SG3524 and is programmed by R
and CT ac-
T
cording to the approximate formula:
1.18
f =
R
T CT
where:
R
is in K
T
is in µF
C
T
Ω
f is in KHz
Pratical values of C
fall between 0.001 and
T
0.1µF. Pratical values of RT fall between 1.8 and
100KΩ. This results in a f requency r ange typically
from 120Hz to to 500KHz.
BLANKING
The output pulse of oscillator is used as a blank-
ing pulse at the output. This pulse width is controlled by the value of C
.If small values of CT are
T
required for frequency control, the oscillator output pulse width may still be increased by applying
a shunt capacitance of up to 100pF from pin 3 to
ground. If still greater dead-time is required, it
should be accomplished by limiting the maximum
duty cycle by clamping the output of t he er ror amplifier. This can easily be done with the circuit below:
Figure 6.
.
SYNCRONOUS OPERATION
When an external clock is desired, a clock pulse
of approximately 3V can be applied directly to the
oscillator output terminal. The impedance to
ground at this point is approximately 2KΩ. In this
configuration R
must be selected for a clock
T CT
period slightly greater than that the external clock.
If two more SG2524 regulators are to be operated
synchronously, all oscillator output terminals
should be tied together, all C
terminals con-
T
nected to a single timing capacitor, and timing resistor connected to a single R
terminal. The
T
other RT terminals c an be left open or shorted to
. Minimum lead lengths should be used be-
V
REF
tween the C
terminals.
T
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Page 6
SG3524
Figure 7
: Flyback Converter Circuit.
Figure 8:
PUSH-PULL Transformer-coupled circuit.
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Page 7
SG3524
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7 .1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
mm inch
OUTLINE AND
MECHANICAL DATA
DIP16
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SG3524
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45˚ (typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1 .27 0.016 0.050
M 0.62 0.024
S
mm inch
8˚(max.)
OUTLINE AND
MECHANICAL DATA
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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SG3524
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of use of such i nformation nor for any i nfringement of patents or ot her rights of third par ties which may result from its use. No license i s
granted by impli cation or otherwis e under any patent or patent righ ts of STMicroelect ronics. Specifica tion mentioned in this publication are
subject to change without notic e. This public ation supers edes and replaces all information prev iously supplied. STMic roelec tronic s products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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