STMicroelectronics switch/hub, mPSD Brochure

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Feb 2003 www.st.com/micropsd
µ
µ
PSD
PSD
It’s All You Need.
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ST’s New 8051
ST’s New 8051--
based MCU Family
based MCU Family
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ST6
ST7
ST9
ST10
ST40 &
STPC
µPSD
Turbo
Q303
Q303
µPSD
NOW
NOW
8051 World
8051 World
N
E
W
!
N
E
W
!
ST5
3
What is
What is µµ
PSD
PSD??
Standard 8032 MCU Core
(3) 16 bit timers – (2) Ext Interrupts
Large Dual Bank Flash
Large SRAM
Programmable Logic
USB, Dual UARTs, I2C
PWM, ADC, DDC
Many I/O
Built-in Superv isor
ISP
In-System Programming
IAP
In-Application Programming
Just add power
and crystal!
Just add power
and crystal!
8032
8032
CORE:
CORE:
w/UART&
w/UART&
WDOG TMR
WDOG TMR
2K, 8K, or
2K, 8K, or
32K Byte SRAM
32K Byte SRAM
64K, 128K, or
64K, 128K, or
256K Byte
256K Byte
MAIN FLASH
MAIN FLASH
16K or 32K Byte
16K or 32K Byte
2
2
nd
nd
FLASH
FLASH
DECODE &
DECODE &
MEM MNGR
MEM MNGR
PROGRAMMABLE
PROGRAMMABLE
LOGIC
LOGIC
I/O
I/O
USB
USB
1.1
1.1
2
2
nd
nd
UART
UART
I2C
I2C
DDC
DDC
PWM
PWM
ADC
ADC
Vcc
Vcc
MON
MON
PWR
PWR
MNG
MNG
JTAG ISP
JTAG ISP
8032
8032
CORE:
CORE:
w/UART&
w/UART&
WDOG TMR
WDOG TMR
2K, 8K, or
2K, 8K, or
32K Byte SRAM
32K Byte SRAM
64K, 128K, or
64K, 128K, or
256K Byte
256K Byte
MAIN FLASH
MAIN FLASH
16K or 32K Byte
16K or 32K Byte
2
2
nd
nd
FLASH
FLASH
DECODE &
DECODE &
MEM MNGR
MEM MNGR
PROGRAMMABLE
PROGRAMMABLE
LOGIC
LOGIC
I/O
I/O
USB
USB
1.1
1.1
2
2
nd
nd
UART
UART
I2C
I2C
DDC
DDC
PWM
PWM
ADC
ADC
Vcc
Vcc
MON
MON
PWR
PWR
MNG
MNG
JTAG ISP
JTAG ISP
4
What makes
What makes µµ
PSD
PSD
different?
different?
PSD Architecture … enhances capability of 8051
PSD = Programmable System Device – Dual bank Flash Memory … Superior IAP – Memory Management … Seamless paging and memory placement – Programmable Logic … Consolidate external logic chips – JTAG ISP … perfect for lab and manufacturing
Some µPSDs have Big Memory up to 288K bytes…
When is larger Flash and SRAM needed?
The use of C language – Elaborate user interfaces … menus, graphics, screens – Multiple languages and fonts, data tables – Faster data transfers – Data recording
Low Cost
Save $ compared to other 8051 and 8-bit MCU devices with
larger SRAM and Flash Memories
5
Unique
Unique µµ
PSD
PSD
features
features
Excellent Memory Management
Flexible Memory Allocation
Remote Field Updates
JTAG In System Programming
Programmable Logic
PSD
Architecture !!!
PSD
Architecture !!!
6
Built-in Address Decoding PLD
Map any µPSD memory sector to any address – Easily convert existing 8051 designs into µPSD – Total memory mapping flexibility for new designs
Memory Paging is Easy using Decode PLD
Break traditional 8051 64K Byte address limit imposed by only 16 address lines – 8-bit page register is built into Decode PLD … it’s like having 8 more address lines – Paging (or banking) is directly supported by most 8051 C compilers
Excellent Memory Management
Excellent Memory Management
64K
FFFF
Page 0
Page 0
32K Main
32K Main
Flash
Flash
Common to All Pages
Map here: SRAM, 2ndFlash, I/O, etc
0000
Page 1
Page 1
32K Main
32K Main
Flash
Flash
Page 2
Page 2
32K Main
32K Main
Flash
Flash
Page 3
Page 3
32K Main
32K Main
Flash
Flash
MAIN FLASH
MAI N FLASH
MAIN FLASH
8
Sectors
MAIN FLASH
MAI N FLASH
MAIN FLASH
MAIN FLASH
MAI N FLASH
MAIN FLASH
8
Sectors
2ndFLASH
2
2
nd
nd
FLASH
FLASH
4
Sectors
2ndFLASH
2
2
nd
nd
FLASH
FLASH
2ndFLASH
2
2
nd
nd
FLASH
FLASH
4
Sectors
SRAM
SRAM
SRAM
1
Sector
DECODE
PLD
DECODE
DECODE
PLD
PLD
Sector
Selects
Page
Register
8032 MCU
8032
8032
MCU
MCU
Address
Sector
Selects
Page 7
Page 7
32K Main
32K Main
Flash
Flash
7
8051 Architecture uses a separate address space for code and for data
Allocate dual banks of Flash to meet Application De mands
The Decode PLD controls where Flash memory resides
You decide how to split the Flash memory
Flexible Memory Allocation
Flexible Memory Allocation
MAIN FLASH
MAIN FLASH
MAIN FLASH
2
nd
FLASH
2
2
nd
nd
FLASH
FLASH
DATA
DATA
DATA
CODE
CODE
CODE
Big Code
(complex
algorithms)
Big Data
(printers, big
GUI, tables)
MAIN FLASH
MAIN FLASH
MAIN FLASH
2
nd
FLASH
2
2
nd
nd
FLASH
FLASH
CODE
CODE
CODE
DATA
DATA
DATA
MAIN FLASH
MAIN FLASH
MAIN FLASH
2
nd
FLASH
2
2
nd
nd
FLASH
FLASH
CODE
CODE
CODE
CODE
CODE
CODE
All Code
(like typical
flash 8051s)
Can use
EEPROM
Emulation
-OR -
-OR -
8
8051s typically cannot write to “code” space
Special µPSD register eliminates this limitation
Typical Flash memory cannot be read and written
at the same time
Dual Banks of Flash eliminate this limitation – Read program from one bank while writing to the other bank
Remote Field Updates with IAP
Remote Field Updates with IAP
3. After IAP
2. During IAP
1. Before IAP
Special Register temporarily re­classifies Main Flash as Data
MCU now reads IAP program from 2ndFlash while receiving bytes of new program from USB, UART, Modem, I2C, etc. and writes the new program to Main Flash
Special Register classifies Main Flash as Code again
MCU now reading new program from Main Flash
MCU reading program from Main Flash
USB, UART,
I
2
C, Modem…
Updated
Updated
Program
Program
MAIN
MAIN
FLASH
FLASH
OLD
OLD
CODE
CODE
2
2
nd
nd
Flash
Flash
DATA
DATA
8032
8032
MCU
MCU
READ &
WRITE
READ
ONLY
MAIN
MAIN
FLASH
FLASH
OLD
OLD
CODE
CODE
2
2
nd
nd
Flash
Flash
DATA
DATA
8032
8032
MCU
MCU
READ &
WRITE
READ
ONLY
READ
ONLY
MAIN
MAIN
FLASH
FLASH
TREAT
TREAT
AS DATA
AS DATA
2
2
nd
nd
Flash
Flash
CODE
CODE
8032
8032
MCU
MCU
READ &
WRITE
READ ONLY
READ
ONLY
READ &
WRITE
MAIN
MAIN
FLASH
FLASH
TREAT
TREAT
AS DATA
AS DATA
2
2
nd
nd
Flash
Flash
CODE
CODE
8032
8032
MCU
MCU
READ &
WRITE
READ &
WRITE
READ ONLY
READ ONLY
READ
ONLY
READ
ONLY
READ &
WRITE
READ &
WRITE
MAIN
MAIN
FLASH
FLASH
2
2
nd
nd
Flash
Flash
DATA
DATA
8032
8032
MCU
MCU
READ &
WRITE
READ ONLY
NEW
NEW
CODE
CODE
MAIN
MAIN
FLASH
FLASH
2
2
nd
nd
Flash
Flash
DATA
DATA
8032
8032
MCU
MCU
READ &
WRITE
READ ONLY
READ ONLY
NEW
NEW
CODE
CODE
NEW
NEW
CODE
CODE
9
µµPSD
PSD
µµPSD
PSD
In
In--
System Programming (ISP)
System Programming (ISP)
Program blank device, no interaction of 8032 MCU required
Entire chip programs in 10-25 seconds
JTAG serial connection is industry standard
Speedy lab development and manufacturing
No sockets or
pre-programmed
parts needed
Last minute
changes are
OK
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Just-In-Time
Inventory
Management
JIT
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