ST MICROELECTRONICS MASTERGAN5 Datasheet

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MASTERGAN5

Datasheet

High power density 600 V half-bridge driver with two enhancement mode

GaNHEMT

Features

• 600 V system-in-package integrating half-bridge gate driver and high-voltage GaN power transistors:

– QFN 9 x 9 x 1 mm package

– R

– I

• Reverse current capability

• Zero reverse recovery loss

• UVLO protection on low-side and high-side

• Internal bootstrap diode

• Interlocking function

• Dedicated pin for shut down functionality

• Accurate internal timing match

• 3.3 V to 15 V compatible inputs with hysteresis and pull-down

• Over temperature protection

• Bill of material reduction

• Very compact and simplified layout

• Flexible, easy and fast design.

DS(ON)

DS(MAX)

= 450 mΩ

= 4 A

Product status link

MASTERGAN5

Product label

Applications

Switch-mode power supplies

Chargers and adapters

High-voltage PFC, DC-DC and DC-AC Converters

Description

The MASTERGAN5 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN power transistors in half bridge configuration. The integrated power GaNs have 650 V drain-source blocking voltage and R

easily supplied by the integrated bootstrap diode.

The MASTERGAN5 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions.

The extended range of the input pins allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.

The MASTERGAN5 operates in the industrial temperature range, -40°C to 125°C.

The device is available in a compact 9x9 mm QFN package.

of 450 mΩ, while the high side of the embedded gate driver can be

DS(ON)

DS13775 - Rev 1 - July 2021 For further information contact your local STMicroelectronics sales office.

www.st.com

1 Block diagram

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGOFF

RGON

RGOFF

MASTERGAN5

Block diagram

Figure 1. Block diagram

DS13775 - Rev 1

page 2/26

2 Pin descriptions and connection diagram

GND

SENSE

OUT

EP1

EP2

EP3

SENSE

OUT

SENSE

OUTb

BOOT

PGND

PVCC

N.C.

VCC

GND

LIN

HIN

SD/OD

N.C.

Figure 2. Pin connections (top view)

MASTERGAN5

Pin descriptions and connection diagram

2.1 Pin list

Table 1. Pin descriptions

Pin Number Pin Name Type Function

15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)

12, 13, 14, EP3 OUT Power Output Half-bridge output

4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source)

22 BOOT Power Supply Gate driver high-side supply voltage

21 OUTb Power Supply

27 VCC Power Supply Logic supply voltage

1 PVCC Power Supply Gate driver low-side supply voltage

28, EP1 GND Power Supply Gate driver ground

3 PGND Power Supply

26 HIN Logic Input High-Side driver logic input

24 LIN Logic Input Low-Side driver logic input

25 SD/OD Logic Input-output Driver Shut-Down input and Fault Open-Drain

2 GL Output Low-Side GaN gate.

20 GH Output High-Side GaN gate.

23, 29, 30, 31 N.C. Not Connected Leave floating

Gate driver high-side supply voltage, used only for Bootstrap

capacitor connection. Internally connected to OUT.

Gate driver low-side buffer ground. Internally connected to

SENSE.

DS13775 - Rev 1

page 3/26

3 Electrical Data

3.1 Absolute maximum ratings

Each voltage referred to GND unless otherwise specified

Symbol Parameter Test Condition Value Unit

VCC Logic supply voltage - -0.3 to 11 V

PVCC-PGND

VCC-PGND Logic supply vs Low-side driver ground - -0.3 to 18.3 V

PVCC Low-side driver supply vs logic ground - -0.3 to 18.3 V

PGND Low-side driver ground vs logic ground - -7.3 to 11.3 V

BOOT Bootstrap voltage - -0.3 to 620 V

CGL, CGH

RGL, RGH

out

Maximum external capacitance between GL and PGND and

Minimum external pull down resistance between GL and

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT

3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12)

4. TCB is temperature of case exposed pad

5. Range estimated by characterization, not tested in production

6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature

GaN Drain-to-Source Voltage

Low-side driver supply voltage

BOOT to OUTb voltage

between GH and OUTb

PGND and GH and OUTb

Drain current

Half-bridge outputs slew rate (10% - 90%) - 100 V/ns

Logic inputs voltage range - -0.3 to 21 V

Junction temperature - -40 to 150 °C

Storage temperature - -40 to 150 °C

Table 2. Absolute maximum ratings

(1)

(2)

DC @ TCB = 25 °C

DC @ TCB = 100 °C

Peak @ TCB = 25 °C

MASTERGAN5

TJ = 25 °C

- -0.3 to 7 V

FSW = 500 kHz

(3)

- 6.8 kΩ

(4) (5)

(4) (5) (6)

Electrical Data

620 V

3.9 nF

4 A

2.6 A

7 A

3.2

DS13775 - Rev 1

Recommended operating conditions

Table 3. Recommended operating conditions

Each voltage referred to GND unless otherwise specified

Symbol Parameter Note Min Max Unit

VS High voltage bus - 0 520 V

VCC Supply voltage - 4.75 9.5 V

PVCC-PGND

PVCC to PGND Low side supply

(1)

- 4.75 6.5 V

page 4/26

MASTERGAN5

Thermal data

Symbol Parameter Note Min Max Unit

PVCC-PGND

PVCC to PGND Low side supply

PVCC Low-side driver supply - 3 8.5 V

VCC-PVCC VCC to PVCC pin voltage - -3 3 V

PGND

Low-side driver ground

DT Suggested minimum dead time - 5 - ns

IN_MIN

Minimum duration of input pulse to obtain undistorted output pulse

BOOT to OUTb pin voltage

BOOT BOOT to GND voltage -

Logic inputs voltage range - 0 20 V

Junction temperature - -40 125 °C

1. PGND internally connected to SENSE

2. See Logic inputs for more detail

3. OUTb internally connected to OUT

4. 5 V is recommended during High Side turn-on

(1)

(3)

Best performance 5 6.5 V

- -2 2 V

(2)

- 120 - ns

- 4.4 6.5 V

Best performance 5 6.5 V

(4)

530 V

3.3 Thermal data

Symbol Parameter Value Unit

th(J-CB)_HS

th(J-A)

The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as per JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation is uniformly distributed over the two GaN transistors.

Thermal resistance of each transistor’s junction to relevant exposed pad, typical 4.7 °C/W

Thermal resistance junction-to-ambient(1) 18.8 °C/W

Table 4. Thermal data

DS13775 - Rev 1

page 5/26

4 Electrical characteristics

4.1 Driver

Table 5. Driver electrical characteristics

VCC = PVCC = 6 V, SENSE = GND, TJ = 25 °C, unless otherwise specified Each voltage referred to GND unless otherwise specified

Symbol - Parameter Test condition Min Typ Max Unit

VCC

QVCCU

thON

thOFF

hys

VCC vs.

GND

QVCC

SVCC

VCC UV turn ON

threshold

(1)

VCC UV turn

OFF threshold

VCC UV

hysteresis

(1)

VCC

undervoltage

quiescent supply

current

VCC quiescent

supply current

VCC switching

supply current

Logic section supply

(1)

VCC = PVCC = 3.

8 V

SD/OD = LIN = 5

HIN = 0 V;

BOOT = 7 V

SD/OD = 5 V;

VBO = 6.5 V;

VS = 0 V;

FSW = 500 kHz

MASTERGAN5

Electrical characteristics

- 4.2 4.5 4.75 V

- 3.9 4.2 4.5 V

- 0.2 0.3 0.45 V

- 320 410 μA

- 680 900 μA

- 0.8 - mA

QPVCC

SPVCC

BLEED

RON

ROFF

BOthON

BOthOFF

BOhys

QBOU

PVCC vs.

PGND

GL vs. PGND

BOOT vs.

OUTb

PVCC quiescent

supply current

PVCC switching

supply current

Low side gate

bleeder

Low side turn on

resistance

Low side turn off

resistance

(2)

VBO UV turn ON

threshold

(3)

VBO UV turn OFF

threshold

(3)

VBO UV

hysteresis

(3)

VBO undervoltage

quiescent supply

current

(3)

Low-side driver section supply

SD/OD = LIN = 5 V - 150 - μA

VS = 0 V

FSW = 500 kHz

- 1.0 - mA

PVCC = PGND 75 100 125 kΩ

I(GL) = 1 mA

(source)

- 77 - Ω

I(GL) = 1 mA (sink) - 2 - Ω

High-side floating section supply

- 3.6 4.0 4.4 V

- 3.4 3.7 4.0 V

- 0.1 0.3 0.5 V

VBO = 3.4 V

- 140 200 μA

DS13775 - Rev 1

page 6/26

MASTERGAN5

Symbol - Parameter Test condition Min Typ Max Unit

VBO = 6 V;

LIN = GND;

SD/OD = HIN = 5

VBO =6 V;

SD/OD = 5 V;

VS = 0 V;

FSW = 500 kHz

- 180 - μA

- 1.1 - mA

QBO

SBO

BOOT vs.

OUTb

BOOT

VBO quiescent

supply current

BOOT switching

supply current

(3)

Driver

DBoot

RON

ROFF

ihys

INh

INl

PD_IN

SDh

SDl

PD_SD

TSD

ON_OD

BOOT vs.

SGND

High voltage

leakage current

BOOT = OUT = 60

0 V

- - 11 μA

SD/OD = LIN = 5

VCC vs.

BOOT

Bootstrap diode

on-resistance

HIN = GND = PGN

(4)

- 140 175 Ω

VCC –

BOOT = 0.5 V

High side turn on

resistance

High side turn off

resistance

(2)

I(GH) = 1 mA

(source)

I(GH) = 1 mA

(sink)

- 77 - Ω

- 2 - Ω

Logic inputs

LIN, HIN,

SD/OD

Low level logic

threshold voltage

High level logic

threshold voltage

Full Temperature

range

(5)

TJ = 25 °C

Full Temperature

range

(5)

TJ = 25 °C

1.1 1.31 1.45

0.8 - -

2 2.17 2.5

- - 2.7

Logic input

threshold

0.7 0.96 1.2 V

hysteresis

LIN, HIN

SD/OD

Logic ‘1’ input

bias current

Logic ‘0’ input

bias current

Input pull-down

resistor

Logic “1” input

bias current

Logic “0” input

bias current

Pull-down

resistor

Thermal

shutdown unlatch

LIN, HIN = 5 V 23 33 55 μA

LIN, HIN = GND - - 1 μA

LIN, HIN = 5 V 90 150 220 kΩ

SD/OD = 5 V 11 15 20 μA

SD/OD = 0 V - - 1 μA

SD/OD = 5 V

OpenDrain OFF

TJ = 25 °C

(6)

250 330 450 kΩ

0.5 0.75 1 V

threshold

SD/OD

Open drain ON

resistance

TJ = 25 °C;

IOD = 400 mV

(6)

8 10 18 Ω

DS13775 - Rev 1

OL_OD

d_GL

SD/OD

LIN, GL

Open Drain low

level sink current

Prop. delay from

LIN to GL

TJ = 25 °C;

VOD = 400 mV

(6)

22 40 50 mA

- 46 - ns

page 7/26

Symbol - Parameter Test condition Min Typ Max Unit

d_GH

TSD

HYS

HIN, GH

Prop. delay from

1. VCC UVLO is referred to VCC - GND

2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson

3. VBO = V

4. R

BD(on)

- V

BOOT

OUT

is tested in the following way

= [(VCC - V

BOOTa

) - (VCC - V

Where: Ia is BOOT pin current when V

5. Range estimated by characterization, not tested in production

6. Tested at wafer level

4.2 GaN power transistor

HIN to GH

Shut down

temperature

Temperature

hysteresis

BOOTb

BOOT

(6)

Over temperature protection

(5)

)] / [Ia - Ib]

= V

; Ib is BOOT pin current when V

BOOTa

MASTERGAN5

GaN power transistor

- 46 - ns

- 175 - °C

- 20 - °C

= V

BOOT

BOOTb

Table 6. GaN power transistor electrical characteristics

VGS = 6 V; TJ = 25 °C, unless otherwise specified.

Symbol Parameter Test condition Min Typ Max Unit

GaN on/off states

(1)

650 - - V

- 0.3 - µA

(1)

(2)

25°C

J =

125°C

(2)

J =

- 1.7 - V

- 20 - µA

- 450 600

- 1012 -

DSS

VGS = 0 V

VDS = 600 V

VGS = 0 V

VDS = V

ID = 1.7 mA

VDS = 0 V

D =

(BR)DS

DSS

GS( th )

DS( on)

Drain-source blocking voltage

Zero gate voltage drain current

Gate threshold voltage

Gate to source current

Static drain-source on-resistance

1. Tested at wafer level

2. Range estimated by characterization, not tested in production

< 6.6 µA

1.2 A

mΩ

DS13775 - Rev 1

page 8/26

5 Device characterization values

The information in Table 7 and Table 8 represent typical values based on characterization and simulation results and are not tested in production.

Table 7. GaN power transistor characterization values (each transistor)

Symbol Parameter Test condition Min Typ Max Unit

Total gate charge

1. C

2. C

Output charge

OSS

Output Capacitance stored energy - 0.9 - µJ

OSS

Output capacitance - 7 - pF

OSS

Effective output capacitance energy related

O(ER)

Effective output capacitance time related

O(TR)

Reverse recovery charge - - 0 - nC

Reverse recovery current - - 0 - A

RRM

is the fixed capacitance that would give the same stored energy as C

O(ER)

is the fixed capacitance that would give the same charging time as C

O(TR)

(2)

6 V, TJ = 25 °C

GS =

0 to 400 V

DS =

VGS = 0 V, VDS = 400 V

(1)

VGS = 0 V, VDS = 0 to 400 V

MASTERGAN5

Device characterization values

- 0.8 - nC

- 7 - nC

- 11 - pF

- 17 - pF

while VDS is rising from 0 V to the stated

OSS

while VDS is rising from 0 V to the stated

OSS

1. t

2. tC

Symbol

(on)

C(on)

(off)

C(off)

and t

(on)

Table 8. Inductive load switching characteristics

Parameter Test condition Min Typ Max Unit

(1)

(2)

(1)

off

and tC

Turn-on time

Crossover time (on) - 25 - ns

Turn-off time - 70 - ns

VS = 400 V,

VGS = 6 V,

Crossover time (off) - 10 - ns

Shutdown to high/low-side propagation delay - 70 - ns

See Figure 3

Turn-on switching losses - 4.5 - µJ

Turn-off switching losses - 2.5 - µJ

include the propagation delay time of the internal driver and GaN Turn on time

(off)

are the switching times of GaN transistor itself under the internally given gate driving conditions

(off)

- 70 - ns

ID = 1.2 A

DS13775 - Rev 1

page 9/26

Figure 3. Switching time definition

(ON)

(OFF)

C(ON)

C(OFF)

10%I

10%V

10%I

10%V

(a) turn-on

(b) turn-off

VDS (V)

(A)

VGS=6V

TJ=25°C

VGS=5V

1 2 3 4 5

VGS=4V

VDS (V)

(A)

VGS=6V

TJ=125°C

VGS=5V

1 2 3 4 5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

VGS=4V

MASTERGAN5

Device characterization values

Figure 4. Typ ID vs VDS at TJ=25°C

DS13775 - Rev 1

Figure 5. Typ ID vs VDS at TJ=125°C

page 10/26

5 9 10

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8 TJ=25°C

ID (A)

DS(on)

(Ω)

762

0.5

2.5 4.5 5

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

TJ=125°C

ID (A)

DS(on)

(Ω)

3.531

21.5

VDS (V)

(A)

VGS=6V

TJ=25°C

1 2 3 4 5

TJ=50°C

TJ=75°C

TJ=100°C

TJ=125°C

Normalized R

DS(on)

(1 at 25°C)

1.0

0.5

1.5

2.0

2.5

3.0

Temperature (°C)

-50

-10

110

150

MASTERGAN5

Device characterization values

Figure 6. Typ R

Figure 8. Typ I

vs ID at TJ=25°C

DS(ON)

D(ON)

vs V

Figure 7. Typ R

Figure 9. Typ R

vs ID at TJ=125°C

DS(ON)

_x vs TJ, normalized at 25°C

DS(ON)

DS13775 - Rev 1

page 11/26

VSD (V)

(A)

VGS=6V

TJ=25°C

VGS=0V

1 2 3 4 5 6 7 8 9 10

VSD (V)

(A)

VGS=6V

TJ=125°C

VGS=0V

1 2 3 4 5 6 7 8 9 10

100

1000

0.01

0.1

50 μs

0.2 μs

Id (A)

Vds (V)

0 0.2

0.4

0.6

0.8

QG (nC)

(V)

400 V

100 V

MASTERGAN5

Device characterization values

Figure 10. Typ ISD vs VSD, at TJ=25°C

Figure 12. Safe Operating Area at TJ=25°C

Figure 11. Typ ISD vs VSD, at TJ=125°C

Figure 13. Typ Gate Charge at TJ=25°C

DS13775 - Rev 1

page 12/26

100

125

TCB (°C)

150

DISS

(W)

DBoot

(ohm)

100

150

200

250

300

Temperature (°C)

-50

-10

110

150

MASTERGAN5

Logic inputs

Figure 14. Derating Curve

5.1 Logic inputs

The MASTERGAN5 features a half-bridge gate driver with three logic inputs to control the internal high-side and low-side GaN transistors.

The devices are controlled through following logic inputs:

• SD/OD: Shut-down input, active low;

• LIN: low-side driver inputs, active high;

• HIN: high-side driver inputs, active high.

Figure 15. Typ R

Dboot

vs T

Table 9. Inputs truth table (applicable when device is not in UVLO)

Input pins GaN transistors status

SD/OD LIN HIN LS HS

(1)

OFF OFF

H L L OFF OFF

H L H OFF ON

H H L ON OFF

(2)

OFF OFF

1. X: Don’t care

2. Interlocking

The logic inputs have internal pull-down resistors. The purpose of these resistors is to set a proper logic level in case, for example, there is an interruption in the logic lines or the controller outputs are in tri-state conditions.

If logic inputs are left floating, the gate driver outputs are set to low level and the corresponding GaN transistors are turned off.

The minimum duration of the on time of the pulses applied to LIN is T either extended to T

or blanked, if shorter than 30ns (typ). Minimum duration of the off time of the pulses

IN_MIN

= 120ns; shorter pulses could be

IN_MIN

applied to LIN is 60ns or could be blanked if they are shorter.

DS13775 - Rev 1

page 13/26

VCC = PVCC

VCC

thON

VCC

thOFF

UVLO VCC

VCC rise

LIN

GL-PGND

PVCC

MASTERGAN5

Bootstrap structure

The minimum duration of the off time of the pulses applied to HIN is T either extended to T

or blanked, if shorter than 30ns (typ). Minimum duration of the on time of the pulses

IN_MIN

applied to HIN is 60ns or could be blanked if they are shorter.

Interlocking feature interrupts running T

to avoid unexpected cross-conduction.

IN_MIN

Matched, short propagation delay between low side and high side are there.

5.2 Bootstrap structure

Bootstrap circuitry is typically used to supply the high-voltage section. MASTERGAN5 integrates this structure by means of a patented integrated high-voltage DMOS to reduce the external components.

The Boostrap integrated circuit is connected to VCC pin and is driven synchronously with the low-side driver.

The use of an external bootstrap diode in parallel to the integrated structure is possible, especially when the operating frequency is generally higher than 500 kHz.

5.3 VCC supply pins and UVLO function

The VCC pin supplies current to the logic circuit, level-shifters in the low-side section and the integrated bootstrap diode.

The PVCC pin supplies low-side output buffer. During outputs commutations the average current used to provide gate charge to the high-side and low-side GaN transistors flow through this pin.

The PVCC pin can be connected either to the same supply voltage of the VCC pin or to a separated voltage source. In case the same voltage source is used, it is suggested to connect VCC and PVCC pins by means of a small decoupling resistance. The use of dedicated bypass ceramic capacitors located as close as possible to each supply pin is highly recommended.

The MASTERGAN5 VCC supply voltage is continuously monitored by under-voltage lockout (UVLO) circuitry that turns the high-side and low-side GaN transistors off when the supply voltage goes below the V

The UVLO circuitry turns on the GaN, accordingly to LIN and HIN status, approximately 20µs (typ) after the supply voltage goes above the V

CCthON

voltage. A V

= 120ns; shorter pulses shall be

IN_MIN

CC_thOFF

hysteresis is provided for noise rejection purposes.

CChys

threshold.

5.4 VBO UVLO protection

Dedicated under-voltage protection is available on the bootstrap section between BOOT and OUTb supply pins. In order to avoid intermittent operation, a hysteresis set the turn-off threshold with respect to the turn-on threshold.

When the VBO voltage falls below the V Approximately 5µs (typ) after the VBO voltage reaches the V operation and the output remains off until the next input pin transition that requests the high-side to turn on.

Figure 16. VCC UVLO and Low Side

BOthOFF

threshold, the high-side GaN transistor is switched off.

threshold, the device returns to normal

BOthON

DS13775 - Rev 1

page 14/26

Figure 17. VBO UVLO and High Side

VCC

VCCthON VCCthOFF

HIN

UVLO VBO

VBOrise

(GH-OUTB)

VBO

BOthON

VBOthOFF

VBO

MASTERGAN5

Thermal shutdown

5.5 Thermal shutdown

The integrated gate driver has a thermal shutdown protection.

When junction temperature reaches the T leaving the half-bridge in 3-state and signaling the state forcing

junction temperature is below T

GaN are driven again according to inputs when

The thermal smart shutdown system gives the possibility to increase the time constant of the external RC network (that determines the disable time after the overtemperature event) up to very large values without delaying the protection.

TSD-THYS

temperature threshold, the device turns off both GaN transistors

TSD

SD/OD pin low. SD/OD pin is released when

and SD/OD is below V

TSD

SD/OD rise above Vih.

DS13775 - Rev 1

page 15/26

Figure 18. Thermal Shutdown timing waveform

THERMAL SHUTDOWN CIRCUIT

GH/GL

OD gate

(internal)

Fast shut down

the driver outputs are switched off

disable time

SD/OD

TSDTHYSTTSD -

VihV

0 V

TSDVOD

t1t

VPU

SD/OD

FROM / TO

CONTROLLER

THERMAL

SHUTDOWN

LOGIC

ON_ODRPD_SD

OD_ext

immediately after overtemperature

MASTERGAN5

Thermal shutdown

DS13775 - Rev 1

page 16/26

6 Typical application diagrams

PVCC

FROM/TO CONTROLLER

H.V.

CBOOT

CVCC

COD

VCC

VPU

CbuS

FROM/TO CONTROLLER

VOUT

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGON

RGOFF

RGON

PVCC

FROM/TO CONTROLLER

H.V.

CBOOT

CVCC

COD

VOUT

VCC

VPU

CbuS

FROM/TO CONTROLLER

TO CONTROLLER

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGON

RGOFF

RGON

Figure 19. Typical application diagram – Resonant LLC converter

MASTERGAN5

Typical application diagrams

Figure 20.

Typical application diagram – Active clamp flyback

DS13775 - Rev 1

page 17/26

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

Table 10. QFN 9 x 9 x 1 mm package dimensions

MASTERGAN5

Package information

Symbol

A3 - 0.10 -

b 0.25 0.30 0.35

D 8.96 9.00 9.04

E 8.96 9.00 9.04

D1 3.30 3.40 3.50

E1 2.06 2.16 2.26

D2 1.76 1.86 1.96

E2 3.10 3.20 3.30

D3 1.70 1.80 1.90

E3 3.10 3.20 3.30

e - 0.60 -

K - 0.24 -

L 0.35 0.45 0.55

N 31

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

Min. Typ. Max.

0.90 0.95 1.00

Dimensions (mm)

Note: • Dimensioning and tolerances conform to ASME Y14.5-2009

• All dimensions are in millimeters

• N total number of terminals

• Dimensions do not include mold protrusion, not to exceed 0.15 mm

• Package outline exclusive of metal burr dimensions

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Figure 21. QFN 9 x 9 x 1 mm package dimensions

TOP VIEW

SIDE

VIEW

BOTTOM VIEW

MASTERGAN5

QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

DS13775 - Rev 1

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8 Suggested footprint

TOP VIEW

Dimensions in mm

The MASTERGAN5 footprint for the PCB layout is usually defined based on several design factors as assembly plant technology capabilities and board component density. For easy device usage and evaluation, ST provides the following footprint design, which is suitable for the largest variety of PCBs.

The following footprint indicates the copper area which should be free from the solder mask,

while the copper area shall extend beyond the indicated areas especially for EP2 and EP3. To aid thermal dissipation, it is recommended to add thermal vias under these EPADs to transfer and dissipate device heat to the other PCB copper layers. A PCB layout example is available with the MASTERGAN5 evaluation board.

Figure 22. Suggested footprint (top view drawing)

MASTERGAN5

Suggested footprint

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9 Ordering information

Order code Package Package Marking Packaging

MASTERGAN5 QFN 9 x 9 x 1 mm MASTERGAN5 Tray

MASTERGAN5TR QFN 9 x 9 x 1 mm MASTERGAN5 Tape and Reel

MASTERGAN5

Ordering information

Table 11. Order codes

DS13775 - Rev 1

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Revision history

MASTERGAN5

Table 12. Document revision history

Date Version Changes

26-Jul-2021 1 Initial release.

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MASTERGAN5

Contents

1 Block diagram .....................................................................2

2 Pin descriptions and connection diagram ..........................................3

2.1 Pin list ........................................................................3

3 Electrical Data .....................................................................4

3.1 Absolute maximum ratings.......................................................4

3.2 Recommended operating conditions ..............................................4

3.3 Thermal data ..................................................................5

4 Electrical characteristics...........................................................6

4.1 Driver ........................................................................6

4.2 GaN power transistor ...........................................................8

5 Device characterization values.....................................................9

5.1 Logic inputs ..................................................................13

5.2 Bootstrap structure ............................................................14

5.3 VCC supply pins and UVLO function .............................................14

5.4 VBO UVLO protection ..........................................................14

5.5 Thermal shutdown.............................................................15

6 Typical application diagrams......................................................17

7 Package information ..............................................................18

7.1 [Package name] package information ............................................18

8 Suggested footprint ..............................................................20

9 Ordering information .............................................................21

Revision history .......................................................................22

Contents ..............................................................................23

List of tables ..........................................................................24

List of figures..........................................................................25

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MASTERGAN5

List of tables

Table 1. Pin descriptions .....................................................................3

Table 2. Absolute maximum ratings .............................................................4

Table 3. Recommended operating conditions.......................................................4

Table 4. Thermal data .......................................................................5

Table 5. Driver electrical characteristics .......................................................... 6

Table 6. GaN power transistor electrical characteristics ................................................8

Table 7. GaN power transistor characterization values (each transistor) ....................................9

Table 8. Inductive load switching characteristics .....................................................9

Table 9. Inputs truth table (applicable when device is not in UVLO)....................................... 13

Table 10. QFN 9 x 9 x 1 mm package dimensions ................................................... 18

Table 11. Order codes ...................................................................... 21

Table 12. Document revision history............................................................. 22

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MASTERGAN5

List of figures

Figure 1. Block diagram ....................................................................2

Figure 2. Pin connections (top view) ............................................................3

Figure 3. Switching time definition ............................................................ 10

Figure 4. Typ ID vs VDS at TJ=25°C............................................................ 10

Figure 5. Typ ID vs VDS at TJ=125°C........................................................... 10

Figure 6. Typ R

Figure 7. Typ R

Figure 8. Typ I

D(ON)

Figure 9. Typ R

Figure 10. Typ ISD vs VSD, at TJ=25°C .......................................................... 12

Figure 11. Typ ISD vs VSD, at TJ=125°C ......................................................... 12

Figure 12. Safe Operating Area at TJ=25°C ....................................................... 12

Figure 13. Typ Gate Charge at TJ=25°C .........................................................12

Figure 14. Derating Curve ................................................................... 13

Figure 15. Typ R

Figure 16. VCC UVLO and Low Side ........................................................... 14

Figure 17. VBO UVLO and High Side ........................................................... 15

Figure 18. Thermal Shutdown timing waveform .................................................... 16

Figure 19. Typical application diagram – Resonant LLC converter ....................................... 17

Figure 20. Typical application diagram – Active clamp flyback .......................................... 17

Figure 21. QFN 9 x 9 x 1 mm package dimensions .................................................19

Figure 22. Suggested footprint (top view drawing) .................................................. 20

vs ID at TJ=25°C ......................................................... 11

DS(ON)

vs ID at TJ=125°C ........................................................ 11

DS(ON)

vs VDS................................................................. 11

_x vs TJ, normalized at 25°C ................................................. 11

DS(ON)

vs TJ.................................................................. 13

Dboot

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MASTERGAN5

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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ST MICROELECTRONICS MASTERGAN5 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Applications

Description

1 Block diagram

2 Pin descriptions and connection diagram

2.1 Pin list

3 Electrical Data

3.1 Absolute maximum ratings

Recommended operating conditions

3.3 Thermal data

4 Electrical characteristics

4.1 Driver

4.2 GaN power transistor

5 Device characterization values

5.1 Logic inputs

5.2 Bootstrap structure

5.3 VCC supply pins and UVLO function

5.4 VBO UVLO protection

5.5 Thermal shutdown

6 Typical application diagrams

7 Package information

7.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

8 Suggested footprint

9 Ordering information

Revision history

Contents

List of tables

List of figures