ST MICROELECTRONICS MASTERGAN5 Datasheet

MASTERGAN5

Datasheet

High power density 600 V half-bridge driver with two enhancement mode

GaNHEMT

Features

• 600 V system-in-package integrating half-bridge gate driver and high-voltage GaN power transistors:

– QFN 9 x 9 x 1 mm package

– R

– I

• Reverse current capability

• Zero reverse recovery loss

• UVLO protection on low-side and high-side

• Internal bootstrap diode

• Interlocking function

• Dedicated pin for shut down functionality

• Accurate internal timing match

• 3.3 V to 15 V compatible inputs with hysteresis and pull-down

• Over temperature protection

• Bill of material reduction

• Very compact and simplified layout

• Flexible, easy and fast design.

DS(ON)

DS(MAX)

= 450 mΩ

= 4 A

Product status link

MASTERGAN5

Product label

Applications

Switch-mode power supplies

Chargers and adapters

High-voltage PFC, DC-DC and DC-AC Converters

Description

The MASTERGAN5 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN power transistors in half bridge configuration. The integrated power GaNs have 650 V drain-source blocking voltage and R

easily supplied by the integrated bootstrap diode.

The MASTERGAN5 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions.

The extended range of the input pins allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.

The MASTERGAN5 operates in the industrial temperature range, -40°C to 125°C.

The device is available in a compact 9x9 mm QFN package.

of 450 mΩ, while the high side of the embedded gate driver can be

DS(ON)

DS13775 - Rev 1 - July 2021 For further information contact your local STMicroelectronics sales office.

www.st.com

1 Block diagram

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

GL

GH

VCC

HIN

LIN

SD/OD

GND

OUT

VS

SENSE

HON

HOFF

LON

LOFF

R

BLEED

RGOFF

H

RGON

H

RGON

L

RGOFF

L

MASTERGAN5

Block diagram

Figure 1. Block diagram

DS13775 - Rev 1

page 2/26

2 Pin descriptions and connection diagram

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

24

23

22

21

20

19

18

17

16

31

30

29

28

27

26

25

GND

SENSE

OUT

EP1

EP2

EP3

SENSE

OUT

SENSE

VS

GH

OUTb

BOOT

PGND

GL

PVCC

N.C.

VCC

GND

LIN

HIN

SD/OD

N.C.

Figure 2. Pin connections (top view)

MASTERGAN5

Pin descriptions and connection diagram

2.1 Pin list

Table 1. Pin descriptions

Pin Number Pin Name Type Function

15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)

12, 13, 14, EP3 OUT Power Output Half-bridge output

4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source)

22 BOOT Power Supply Gate driver high-side supply voltage

21 OUTb Power Supply

27 VCC Power Supply Logic supply voltage

1 PVCC Power Supply Gate driver low-side supply voltage

28, EP1 GND Power Supply Gate driver ground

3 PGND Power Supply

26 HIN Logic Input High-Side driver logic input

24 LIN Logic Input Low-Side driver logic input

25 SD/OD Logic Input-output Driver Shut-Down input and Fault Open-Drain

2 GL Output Low-Side GaN gate.

20 GH Output High-Side GaN gate.

23, 29, 30, 31 N.C. Not Connected Leave floating

Gate driver high-side supply voltage, used only for Bootstrap

capacitor connection. Internally connected to OUT.

Gate driver low-side buffer ground. Internally connected to

SENSE.

DS13775 - Rev 1

page 3/26

3 Electrical Data

3.1 Absolute maximum ratings

Each voltage referred to GND unless otherwise specified

Symbol Parameter Test Condition Value Unit

V

DS

VCC Logic supply voltage - -0.3 to 11 V

PVCC-PGND

VCC-PGND Logic supply vs Low-side driver ground - -0.3 to 18.3 V

PVCC Low-side driver supply vs logic ground - -0.3 to 18.3 V

PGND Low-side driver ground vs logic ground - -7.3 to 11.3 V

V

BO

BOOT Bootstrap voltage - -0.3 to 620 V

CGL, CGH

RGL, RGH

SR

T

I

D

out

V

i

J

s

Maximum external capacitance between GL and PGND and

Minimum external pull down resistance between GL and

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT

3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12)

4. TCB is temperature of case exposed pad

5. Range estimated by characterization, not tested in production

6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature

GaN Drain-to-Source Voltage

Low-side driver supply voltage

BOOT to OUTb voltage

between GH and OUTb

PGND and GH and OUTb

Drain current

Half-bridge outputs slew rate (10% - 90%) - 100 V/ns

Logic inputs voltage range - -0.3 to 21 V

Junction temperature - -40 to 150 °C

Storage temperature - -40 to 150 °C

Table 2. Absolute maximum ratings

(1)

(2)

DC @ TCB = 25 °C

DC @ TCB = 100 °C

Peak @ TCB = 25 °C

MASTERGAN5

TJ = 25 °C

- -0.3 to 7 V

FSW = 500 kHz

(3)

- 6.8 kΩ

(4) (5)

(4) (5) (6)

Electrical Data

620 V

3.9 nF

4 A

2.6 A

7 A

3.2

DS13775 - Rev 1

Recommended operating conditions

Table 3. Recommended operating conditions

Each voltage referred to GND unless otherwise specified

Symbol Parameter Note Min Max Unit

VS High voltage bus - 0 520 V

VCC Supply voltage - 4.75 9.5 V

PVCC-PGND

PVCC to PGND Low side supply

(1)

- 4.75 6.5 V

page 4/26

MASTERGAN5

Thermal data

Symbol Parameter Note Min Max Unit

PVCC-PGND

PVCC to PGND Low side supply

PVCC Low-side driver supply - 3 8.5 V

VCC-PVCC VCC to PVCC pin voltage - -3 3 V

PGND

Low-side driver ground

DT Suggested minimum dead time - 5 - ns

T

IN_MIN

V

BO

Minimum duration of input pulse to obtain undistorted output pulse

BOOT to OUTb pin voltage

BOOT BOOT to GND voltage -

V

i

T

J

Logic inputs voltage range - 0 20 V

Junction temperature - -40 125 °C

1. PGND internally connected to SENSE

2. See Logic inputs for more detail

3. OUTb internally connected to OUT

4. 5 V is recommended during High Side turn-on

(1)

(3)

Best performance 5 6.5 V

- -2 2 V

(2)

- 120 - ns

- 4.4 6.5 V

Best performance 5 6.5 V

(4)

530 V

0

3.3 Thermal data

Symbol Parameter Value Unit

R

th(J-CB)_HS

R

th(J-A)

The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as per JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation is uniformly distributed over the two GaN transistors.

Thermal resistance of each transistor’s junction to relevant exposed pad, typical 4.7 °C/W

Thermal resistance junction-to-ambient(1) 18.8 °C/W

Table 4. Thermal data

DS13775 - Rev 1

page 5/26

4 Electrical characteristics

4.1 Driver

Table 5. Driver electrical characteristics

VCC = PVCC = 6 V, SENSE = GND, TJ = 25 °C, unless otherwise specified Each voltage referred to GND unless otherwise specified

Symbol - Parameter Test condition Min Typ Max Unit

VCC

I

QVCCU

I

thON

thOFF

hys

VCC vs.

GND

QVCC

SVCC

VCC UV turn ON

threshold

(1)

VCC UV turn

OFF threshold

VCC UV

hysteresis

(1)

VCC

undervoltage

quiescent supply

current

VCC quiescent

supply current

VCC switching

supply current

Logic section supply

(1)

VCC = PVCC = 3.

8 V

SD/OD = LIN = 5

HIN = 0 V;

BOOT = 7 V

SD/OD = 5 V;

VBO = 6.5 V;

VS = 0 V;

FSW = 500 kHz

MASTERGAN5

Electrical characteristics

- 4.2 4.5 4.75 V

- 3.9 4.2 4.5 V

- 0.2 0.3 0.45 V

- 320 410 μA

V;

- 680 900 μA

- 0.8 - mA

I

QPVCC

I

SPVCC

R

BLEED

RON

ROFF

V

BOthON

V

BOthOFF

V

BOhys

I

QBOU

L

PVCC vs.

PGND

GL vs. PGND

-

BOOT vs.

OUTb

PVCC quiescent

supply current

PVCC switching

supply current

Low side gate

bleeder

Low side turn on

resistance

Low side turn off

resistance

(2)

VBO UV turn ON

threshold

(3)

VBO UV turn OFF

threshold

(3)

VBO UV

hysteresis

(3)

VBO undervoltage

quiescent supply

current

(3)

Low-side driver section supply

SD/OD = LIN = 5 V - 150 - μA

VS = 0 V

FSW = 500 kHz

- 1.0 - mA

PVCC = PGND 75 100 125 kΩ

I(GL) = 1 mA

(source)

- 77 - Ω

I(GL) = 1 mA (sink) - 2 - Ω

High-side floating section supply

- 3.6 4.0 4.4 V

- 3.4 3.7 4.0 V

- 0.1 0.3 0.5 V

VBO = 3.4 V

- 140 200 μA

DS13775 - Rev 1

page 6/26

MASTERGAN5

Symbol - Parameter Test condition Min Typ Max Unit

VBO = 6 V;

LIN = GND;

SD/OD = HIN = 5

V;

VBO =6 V;

SD/OD = 5 V;

VS = 0 V;

FSW = 500 kHz

- 180 - μA

- 1.1 - mA

I

QBO

I

SBO

BOOT vs.

OUTb

BOOT

VBO quiescent

supply current

BOOT switching

supply current

(3)

Driver

I

LK

R

DBoot

RON

ROFF

V

ihys

I

INh

I

INl

R

PD_IN

I

SDh

I

SDl

R

PD_SD

V

TSD

R

ON_OD

BOOT vs.

SGND

High voltage

leakage current

BOOT = OUT = 60

0 V

- - 11 μA

SD/OD = LIN = 5

V;

VCC vs.

BOOT

Bootstrap diode

on-resistance

HIN = GND = PGN

(4)

D

- 140 175 Ω

VCC –

BOOT = 0.5 V

H

-

High side turn on

resistance

High side turn off

resistance

(2)

I(GH) = 1 mA

(source)

I(GH) = 1 mA

(sink)

- 77 - Ω

- 2 - Ω

Logic inputs

il

LIN, HIN,

ih

SD/OD

Low level logic

threshold voltage

High level logic

threshold voltage

Full Temperature

range

(5)

TJ = 25 °C

Full Temperature

range

(5)

TJ = 25 °C

1.1 1.31 1.45

V

0.8 - -

2 2.17 2.5

V

- - 2.7

Logic input

threshold

0.7 0.96 1.2 V

hysteresis

LIN, HIN

SD/OD

Logic ‘1’ input

bias current

Logic ‘0’ input

bias current

Input pull-down

resistor

Logic “1” input

bias current

Logic “0” input

bias current

Pull-down

resistor

Thermal

shutdown unlatch

LIN, HIN = 5 V 23 33 55 μA

LIN, HIN = GND - - 1 μA

LIN, HIN = 5 V 90 150 220 kΩ

SD/OD = 5 V 11 15 20 μA

SD/OD = 0 V - - 1 μA

SD/OD = 5 V

OpenDrain OFF

TJ = 25 °C

(6)

250 330 450 kΩ

0.5 0.75 1 V

threshold

SD/OD

Open drain ON

resistance

TJ = 25 °C;

IOD = 400 mV

(6)

8 10 18 Ω

DS13775 - Rev 1

I

OL_OD

T

d_GL

SD/OD

LIN, GL

Open Drain low

level sink current

Prop. delay from

LIN to GL

TJ = 25 °C;

VOD = 400 mV

(6)

22 40 50 mA

- 46 - ns

page 7/26

Symbol - Parameter Test condition Min Typ Max Unit

T

d_GH

T

TSD

T

HYS

HIN, GH

-

Prop. delay from

1. VCC UVLO is referred to VCC - GND

2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson

3. VBO = V

4. R

BD(on)

R

BD(on)

- V

BOOT

OUT

is tested in the following way

= [(VCC - V

BOOTa

) - (VCC - V

Where: Ia is BOOT pin current when V

5. Range estimated by characterization, not tested in production

6. Tested at wafer level

4.2 GaN power transistor

HIN to GH

Shut down

temperature

Temperature

hysteresis

BOOTb

BOOT

(6)

Over temperature protection

(5)

)] / [Ia - Ib]

= V

; Ib is BOOT pin current when V

BOOTa

MASTERGAN5

GaN power transistor

- 46 - ns

- 175 - °C

- 20 - °C

= V

BOOT

BOOTb

Table 6. GaN power transistor electrical characteristics

VGS = 6 V; TJ = 25 °C, unless otherwise specified.

Symbol Parameter Test condition Min Typ Max Unit

GaN on/off states

GS

(1)

650 - - V

- 0.3 - µA

(1)

(2)

T

25°C

J =

125°C

(2)

T

J =

- 1.7 - V

- 20 - µA

- 450 600

- 1012 -

I

DSS

VGS = 0 V

VDS = 600 V

VGS = 0 V

VDS = V

ID = 1.7 mA

VDS = 0 V

I

D =

V

(BR)DS

I

DSS

V

GS( th )

I

R

DS( on)

GS

Drain-source blocking voltage

Zero gate voltage drain current

Gate threshold voltage

Gate to source current

Static drain-source on-resistance

1. Tested at wafer level

2. Range estimated by characterization, not tested in production

< 6.6 µA

1.2 A

mΩ

DS13775 - Rev 1

page 8/26

ST MICROELECTRONICS MASTERGAN5 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Applications

Description

1 Block diagram

2 Pin descriptions and connection diagram

2.1 Pin list

3 Electrical Data

3.1 Absolute maximum ratings

Recommended operating conditions

3.3 Thermal data

4 Electrical characteristics

4.1 Driver

4.2 GaN power transistor