MASTERGAN4
Datasheet
High power density 600V half-bridge driver with two enhancement mode GaN
HEMT
Features
• 600 V system-in-package integrating half-bridge gate driver and high-voltage
GaN power transistors:
– QFN 9 x 9 x 1 mm package
– R
– I
• Reverse current capability
• Zero reverse recovery loss
• UVLO protection on low-side and high-side
• Internal bootstrap diode
• Interlocking function
• Dedicated pin for shut down functionality
• Accurate internal timing match
• 3.3 V to 15 V compatible inputs with hysteresis and pull-down
• Over temperature protection
• Bill of material reduction
• Very compact and simplified layout
• Flexible, easy and fast design.
DS(ON)
DS(MAX)
= 225 mΩ
= 6.5 A
Product status link
MASTERGAN4
Product label
Applications
Switch-mode power supplies
Chargers and adapters
High-voltage PFC, DC-DC and DC-AC Converters
Description
The MASTERGAN4 is an advanced power system-in-package integrating a
gate driver and two enhancement mode GaN power transistors in half bridge
configuration. The integrated power GaNs have 650 V drain-source blocking voltage
and R
easily supplied by the integrated bootstrap diode.
The MASTERGAN4 features UVLO protection on both the lower and upper
driving sections, preventing the power switches from operating in low efficiency
or dangerous conditions, and the interlocking function avoids cross-conduction
conditions.
The extended range of the input pins allows easy interfacing with microcontrollers,
DSP units or Hall effect sensors.
The MASTERGAN4 operates in the industrial temperature range, -40°C to 125°C.
The device is available in a compact 9x9 mm QFN package.
of 225 mΩ, while the high side of the embedded gate driver can be
DS(ON)
DS13686 - Rev 1 - April 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Block diagram
Driver
Driver
Logic,
interlocking,
overtemp
Level Shifter
Level Shifter
VCC UVLO
UVLO
Vbo
PGNDPVCC
OUTbBOOT
GL
GH
VCC
HIN
LIN
SD/OD
GND
OUT
VS
SENSE
HON
HOFF
LON
LOFF
R
BLEED
RGOFF
H
RGON
H
RGON
L
RGOFF
L
MASTERGAN4
Block diagram
Figure 1. Block diagram
DS13686 - Rev 1
page 2/27
2 Pin descriptions and connection diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
24
23
22
21
20
19
18
17
16
31
30
29
28
27
26
25
GND
SENSE
OUT
EP1
EP2
EP3
SENSE
OUT
OUT
OUT
SENSE
SENSE
SENSE
SENSE
SENSE
VS
VS
VS
VS
VS
GH
OUTb
BOOT
PGND
GL
PVCC
N.C.
VCC
GND
LIN
HIN
SD/OD
N.C.
N.C.
N.C.
Figure 2. Pin connections (top view)
MASTERGAN4
Pin descriptions and connection diagram
2.1 Pin list
Table 1. Pin descriptions
Pin Number Pin Name Type Function
15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)
12, 13, 14, EP3 OUT Power Output Half-bridge output
4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source)
22 BOOT Power Supply Gate driver high-side supply voltage
21 OUTb Power Supply
27 VCC Power Supply Logic supply voltage
1 PVCC Power Supply Gate driver low-side supply voltage
28, EP1 GND Power Supply Gate driver ground
3 PGND Power Supply
26 HIN Logic Input High-Side driver logic input
24 LIN Logic Input Low-Side driver logic input
25 SD/OD Logic Input-output Driver Shut-Down input and Fault Open-Drain
2 GL Output Low-Side GaN gate.
20 GH Output High-Side GaN gate.
23, 29, 30, 31 N.C. Not Connected Leave floating
Gate driver high-side supply voltage, used only for Bootstrap
capacitor connection. Internally connected to OUT.
Gate driver low-side buffer ground. Internally connected to
SENSE.
DS13686 - Rev 1
page 3/27
3 Electrical Data
3.1 Absolute maximum ratings
Each voltage referred to GND unless otherwise specified
Symbol Parameter Test Condition Value Unit
V
DS
VCC Logic supply voltage - -0.3 to 11 V
PVCC-PGND
VCC-PGND Logic supply vs Low-side driver ground - -0.3 to 18.3 V
PVCC Low-side driver supply vs logic ground - -0.3 to 18.3 V
PGND Low-side driver ground vs logic ground - -7.3 to 11.3 V
V
BO
BOOT Bootstrap voltage - -0.3 to 620 V
CGL, CGH
RGL, RGH
I
D
SR
V
T
T
1. PGND internally connected to SENSE.
2. OUTb internally connected to OUT
3. CGx < 0.08/(Pvcc^2*Fsw)-(330*10-12)
4. TCB is temperature of case exposed pad
5. Range estimated by characterization, not tested in production
6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature
GaN Drain-to-Source Voltage
Low-side driver supply voltage
BOOT to OUTb voltage
(2)
Maximum external capacitance between GL and PGND and
between GH and OUTb
Minimum external pull down resistance between GL and
PGND and GH and OUTb
Drain current
Half-bridge outputs slew rate (10% - 90%) - 100 V/ns
out
Logic inputs voltage range - -0.3 to 21 V
i
Junction temperature - -40 to 150 °C
J
Storage temperature - -40 to 150 °C
s
Table 2. Absolute maximum ratings
TJ = 25 °C
(1)
FSW = 500 kHz
DC @ TCB = 25 °C
DC @ TCB = 100 °C
Peak @ TCB = 25 °C
MASTERGAN4
Electrical Data
620 V
- -0.3 to 7 V
- -0.3 to 7 V
(3)
- 6.8 kΩ
(4) (5)
(4) (5)
(4) (5) (6)
3.9 nF
6.5 A
4.6 A
12 A
DS13686 - Rev 1
page 4/27
3.2 Recommended operating conditions
Table 3. Recommended operating conditions
Each voltage referred to GND unless otherwise specified
Symbol Parameter Note Min Max Unit
VS High voltage bus - 0 520 V
VCC Supply voltage - 4.75 9.5 V
PVCC-PGND
PVCC to PGND Low side supply
PVCC Low-side driver supply - 3 8.5 V
VCC-PVCC VCC to PVCC pin voltage - -3 3 V
PGND
Low-side driver ground
(1)
DT Suggested minimum dead time - 5 - ns
T
IN_MIN
V
BO
Minimum duration of input pulse to obtain undistorted output pulse
BOOT to OUTb pin voltage
BOOT BOOT to GND voltage -
V
T
J
Logic inputs voltage range - 0 20 V
i
Junction temperature - -40 125 °C
1. PGND internally connected to SENSE
2. See Section 6.1 Logic inputs for more detail
3. OUTb internally connected to OUT
4. 5 V is recommended during High Side turn-on
(1)
(3)
MASTERGAN4
Recommended operating conditions
- 4.75 6.5 V
Best performance 5 6.5 V
- -2 2 V
(2)
Best performance 5 6.5 V
- 120 - ns
- 4.4 6.5 V
(4)
0
530 V
3.3
Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
th(J-CB)_HS
R
th(J-A)
The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4
board as per JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation is uniformly distributed
over the two GaN transistors.
Thermal resistance of each transistor’s junction to relevant exposed pad, typical 2.8 °C/W
Thermal resistance junction-to-ambient(1) 17.8 °C/W
DS13686 - Rev 1
page 5/27
4 Electrical characteristics
4.1 Driver
Table 5. Driver electrical characteristics
VCC = PVCC = 6 V, SENSE = GND, TJ = 25 °C, unless otherwise specified
Each voltage referred to GND unless otherwise specified
Symbol - Parameter Test condition Min Typ Max Unit
VCC
VCC
VCC
I
QVCCU
I
I
thON
thOFF
hys
VCC vs. GND
QVCC
SVCC
VCC UV turn ON threshold
VCC UV turn OFF threshold
VCC UV hysteresis
VCC undervoltage quiescent
supply current
VCC quiescent supply current
VCC switching supply current
Logic section supply
(1)
(1)
(1)
VCC = PVCC = 3.8 V - 320 410 μA
SD/OD = LIN = 5 V;
HIN = 0 V;
BOOT = 7 V
SD/OD = 5 V; VBO = 6.5 V;
VS = 0 V; FSW = 500 kHz
MASTERGAN4
Electrical characteristics
- 4.2 4.5 4.75 V
- 3.9 4.2 4.5 V
- 0.2 0.3 0.45 V
- 680 900 μA
- 0.8 - mA
I
QPVCC
I
SPVCC
R
BLEED
RON
ROFF
V
BOthON
V
BOthOFF
V
BOhys
I
QBOU
I
QBO
I
SBO
I
R
DBoot
RON
ROFF
Low-side driver section supply
PVCC quiescent supply current SD/OD = LIN = 5 V - 150 - μA
PVCC vs. PGND
PVCC switching supply current
VS = 0 V
FSW = 500 kHz
- 1.0 - mA
GL vs. PGND Low side gate bleeder PVCC = PGND 75 100 125 kΩ
L
L
-
-
Low side turn on resistance
Low side turn off resistance
(2)
(2)
I(GL) = 1 mA (source) - 77 - Ω
I(GL) = 1 mA (sink) - 2 - Ω
High-side floating section supply
VBO UV turn ON threshold
VBO UV turn OFF threshold
VBO UV hysteresis
BOOT vs. OUTb
VBO undervoltage quiescent
supply current
(3)
VBO quiescent supply current
BOOT BOOT switching supply current
BOOT vs. SGND High voltage leakage current BOOT = OUT = 600 V - - 11 μA
LK
VCC vs. BOOT
Bootstrap diode on-resistance
(3)
(3)
(3)
VBO = 3.4 V
VBO = 6 V; LIN = GND;
(3)
SD/OD = HIN = 5 V;
VBO =6 V; SD/OD = 5 V;
VS = 0 V; FSW = 500 kHz
SD/OD = LIN = 5 V;
(4)
HIN = GND = PGND
- 3.6 4.0 4.4 V
- 3.4 3.7 4.0 V
- 0.1 0.3 0.5 V
- 140 200 μA
- 217 - μA
- 1.9 - mA
- 140 175 Ω
VCC – BOOT = 0.5 V
H
H
-
-
High side turn on resistance
High side turn off resistance
(2)
I(GH) = 1 mA (source) - 77 - Ω
(2)
I(GH) = 1 mA (sink) - 2 - Ω
DS13686 - Rev 1
page 6/27
MASTERGAN4
Driver
Symbol - Parameter Test condition Min Typ Max Unit
Logic inputs
V
R
PD_IN
I
I
R
PD_SD
V
R
ON_OD
V
V
ihys
I
INh
I
INl
SDh
SDl
TSD
il
ih
TJ = 25 °C
LIN, HIN, SD/OD
Low level logic threshold voltage
Full Temperature range
TJ = 25 °C
High level logic threshold voltage
Full Temperature range
(5)
(5)
Logic input threshold hysteresis 0.7 0.96 1.2 V
Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA
LIN, HIN
Logic ‘0’ input bias current LIN, HIN = GND - - 1 μA
Input pull-down
resistor
LIN, HIN = 5 V 90 150 220 kΩ
SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA
SD/OD Logic “0” input bias current SD/OD = 0 V - - 1 μA
SD/OD Pull-down resistor
SD/OD
Thermal shutdown unlatch
threshold
SD/OD Open drain ON resistance
SD/OD = 5 V
OpenDrain OFF
TJ = 25 °C
(6)
TJ = 25 °C;
IOD = 400 mV
(6)
1.1 1.31 1.45
V
0.8 - -
2 2.17 2.5
V
- - 2.7
250 330 450 kΩ
0.5 0.75 1 V
8 10 18 Ω
I
OL_OD
T
d_GL
T
d_GH
SD/OD Open Drain low level sink current
LIN, GL Prop. delay from LIN to GL
HIN, GH Prop. delay from HIN to GH
TJ = 25 °C;
VOD = 400 mV
(6)
(6)
(6)
Over temperature protection
T
TSD
T
HYS
- Shut down temperature
- Temperature hysteresis
(5)
(5)
1. VCC UVLO is referred to VCC - GND
2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson
3. VBO = V
4. R
BD(on)
R
BD(on)
Where: Ia is BOOT pin current when V
- V
BOOT
OUT
is tested in the following way
= [(VCC - V
BOOTa
) - (VCC - V
BOOTb
BOOT
)] / [Ia - Ib]
= V
BOOTa
; Ib is BOOT pin current when V
BOOT
= V
BOOTb
5. Range estimated by characterization, not tested in production
6. Tested at wafer level
22 40 50 mA
- 46 - ns
- 46 - ns
- 175 - °C
- 20 - °C
DS13686 - Rev 1
page 7/27
4.2 GaN power transistor
Table 6. GaN power transistor electrical characteristics
VGS = 6 V; TJ = 25 °C, unless otherwise specified.
Symbol Parameter Test condition Min Typ Max Unit
V
(BR)DS
Drain-source blocking voltage
GaN on/off states
I
< 13.3 µA
DSS
VGS = 0 V
MASTERGAN4
GaN power transistor
(1)
650 - - V
VDS = 600 V
VGS = 0 V
VDS = V
ID = 1.7 mA
VDS = 0 V
I
D =
I
DSS
V
GS( th )
I
GS
R
DS( on)
Zero gate voltage drain current
Gate threshold voltage
Gate to source current
Static drain-source on-resistance
1. Tested at wafer level
2. Range estimated by characterization, not tested in production
2.2 A
GS
- 0.5 - µA
(1)
(2)
T
25°C
J =
125°C
(2)
T
J =
- 1.7 - V
- 40 - µA
- 225 300
mΩ
- 495 -
DS13686 - Rev 1
page 8/27
5 Device characterization values
The information in Table 7 and Table 8 represent typical values based on characterization and simulation results
and are not tested in production.
Table 7. GaN power transistor characterization values (each transistor)
Symbol Parameter Test condition Min Typ Max Unit
Q
Total gate charge
G
Q
E
C
C
C
I
1. C
2. C
Q
Output charge
OSS
Output Capacitance stored energy - 1.7 - µJ
OSS
Output capacitance - 14.2 - pF
OSS
Effective output capacitance energy related
O(ER)
Effective output capacitance time related
O(TR)
Reverse recovery charge - - 0 - nC
RR
Reverse recovery current - - 0 - A
RRM
is the fixed capacitance that would give the same stored energy as C
O(ER)
V
DS
is the fixed capacitance that would give the same charging time as C
O(TR)
V
DS
(2)
MASTERGAN4
Device characterization values
V
6 V, TJ = 25 °C
GS =
V
0 to 400 V
DS =
VGS = 0 V, VDS = 400 V
(1)
VGS = 0 V, VDS = 0 to 400 V
while VDS is rising from 0 V to the stated
OSS
while VDS is rising from 0 V to the stated
OSS
- 1.5 - nC
- 14 - nC
- 21 - pF
- 34 - pF
Symbol
t
(on)
t
C(on)
t
(off)
t
C(off)
1. t
2. tC
t
SD
E
E
(on)
Table 8. Inductive load switching characteristics
Parameter Test condition Min Typ Max Unit
(1)
Turn-on time
(2)
Crossover time (on) - 25 - ns
(2)
Turn-off time - 70 - ns
(1)
Crossover time (off) - 10 - ns
Shutdown to high/low-side propagation delay - 70 - ns
Turn-on switching losses - 10 - µJ
on
Turn-off switching losses - 2.5 - µJ
off
and t
(on)
include the propagation delay time of the internal driver and GaN Turn on time
(off)
and tC
are the switching times of GaN transistor itself under the internally given gate driving conditions
(off)
VS = 400 V,
VGS = 6 V,
ID = 3.2 A
See Figure 3
- 70 - ns
DS13686 - Rev 1
page 9/27
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