ST MICROELECTRONICS MASTERGAN3 Datasheet

MASTERGAN3

Datasheet

High power density 600 V Half bridge driver with two enhancement mode

GaNHEMT

Features

• 600 V system-in-package integrating half-bridge gate driver and high-voltage power GaN transistors in asymmetrical configuration:

– QFN 9 x 9 x 1 mm package

– R

– I

DS(MAX)

• Reverse current capability

• Zero reverse recovery loss

• UVLO protection on low-side and high-side

• Internal bootstrap diode

• Interlocking function

• Dedicated pin for shutdown functionality

• Accurate internal timing match

• 3.3 V to 15 V compatible inputs with hysteresis and pull-down

• Overtemperature protection

• Bill of material reduction

• Very compact and simplified layout

• Flexible, easy and fast design.

= 225 mΩ (LS) + 450 mΩ (HS)

DS(ON)

= 6.5 A (LS) + 4 A (HS)

Product status link

MASTERGAN3

Product label

Application

• Switch-mode power supplies

• Chargers and adapters

• High-voltage PFC, and DC-DC converters

Description

The MASTERGAN3 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN transistors in asymmetrical half‑bridge configuration.

The integrated power GaNs have 650 V drain‑source blocking voltage and R of 225 mΩ and 450 mΩ for Low side and High side respectively, while the high

side of the embedded gate driver can be easily supplied by the integrated bootstrap diode, while the high side of the embedded gate driver can be easily supplied by the integrated bootstrap diode.

The MASTERGAN3 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions.

The input pins extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.

The MASTERGAN3 operates in the industrial temperature range, -40°C to 125°C.

The device is available in a compact 9x9 mm QFN package.

DS(ON)

DS13724 - Rev 1 - May 2021 For further information contact your local STMicroelectronics sales office.

www.st.com

1 Block diagram

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGOFF

RGON

RGOFF

MASTERGAN3

Block diagram

Figure 1. MASTERGAN3 block diagram

DS13724 - Rev 1

page 2/30

2 Pin description and connection diagram

GND

SENSE

OUT

EP1

EP2

EP3

SENSE

OUT

SENSE

OUTb

BOOT

PGND

PVCC

N.C.

VCC

GND

LIN

HIN

SD/OD

N.C.

Figure 2. Pin connection (top view)

MASTERGAN3

Pin description and connection diagram

2.1 Pin list

Table 1. Pin description

Pin Number Pin Name Type Function

15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)

12, 13, 14, EP3 OUT Power Output Half-bridge output

4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source)

22 BOOT Power Supply Gate driver high-side supply voltage

21 OUTb Power Supply

27 VCC Power Supply Logic supply voltage

1 PVCC Power Supply Gate driver low-side supply voltage

28, EP1 GND Power Supply Gate driver ground

3 PGND Power Supply

26 HIN Logic Input High-Side driver logic input

24 LIN Logic Input Low-Side driver logic input

25 SD/OD Logic Input-Output Driver Shutdown input and Fault Open-Drain

2 GL Output Low-Side GaN gate

20 GH Output High-Side GaN gate

23, 29, 30, 31 N.C. Not Connected Leave floating

Gate driver high-side reference voltage, used only for Bootstrap capacitor connection. Internally connected to OUT.

Gate driver low-side buffer ground. Internally connected to SENSE

DS13724 - Rev 1

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3 Electrical Data

3.1 Absolute maximum ratings

Each voltage referred to GND unless otherwise specified

Symbol Parameter Test Condition Value Unit

VCC Logic supply voltage -0.3 to 11 V

PVCC-PGND

VCC-PGND Logic supply vs. Low-side driver ground -0.3 to 18.3 V

PVCC Low-side driver supply vs. logic ground -0.3 to 18.3 V

PGND Low-side driver ground vs. logic ground -7.3 to 11.3 V

BOOT Bootstrap voltage -0.3 to 620 V

CGL, CGH

RGL, RGH

1. PGND internally connected to SENSE

2. OUTb internally connected to OUT

CGx < 0.08/(Pvcc^2*Fsw)-(330*10

4. TCB is temperature of case exposed pad.

5. Range estimated by characterization, not tested in production.

6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.

GaN Drain-to-Source Voltage

Low-side driver supply voltage

BOOT to OUTb voltage

(2)

Maximum external capacitance between GL and PGND and between GH and OUTb

Minimum external pull-down resistance between GL and PGND and GH and OUTb

Drain current (Low side GaN transistor)

Drain current (High side GaN transistor)

Half-bridge outputs slew rate (10% - 90%) 100 V/ns

out

Logic inputs voltage range -0.3 to 21 V

Junction temperature -40 to 150 °C

Storage temperature -40 to 150 °C

-12

)

Table 2. Absolute maximum ratings

(1)

DC @ TCB = 25°C

DC @ TCB = 100°C

Peak @ TCB = 25°C

DC @ TCB = 25°C

DC @ TCB = 100°C

Peak @ TCB = 25°C

TJ = 25 °C

Fsw = 500 kHz

MASTERGAN3

Electrical Data

620 V

-0.3 to 7 V

(3)

(4) (5)

(4) (5) (6)

(4) (5)

(4) (5) (6)

3.9 nF

6.8 kΩ

6.5 A

4.4 A

12 A

4 A

2.6 A

7 A

DS13724 - Rev 1

page 4/30

3.2 Recommended operating conditions

Table 3. Recommended operating conditions

Each voltage referred to GND unless otherwise specified

Symbol Parameter Note Min Max Unit

VS High voltage bus 0 520 V

VCC Supply voltage 4.75 9.5 V

PVCC-PGND

PVCC Low-side driver supply voltage 3 8.5 V

VCC-PVCC VCC to PVCC pin voltage -3 3 V

PGND

DT Suggested minimum deadtime 5 ns

IN_MIN

BOOT BOOT to GND voltage

1. PGND internally connected to SENSE

2. OUTb internally connected to OUT

3. 5 V is recommended during high-hide turn-on

PVCC to PGND low side supply voltage

Low-side driver ground

(1)

Minimum duration of input pulse to obtain undistorted output pulse 120 ns

BOOT to OUTb pin voltage

Logic inputs voltage range 0 20 V

(2)

Junction temperature -40 125 °C

MASTERGAN3

Recommended operating conditions

(1)

Best performance 5 6.5 V

4.75 6.5 V

-2 2 V

4.4 6.5 V

(3)

530 V

3.3

Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

th(J-CB)_LS

th(J-CB)_HS

th(J-A)

1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.

Thermal resistance Low side junction to SENSE exposed pad, typical 2.8 °C/W

Thermal resistance High side junction to OUT exposed pad, typical 4.7 °C/W

Thermal resistance junction-to-ambient

(1)

18.8 °C/W

DS13724 - Rev 1

page 5/30

4 Electrical characteristics

4.1 Driver

Table 5. Driver electrical characteristics

VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise specified (each voltage referred to GND unless otherwise specified)

Symbol Parameter Test condition Min Typ Max Unit

VCC

QVCCU

thON

thOFF

hys

VCC vs. GND

QVCC

SVCC

VCC UV turn ON threshold

VCC UV turn OFF threshold

VCC UV hysteresis

VCC undervoltage quiescent supply current VCC = PVCC = 3.8 V 320 410 μA

VCC quiescent supply current

VCC switching supply current

Logic section supply

(1)

SD/OD = LIN = 5 V; HIN = 0 V; BOOT = 7 V

SD/OD = 5 V; VBO = 6.5 V;

VS = 0 V; FSW = 500 kHz

MASTERGAN3

Electrical characteristics

4.2 4.5 4.75 V

3.9 4.2 4.5 V

0.2 0.3 0.45 V

680 900 μA

0.8 mA

QPVCC

SPVCC

BLEED

RON

ROFF

BOthON

BOthOFF

BOhys

QBOU

QBO

SBO

DBoot

RON

Low-side driver section supply

PVCC quiescent supply current SD/OD = LIN = 5 V 150 μA

PVCC vs. PGND

PVCC switching supply current

VS = 0 V

FSW = 500 kHz

1 mA

GL vs. PGND Low side gate bleeder PVCC = PGND 75 100 125 kΩ

Low side turn on resistance

Low side turn off resistance

(2)

I(GL) = 1 mA (source) 77 Ω

I(GL) = 1 mA (sink) 2 Ω

High-side floating section supply

(3)

VBO = 3.4 V

(3)

VBO = 6 V; LIN = GND;

SD/OD = HIN = 5 V;

3.6 4.0 4.4 V

3.4 3.7 4.0 V

0.1 0.3 0.5 V

140 200 μA

180 μA

BOOT vs. OUTb

VBO UV turn ON threshold

VBO UV turn OFF threshold

VBO UV hysteresis

VBO undervoltage quiescent supply

(3)

current

VBO quiescent supply current

VBO = 6 V;

BOOT BOOT switching supply current

SD/OD = 5 V;

1.1 mA

VS = 0 V; FSW = 500 kHz

BOOT vs. SGND High voltage leakage current BOOT = OUT = 600 V 11 μA

SD/OD = LIN = 5 V;

VCC vs. BOOT

Bootstrap diode on resistance

(4)

HIN = GND = PGND

140 175 Ω

VCC – BOOT = 0.5 V

High side turn on resistance

(2)

I(GH) = 1 mA (source) 77 Ω

DS13724 - Rev 1

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MASTERGAN3

Symbol Parameter Test condition Min Typ Max Unit

ROFF

ihys

INh

PD_IN

SDh

SDl

PD_SD

TSD

ON_OD

OL_OD

d,GL

d,GH

INl

LIN, HIN, SD/OD

LIN, HIN

SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA

SD/OD Logic “0” input bias current SD/OD = 0 V 1 μA

SD/OD Pull-down resistor

SD/OD Thermal shutdown unlatch threshold

SD/OD Open drain ON resistance

SD/OD Open Drain low level sink current

LIN, GL Prop. delay from LIN to GL

HIN, GH Prop. delay from HIN to GH

High side turn off resistance

Low level logic threshold

High level logic threshold

Logic input threshold hysteresis 0.7 0.96 1.2 V

Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA

Logic ‘0’ input bias current LIN, HIN = GND 1 μA

Input pull-down resistor LIN, HIN = 5 V 90 150 220 kΩ

Overtemperature protection

TSD

HYS

Shutdown temperature

Temperature hysteresis

1. VCC UVLO is referred to VCC - GND

2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson

3. VBO = V

4. R

BD(on)

Where: Ia is BOOT pin current when V

- V

BOOT

OUT

is tested in the following way:

= [(VCC - V

BOOTa

) - (VCC - V

BOOTb

BOOT

)] / [Ia - Ib]

= V

5. Range estimated by characterization, not tested in production.

6. Tested at wafer level.

(2)

Logic inputs

; Ib is BOOT pin current when V

BOOTa

I(GH) = 1 mA (sink) 2 Ω

TJ = 25°C

Full Temperature range

TJ = 25°C

Full Temperature range

SD/OD = 5 V

OpenDrain OFF

TJ = 25°C

(6)

TJ = 25°C;

= 400 mV

(6)

TJ = 25°C;

VOD = 400 mV

(6)

(5)

(6)

BOOT

= V

1.1 1.31 1.45

(5)

0.8

2 2.17 2.5

(5)

250 330 450 kΩ

0.5 0.75 1 V

8 10 18 Ω

22 40 50 mA

175 °C

BOOTb

2.7

46 ns

20 °C

Driver

DS13724 - Rev 1

page 7/30

4.2 GaN power transistor

Table 6. GaN power transistor electrical characteristics

= 6 V; TJ = 25°C, unless otherwise specified

Symbol Parameter Test condition Min Typ Max Unit

(BR)DS

Drain-source blocking voltage

GaN on/off states

Low side I

High side I

VGS = 0 V

< 13.3 µA

DSS

< 6.6 µA

DSS

MASTERGAN3

GaN power transistor

(1)

650 V

DS(on)_LS

DS(on)_HS

DSS_LS

DSS_HS

GS(th)

GS_LS

GS_HS

Zero gate voltage drain current - low side

Zero gate voltage drain current - high side

Gate threshold voltage

Gate to source current - Low side

Gate to source current - High side

Static drain-source on-resistance - Low side

Static drain-source on-resistance - High side

1. Tested at wafer level.

2. Value estimated by characterization, not tested in production.

VDS = 600 V

VGS = 0 V

VDS = 600 V

VGS = 0 V

VDS = V

Low side, ID = 2.5 mA

High side, ID = 1.7 mA

VDS = 0 V

(2)

TJ = 25°C

ID = 2.2 A

TJ = 125°C

TJ = 25°C

ID = 1.2 A

TJ = 125°C

0.5 µA

0.3 µA

(1)

1.7 V

40 µA

20 µA

225 300

(2)

495

mΩ

450 600

(2)

1012

mΩ

DS13724 - Rev 1

page 8/30

5 Device characterization values

The information in Table 7 and Table 8 represents typical values based on characterization and simulation results and are not subject to the production test.

Table 7. GaN power transistor characterization values

Symbol Parameter Test condition Min Typ Max Unit

Total gate charge

Device characterization values

VGS = 6 V, TJ = 25°C

VDS = 0 to 400 V - Low side

VGS = 6 V, TJ = 25°C

VDS = 0 to 400 V - High side

MASTERGAN3

1.5 nC

0.8 nC

O(ER)

RRM

1. C

2. C

Symbol

C(on)

t(off)

C(off)

Output charge - Low side

OSS

Output charge - High side 7 nC

Output capacitance stored energy - Low side 1.7 µJ

OSS

Output capacitance stored energy - High side 0.9 µJ

VGS = 0 V,

VDS = 400 V

Output capacitance - Low side 14.2 pF

OSS

Output capacitance - High side 7 pF

Effective output capacitance energy related - Low side

Effective output capacitance energy related - High side

Effective output capacitance time related - Low side

O(TR)

Effective output capacitance time related - High side

Reverse recovery charge 0 nC

(1)

(2)

= 0 V,

VDS = 0 to 400 V

Reverse recovery current 0 A

is the fixed capacitance that would give the same stored energy as C

O(ER)

is the fixed capacitance that would give the same charging time as C

O(TR)

while VDS is rising from 0 V to the stated

OSS

while VDS is rising from 0 V to the stated

OSS

Table 8. Inductive load switching characteristics

Parameter Test condition Min Typ Max Unit

(on)

Turn-on time - Low side

(1)

Turn-on time - High side 70 ns

Crossover time (on) - Low side 15 ns

(2)

Crossover time (on) - High side 25 ns

Turn-off time - Low side 70 ns

(1)

Turn-off time - High side 70 ns

Crossover time (off) - Low side 15 ns

(2)

Crossover time (off) - High side 10 ns

Shutdown to high/low-side propagation delay 70 ns

VS = 400 V,

VGS = 6 V,

=2.2 A,

D_LS

=1.2 A

D_HS

See Figure 3

Turn-on switching losses - Low side 10 µJ

Turn-on switching losses - High side 4.5 µJ

70 ns

14 nC

21 pF

11 pF

34 pF

17 pF

DS13724 - Rev 1

page 9/30

+ 21 hidden pages

ST MICROELECTRONICS MASTERGAN3 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Application

Description

1 Block diagram

2 Pin description and connection diagram

2.1 Pin list

3 Electrical Data

3.1 Absolute maximum ratings

3.2 Recommended operating conditions

Thermal data

4 Electrical characteristics

4.1 Driver

4.2 GaN power transistor

5 Device characterization values