MASTERGAN2
Datasheet
High power density 600V Half bridge driver with two enhancement mode GaN
HEMT
Features
• 600 V system-in-package integrating half-bridge gate driver and high-voltage
power GaN transistors in asymmetrical configuration:
– QFN 9 x 9 x 1 mm package
– R
– I
DS(MAX)
• Reverse current capability
• Zero reverse recovery loss
• UVLO protection on low-side and high-side
• Internal bootstrap diode
• Interlocking function
• Dedicated pin for shutdown functionality
• Accurate internal timing match
• 3.3 V to 15 V compatible inputs with hysteresis and pull-down
• Overtemperature protection
• Bill of material reduction
• Very compact and simplified layout
• Flexible, easy and fast design.
= 150 mΩ (LS) + 225 mΩ (HS)
DS(ON)
= 10 A (LS) + 6.5 A (HS)
Product status link
MASTERGAN2
Product label
Application
• Switch-mode power supplies
• Chargers and adapters
• High-voltage PFC, and DC-DC converters
Description
The MASTERGAN2 is an advanced power system-in-package integrating a gate
driver and two enhancement mode GaN transistors in asymmetrical half‑bridge
configuration.
The integrated power GaNs have 650 V drain‑source blocking voltage and R
of 150 mΩ and 225 mΩ for Low side and High side respectively, while the high
side of the embedded gate driver can be easily supplied by the integrated bootstrap
diode.
The MASTERGAN2 features UVLO protection on both the lower and upper
driving sections, preventing the power switches from operating in low efficiency
or dangerous conditions, and the interlocking function avoids cross-conduction
conditions.
The input pins extended range allows easy interfacing with microcontrollers, DSP
units or Hall effect sensors.
The MASTERGAN2 operates in the industrial temperature range, -40°C to 125°C.
The device is available in a compact 9x9 mm QFN package.
DS(ON)
DS13597 - Rev 2.0 - June 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Block diagram
Driver
Driver
Logic,
interlocking,
overtemp
Level Shifter
Level Shifter
VCC UVLO
UVLO
Vbo
PGNDPVCC
OUTbBOOT
GL
GH
VCC
HIN
LIN
SD/OD
GND
OUT
VS
SENSE
HON
HOFF
LON
LOFF
R
BLEED
RGOFF
H
RGON
H
RGON
L
RGOFF
L
MASTERGAN2
Block diagram
Figure 1. MASTERGAN2 block diagram
DS13597 - Rev 2.0
page 2/29
2 Pin description and connection diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
24
23
22
21
20
19
18
17
16
31
30
29
28
27
26
25
GND
SENSE
OUT
EP1
EP2
EP3
SENSE
OUT
OUT
OUT
SENSE
SENSE
SENSE
SENSE
SENSE
VS
VS
VS
VS
VS
GH
OUTb
BOOT
PGND
GL
PVCC
N.C.
VCC
GND
LIN
HIN
SD/OD
N.C.
N.C.
N.C.
Figure 2. Pin connection (top view)
MASTERGAN2
Pin description and connection diagram
2.1 Pin list
Table 1. Pin description
Pin Number Pin Name Type Function
15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)
12, 13, 14, EP3 OUT Power Output Half-bridge output
4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source)
22 BOOT Power Supply Gate driver high-side supply voltage
21 OUTb Power Supply
27 VCC Power Supply Logic supply voltage
1 PVCC Power Supply Gate driver low-side supply voltage
28, EP1 GND Power Supply Gate driver ground
3 PGND Power Supply
26 HIN Logic Input High-Side driver logic input
24 LIN Logic Input Low-Side driver logic input
25 SD/OD Logic Input-Output Driver Shutdown input and Fault Open-Drain
2 GL Output Low-Side GaN gate
20 GH Output High-Side GaN gate
23, 29, 30, 31 N.C. Not Connected Leave floating
Gate driver high-side reference voltage, used only for Bootstrap
capacitor connection. Internally connected to OUT.
Gate driver low-side buffer ground. Internally connected to
SENSE
DS13597 - Rev 2.0
page 3/29
3 Electrical Data
3.1 Absolute maximum ratings
each voltage referred to GND unless otherwise specified
Symbol Parameter Test Condition Value Unit
V
DS
VCC Logic supply voltage -0.3 to 11 V
PVCC-PGND
VCC-PGND Logic supply vs. Low-side driver ground -0.3 to 18.3 V
PVCC Low-side driver supply vs. logic ground -0.3 to 18.3 V
PGND Low-side driver ground vs. logic ground -7.3 to 11.3 V
V
BO
BOOT Bootstrap voltage -0.3 to 620 V
CGL, CGH
RGL, RGH
I
D
I
D
SR
V
T
T
1. PGND internally connected to SENSE
2. OUTb internally connected to OUT
3.
CGx < 0.08/(Pvcc^2*Fsw)-(330*10
4. TCB is temperature of case exposed pad.
5. Range estimated by characterization, not tested in production.
6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.
GaN Drain-to-Source Voltage
Low-side driver supply voltage
BOOT to OUTb voltage
(2)
Maximum external capacitance between GL and PGND and
between GH and OUTb
Minimum external pull-down resistance between GL and
PGND and GH and OUTb
Drain current (Low side GaN transistor)
Drain current (High side GaN transistor)
Half-bridge outputs slew rate (10% - 90%) 100 V/ns
out
Logic inputs voltage range -0.3 to 21 V
i
Junction temperature -40 to 150 °C
J
Storage temperature -40 to 150 °C
s
-12
)
Table 2. Absolute maximum ratings
(1)
DC @ TCB = 25°C
DC @ TCB = 100°C
Peak @ TCB = 25°C
DC @ TCB = 25°C
DC @ TCB = 100°C
Peak @ TCB = 25°C
TJ = 25 °C
Fsw = 500 kHz
MASTERGAN2
Electrical Data
620 V
-0.3 to 7 V
-0.3 to 7 V
(3)
(4) (5)
(4) (5)
(4) (5) (6)
(4) (5)
(4) (5)
(4) (5) (6)
3.9 nF
6.8 kΩ
9.7 A
6.4 A
17 A
6.5 A
4.4 A
12 A
DS13597 - Rev 2.0
page 4/29
3.2 Recommended operating conditions
Table 3. Recommended operating conditions
Each voltage referred to GND unless otherwise specified
Symbol Parameter Note Min Max Unit
VS High voltage bus 0 520 V
VCC Supply voltage 4.75 9.5 V
PVCC-PGND
PVCC Low-side driver supply voltage 3 8.5 V
VCC-PVCC VCC to PVCC pin voltage -3 3 V
PGND
DT Suggested minimum deadtime 5 ns
T
IN_MIN
V
BO
BOOT BOOT to GND voltage
V
T
J
1. PGND internally connected to SENSE
2. OUTb internally connected to OUT
3. 5 V is recommended during high-hide turn-on
PVCC to PGND low side supply voltage
Low-side driver ground
(1)
Minimum duration of input pulse to obtain undistorted output pulse 120 ns
BOOT to OUTb pin voltage
Logic inputs voltage range 0 20 V
i
(2)
Junction temperature -40 125 °C
MASTERGAN2
Recommended operating conditions
(1)
Best performance 5 6.5 V
Best performance 5 6.5 V
4.75 6.5 V
-2 2 V
4.4 6.5 V
(3)
530 V
0
3.3
Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
th(J-CB)_LS
R
th(J-CB)_HS
R
th(J-A)
1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as
JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.
Thermal resistance Low side junction to SENSE exposed pad, typical 1.9 °C/W
Thermal resistance High side junction to OUT exposed pad, typical 2.8 °C/W
Thermal resistance junction-to-ambient
(1)
17.8 °C/W
DS13597 - Rev 2.0
page 5/29
4 Electrical characteristics
4.1 Driver
Table 5. Driver electrical characteristics
VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise specified (each voltage referred to GND unless otherwise
specified)
Symbol Parameter Test condition Min Typ Max Unit
VCC
VCC
VCC
I
QVCCU
I
I
thON
thOFF
hys
VCC vs. GND
QVCC
SVCC
VCC UV turn ON threshold
VCC UV turn OFF threshold
VCC UV hysteresis
VCC undervoltage quiescent supply current VCC = PVCC = 3.8 V 320 410 μA
VCC quiescent supply current
VCC switching supply current
Logic section supply
(1)
(1)
(1)
SD/OD = LIN = 5 V;
HIN = 0 V;
BOOT = 7 V
SD/OD = 5 V;
VBO = 6.5 V;
VS = 0 V; FSW = 500 kHz
MASTERGAN2
Electrical characteristics
4.2 4.5 4.75 V
3.9 4.2 4.5 V
0.2 0.3 0.45 V
680 900 μA
0.8 mA
I
QPVCC
I
SPVCC
R
BLEED
RON
ROFF
V
BOthON
V
BOthOFF
V
BOhys
I
QBOU
I
QBO
I
SBO
I
LK
R
DBoot
RON
ROFF
Low-side driver section supply
PVCC quiescent supply current SD/OD = LIN = 5 V 150 μA
PVCC vs. PGND
PVCC switching supply current
VS = 0 V
FSW = 500 kHz
1.4 mA
GL vs. PGND Low side gate bleeder PVCC = PGND 75 100 125 kΩ
L
L
Low side turn on resistance
Low side turn off resistance
(2)
(2)
I(GL) = 1 mA (source) 52 Ω
I(GL) = 1 mA (sink) 2 Ω
High-side floating section supply
(3)
(3)
(3)
VBO = 3.4 V
(3)
VBO = 6 V; LIN = GND;
SD/OD = HIN = 5 V;
3.6 4.0 4.4 V
3.4 3.7 4.0 V
0.1 0.3 0.5 V
140 200 μA
217 μA
BOOT vs. OUTb
VBO UV turn ON threshold
VBO UV turn OFF threshold
VBO UV hysteresis
VBO undervoltage quiescent supply
(3)
current
VBO quiescent supply current
VBO = 6 V;
BOOT BOOT switching supply current
SD/OD = 5 V;
1.9 mA
VS = 0 V; FSW = 500 kHz
BOOT vs. SGND High voltage leakage current BOOT = OUT = 600 V 11 μA
SD/OD = LIN = 5 V;
VCC vs. BOOT
Bootstrap diode on resistance
(4)
HIN = GND = PGND
140 175 Ω
VCC – BOOT = 0.5 V
H
H
High side turn on resistance
High side turn off resistance
(2)
(2)
I(GH) = 1 mA (source) 77 Ω
I(GH) = 1 mA (sink) 2 Ω
DS13597 - Rev 2.0
page 6/29
MASTERGAN2
Symbol Parameter Test condition Min Typ Max Unit
Logic inputs
TJ = 25°C
V
I
R
PD_IN
I
I
R
PD_SD
V
R
ON_OD
I
OL_OD
T
T
d_GH
V
il
V
ih
ihys
INh
I
INl
SDh
SDl
TSD
d_GL
LIN, HIN, SD/OD
LIN, HIN
SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA
SD/OD Logic “0” input bias current SD/OD = 0 V 1 μA
SD/OD Pull-down resistor
SD/OD Thermal shutdown unlatch threshold
SD/OD Open drain ON resistance
SD/OD Open Drain low level sink current
LIN,GL Prop. delay from LIN to GL
HIN,GH Prop. delay from HIN to GH
Low level logic threshold
Full Temperature range
TJ = 25°C
High level logic threshold
Full Temperature range
Logic input threshold hysteresis 0.7 0.96 1.2 V
Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA
Logic ‘0’ input bias current LIN, HIN = GND 1 μA
Input pull-down resistor LIN, HIN = 5 V 90 150 220 kΩ
SD/OD = 5 V
OpenDrain OFF
TJ = 25°C
(6)
TJ = 25°C;
I
OD
= 400 mV
(6)
TJ = 25°C;
VOD = 400 mV
(6)
(6)
(6)
Overtemperature protection
T
TSD
T
HYS
Shutdown temperature
Temperature hysteresis
(5)
(5)
1. VCC UVLO is referred to VCC - GND
2. Turn on and turn off total resistances include the values of the gate resistors and the driver Rdson
3. VBO = V
4. R
BD(on)
R
BD(on)
Where: Ia is BOOT pin current when V
- V
BOOT
OUT
is tested in the following way:
= [(VCC - V
BOOTa
) - (VCC - V
BOOTb
BOOT
)] / [Ia - Ib]
= V
BOOTa
; Ib is BOOT pin current when V
BOOT
= V
5. Range estimated by characterization, not tested in production.
6. Tested at wafer level.
1.1 1.31 1.45
(5)
0.8
2 2.17 2.5
(5)
250 330 450 kΩ
0.5 0.75 1 V
8 10 18 Ω
22 40 50 mA
- 46 -
- 46 -
175 °C
BOOTb
2.7
20 °C
Driver
V
V
DS13597 - Rev 2.0
page 7/29
4.2 GaN power transistor
Table 6. GaN power transistor electrical characteristics
V
= 6 V; TJ = 25°C, unless otherwise specified
GS
Symbol Parameter Test condition Min Typ Max Unit
V
(BR)DS
Drain-source blocking voltage
GaN on/off states
Low side I
High side I
VGS = 0 V
DSS
DSS
< 18 µA
< 13.3 µA
MASTERGAN2
GaN power transistor
(1)
(1)
650 V
I
R
R
I
DSS_LS
DSS_HS
V
GS(th)
I
GS_LS
I
GS_HS
DS(on)_LS
DS(on)_HS
Zero gate voltage drain current - low side
Zero gate voltage drain current - high side
Gate threshold voltage
Gate to source current - Low side
Gate to source current - High side
Static drain-source on-resistance - Low side
Static drain-source on-resistance - High side
1. Tested at wafer level.
2. Value estimated by characterization, not tested in production.
VDS = 600 V
VGS = 0 V
VDS = 600 V
VGS = 0 V
VDS = V
GS
Low side, ID = 2.5 mA
High side, ID = 1.7 mA
VDS = 0 V
VDS = 0 V
(2)
(2)
TJ = 25°C
ID = 3.2 A
TJ = 125°C
TJ = 25°C
ID = 2.2 A
TJ = 125°C
0.7 µA
0.5 µA
(1)
(1)
1.7 V
57 µA
40 µA
150 220
(2)
330
mΩ
225 300
(2)
495
mΩ
DS13597 - Rev 2.0
page 8/29
5 Device characterization values
The information in Table 7 and Table 8 represents typical values based on characterization and simulation results
and are not subject to the production test.
Table 7. GaN power transistor characterization values
Symbol Parameter Test condition Min Typ Max Unit
Q
Total gate charge
G
Device characterization values
VGS = 6 V, TJ = 25°C
VDS = 0 to 400 V - Low side
VGS = 6 V, TJ = 25°C
VDS = 0 to 400 V - High side
MASTERGAN2
2 nC
1.5 nC
Q
E
C
C
O(ER)
C
Q
I
RRM
1. C
2. C
Symbol
t
t
C(on)
t(off)
t
C(off)
Output charge - Low side
OSS
Output charge - High side 14 nC
Output capacitance stored energy - Low side 2.7 µJ
OSS
Output capacitance stored energy - High side 1.7 µJ
VGS = 0 V,
VDS = 400 V
Output capacitance - Low side 20 pF
OSS
Output capacitance - High side 14.2 pF
Effective output capacitance energy related - Low side
Effective output capacitance energy related - High side
Effective output capacitance time related - Low side
O(TR)
Effective output capacitance time related - High side
Reverse recovery charge 0 nC
RR
(1)
(1)
(2)
(2)
V
= 0 V,
GS
VDS = 0 to 400 V
Reverse recovery current 0 A
is the fixed capacitance that would give the same stored energy as C
O(ER)
V
DS
is the fixed capacitance that would give the same charging time as C
O(TR)
V
DS
while VDS is rising from 0 V to the stated
OSS
while VDS is rising from 0 V to the stated
OSS
Table 8. Inductive load switching characteristics
Parameter Test condition Min Typ Max Unit
(on)
t
E
Turn-on time - Low side
(1)
Turn-on time - High side 70 ns
Crossover time (on) - Low side 15 ns
(2)
Crossover time (on) - High side 25 ns
Turn-off time - Low side 70 ns
(1)
Turn-off time - High side 70 ns
Crossover time (off) - Low side 15 ns
(2)
Crossover time (off) - High side 10 ns
Shutdown to high/low-side propagation delay 70 ns
SD
VS = 400 V,
VGS = 6 V,
I
= 3.2 A,
D_LS
I
= 2.2 A
D_HS
See Figure 3
Turn-on switching losses - Low side 12.5 µJ
on
Turn-on switching losses - High side 10 µJ
70 ns
20 nC
31 pF
21 pF
50 pF
34 pF
DS13597 - Rev 2.0
page 9/29
I
D
I
D
V
DS
V
DS
V
IN
V
IN
t
(ON)
t
(OFF)
t
C(ON)
t
C(OFF)
10%I
D
10%V
DS
10%I
D
10%V
DS
(a) turn-on
(b) turn-off
0
1
2 3
4
5
VDS (V)
I
D
(A)
0
10
5
15
20
25
30
TJ=25°C
4V
5V
6V
0
1
2 3
4
5
VDS (V)
I
D
(A)
0
4
2
6
8
10
12
TJ=125°C
4V
5V
6V
MASTERGAN2
Device characterization values
Symbol Parameter Test condition Min Typ Max Unit
VS = 400 V,
VGS = 6 V,
I
= 3.2 A,
D_LS
I
= 2.2 A
D_HS
See Figure 3
1. t
2. t
E
off
(on)
C(on)
Turn-off switching losses 2.5 µJ
and t
include the propagation delay time of the internal driver
(off)
and t
are the switching times of GaN transistor itself under the internally given gate driving conditions
C(off)
Figure 3. Switching time definition
DS13597 - Rev 2.0
Figure 4. Typ I
vs. VDS at TJ=25°C
D_LS
Figure 5. Typ I
vs. VDS at TJ=125°C
D_LS
page 10/29
VDS (V)
I
D
(A)
VGS=6V
TJ=25°C
VGS=5V
0
1 2 3 4 5
0
2
4
6
8
10
12
14
16
18
20
VGS=4V
VDS (V)
I
D
(A)
VGS=6V
TJ=125°C
VGS=5V
0
1 2 3 4 5
0
1
2
3
4
5
6
7
8
9
10
VGS=4V
0
5 10 15 20 25
30
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
TJ=25°C
4V
5V
6V
ID (A)
R
DS(on)
(Ω)
0
2 4
6 8 10
12
0.31
0.33
0.35
0.37
0.39
0.41
0.43
0.45
0.47
TJ=125°C
4V
5V
6V
ID (A)
R
DS(on)
(Ω)
MASTERGAN2
Device characterization values
Figure 6. Typ I
Figure 8. Typ R
vs. VDS at TJ=25°C
D_HS
DS(on)_LS
vs. ID at TJ=25°C
Figure 7. Typ I
Figure 9. Typ R
vs. VDS at TJ=125°C
D_HS
DS(on)_LS
vs. ID at TJ=125°C
DS13597 - Rev 2.0
page 11/29
0
2
10 18 20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
TJ=25°C
ID (A)
R
DS(on)
(Ω)
4V
5V
6V
16
14124
86
0
1
5 9 10
0.45
0.48
0.51
0.54
0.57
0.60
0.63
0.66
0.69
TJ=125°C
ID (A)
R
DS(on)
(Ω)
4V
5V
6V
8
762
43
0
1
2 3
4
5
VDS (V)
I
D
(A)
0
10
5
15
20
25
30
VGS=6V
TJ=25°C
TJ=50°C
TJ=75°C
TJ=125°C
TJ=100°C
VDS (V)
I
D
(A)
VGS=6V
TJ=25°C
0
1 2 3 4 5
0
2
4
6
8
10
12
14
16
18
20
TJ=50°C
TJ=75°C
TJ=100°C
TJ=125°C
MASTERGAN2
Device characterization values
Figure 10. Typ R
Figure 12. Typ I
DS(on)_HS
D_LS
vs. ID at TJ=25°C
vs. V
DS
Figure 11. Typ R
Figure 13. Typ I
DS(on)_HS
vs. ID at TJ=125°C
vs. V
D_HS
DS
DS13597 - Rev 2.0
page 12/29
Normalized R
DS(on)
(1 at 25°C)
0
1.0
0.5
1.5
2.0
2.5
3.0
Temperature (°C)
-50
-10
30
70
110
150
VSD (V)
I
S
(A)
VGS=6V
TJ=25°C
VGS=0V
0
1 2 3 4 5 6 7 8 9 10
0
5
10
15
20
25
30
35
40
45
50
TJ=125°C
VSD (V)
I
S
(A)
0
1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
12
14
16
18
20
22
24
VGS=6V
VGS=0V
MASTERGAN2
Device characterization values
Figure 15. Typ I
SD_LS
Figure 14. Typ R
vs. V
SD_LS
DS(on)
at TJ=25°C
vs. TJ normalized at 25°C
Figure 16. Typ I
SD_LS
vs. V
SD_LS
at TJ=125°C
DS13597 - Rev 2.0
page 13/29
VSD (V)
I
S
(A)
VGS=6V
TJ=25°C
VGS=0V
0
1 2 3 4 5 6 7 8 9 10
0
4
8
12
16
20
24
28
32
36
40
VSD (V)
I
S
(A)
VGS=6V
TJ=125°C
VGS=0V
0
1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
12
14
16
18
20
1
10
100
1000
0.01
0.1
1
10
DC
50 μs
0.2 μs
Id (A)
Vds (V)
1
10
100
1000
0.01
0.1
1
10
DC
50 μs
0.2 μs
Id (A)
Vds (V)
MASTERGAN2
Device characterization values
Figure 17. Typ I
SD_HS
vs. V
SD_HS
at TJ=25°C
Figure 19. Safe Operating Area (LS) at TJ=25°C
Figure 18. Typ I
SD_HS
vs. V
SD_HS
at TJ=125°C
Figure 20. Safe Operating Area (HS) at TJ=25°C
DS13597 - Rev 2.0
page 14/29
0 0.5
1
1.5
2
2.5
QG (nC)
V
GS
(V)
0
2
1
3
4
5
6
400 V
100 V
7
0 0.5
1
1.5
2
2.5
QG (nC)
V
GS
(V)
0
2
1
3
4
5
6
400 V
100 V
7
0
25
50
75
100
125
TCB (°C)
0
150
10
20
30
40
50
60
70
P
DISS
(W)
0
25
50
75
100
125
TCB (°C)
0
150
10
20
30
40
50
60
70
P
DISS
(W)
MASTERGAN2
Device characterization values
Figure 21. Typical Gate Charge (LS) at TJ=25°C
Figure 23. LS Derating curve
Figure 22. Typical Gate Charge (HS) at TJ=25°C
Figure 24. HS Derating curve
DS13597 - Rev 2.0
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R
DBoot
(Ω)
0
100
50
150
200
250
300
Temperature (°C)
-50
-10
30
70
110
150
MASTERGAN2
Device characterization values
Figure 25. Typ R
Dboot
vs. T
J
DS13597 - Rev 2.0
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6 Functional description
6.1 Logic inputs
The MASTERGAN2 features a half-bridge gate driver with three logic inputs to control the internal high-side and
low-side GaN transistors.
The devices are controlled through the following logic inputs:
• SD/OD: Shutdown input, active low
• LIN: low-side driver inputs, active high
• HIN: high-side driver inputs, active high
Table 9. Inputs truth table (applicable when device is not in UVLO)
Input pins GaN transistors status
SD/OD LIN HIN LS HS
L
H L L OFF OFF
H L H OFF ON
H H L ON OFF
1. X: Don’t care
2. Interlocking
H
(1)
X
(2)
H
MASTERGAN2
Functional description
(1)
X
(2)
H
OFF OFF
OFF OFF
The logic inputs have internal pull-down resistors. The purpose of these resistors is to set a proper logic level in
case, for example, there is an interruption in the logic lines or the controller outputs are in tri-state conditions.
If logic inputs are left floating, the gate driver outputs are set to low level and the correspondent GaN transistors
are turned off.
The minimum duration of the on time of the pulses applied to LIN is T
either extended to T
or blanked, when shorter than 30ns (typ).
IN_MIN
The minimum duration of the off time of the pulses applied to HIN is T
either extended to T
Interlocking feature interrupts running T
or blanked, when shorter than 30ns (typ).
IN_MIN
to avoid unexpected cross-conduction.
IN_MIN
Matched, short propagation delay between low side and high side are there.
6.2
Bootstrap structure
A bootstrap circuitry is typically used to supply the high-voltage section. MASTERGAN2 integrates this structure,
realized by a patented integrated high-voltage DMOS, to reduce the external components.
The Boostrap integrated circuit is connected to VCC pin and is driven synchronously with the low-side driver.
The use of an external bootstrap diode in parallel to the integrated structure is possible, in particular if the
operating frequency is approximately higher than 500 kHz.
6.3 VCC supply pins and UVLO function
The VCC pin supplies current to the logic circuit, level-shifters in the low-side section and the integrated bootstrap
diode.
The PVCC pin supplies low-side output buffer. During output commutations the average current used to provide
gate charge to the high-side and low-side GaN transistors flows through this pin.
= 120ns; shorter pulses shall be
IN_MIN
= 120ns; shorter pulses shall be
IN_MIN
DS13597 - Rev 2.0
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VCC = PVCC
VCC
thON
VCC
thOFF
UVLO VCC
0V
0V
VCC rise
Tdelay_VCC
Tdelay_VCC
LIN
GL-PGND
0V
PVCC
VCC
VCCthON
VCCthOFF
HIN
UVLO VBO
0V
0V
VBOrise
(GH-OUTB)
VBO
0V
V
BOthON
VBOthOFF
0V
VBO
MASTERGAN2
VBO UVLO protection
The PVCC pin can be connected either to the same supply voltage of the VCC pin or to a separate voltage
source. In case the same voltage source is used, it is suggested to connect VCC and PVCC pins by means of
a small decoupling resistance. The use of dedicated bypass ceramic capacitors located as close as possible to
each supply pin is highly recommended.
The MASTERGAN2 VCC supply voltage is continuously monitored by under-voltage lockout (UVLO) circuitry that
turns both the high-side and low-side GaN transistors off when the supply voltage goes below the V
threshold. The UVLO circuitry turns on the GaN, according to LIN and HIN status, approximately 20 µs (typ)
after the supply voltage goes above the V
CCthON
voltage. A V
hysteresis is provided for noise rejection
CChys
purposes.
Figure 26. VCC UVLO and Low Side
CC_thOFF
6.4
VBO UVLO protection
Dedicated undervoltage protection is available on the bootstrap section between BOOT and OUTb supply pins. In
order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold.
Approximately 5 µs (typ) after VBO voltage falls below V
switched off. When VBO voltage reaches the V
BOthON
BOthOFF
threshold, the device returns to normal operation and the
output remains off until the next input pin transition that requests the high-side to turn on.
Figure 27. VBO UVLO and High Side
threshold, the high-side GaN transistor is
DS13597 - Rev 2.0
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6.5 Thermal shutdown
THERMAL SHUTDOWN CIRCUIT
GH/GL
OD gate
(internal)
Fast shut down
the driver outputs are switched off
disable time
SD/OD
T
TSDTHYSTTSD -
VihV
0 V
TSDVOD
TJ
t1t
2
VPU
SD/OD
FROM / TO
CONTROLLER
C
OD
THERMAL
SHUTDOWN
LOGIC
R
ON_ODRPD_SD
R
OD_ext
2
1
immediately after overtemperature
The integrated gate driver has a thermal shutdown protection.
When junction temperature reaches the T
leaving the half-bridge in 3-state and signaling the state forcing
junction temperature is below T
GaN are driven again according to inputs when
The thermal smart shutdown system provides the possibility to increase the time constant of the external RC
network (that determines the disable time after the overtemperature event) up to very large values without
delaying the protection.
temperature threshold, the device turns off both GaN transistors,
TSD
SD/OD pin low. SD/OD pin is released when
TSD-THYS
and SD/OD is below V
TSD
.
SD/OD rises above Vih.
Figure 28. Thermal shutdown timing waveform
MASTERGAN2
Thermal shutdown
DS13597 - Rev 2.0
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7 Typical application diagrams
+
C
PVCC
FROM/TO CONTROLLER
H.V.
C
R
CBOOT
CVCC
C
R
COD
R
VOUT
VCC
VCC
VPU
CC
CbuS
FROM/TO CONTROLLER
FROM/TO CONTROLLER
TO CONTROLLER
Driver
Driver
Logic,
interlocking,
overtemp
Level Shifter
Level Shifter
VCC UVLO
UVLO
Vbo
PGNDPVCC
OUTbBOOT
GL
GH
VCC
HIN
LIN
SD/OD
GND
OUT
VS
SENSE
HON
HOFF
LON
LOFF
R
BLEED
RON
L
ROFF
L
ROFF
H
RON
H
Figure 29. Asymmetrical Active clamp flyback
MASTERGAN2
Typical application diagrams
DS13597 - Rev 2.0
page 20/29
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information
Table 10. QFN 9 x 9 x 1 mm package dimensions
MASTERGAN2
Package information
Symbol
A
A3 0.10
b 0.25 0.30 0.35
D 8.96 9.00 9.04
E 8.96 9.00 9.04
D1 3.30 3.40 3.50
E1 2.06 2.16 2.26
D2 1.76 1.86 1.96
E2 3.10 3.20 3.30
D3 1.70 1.80 1.90
E3 3.10 3.20 3.30
e 0.60
K 0.24
L 0.35 0.45 0.55
N 31
aaa 0.10
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
Min. Typ. Max.
0.90 0.95 1.00
Dimensions (mm)
Note: 1. Dimensioning and tolerances conform to ASME Y14.5-2009.
2. All dimensions are in millimeters.
3. N total number of terminals.
4. Dimensions do not include mold protrusion, not to exceed 0.15 mm.
5. Package outline exclusive of metal burr dimensions.
DS13597 - Rev 2.0
page 21/29
Figure 30. QFN 9 x 9 x 1 mm package dimensions
TOP VIEW
SIDE
VIEW
BOTTOM VIEW
MASTERGAN2
QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information
DS13597 - Rev 2.0
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9 Suggested footprint
TOP VIEW
Dimensions in mm
The MASTERGAN2 footprint for the PCB layout is usually defined based on several design factors such as
assembly plant technology capabilities and board component density. For easy device usage and evaluation, ST
provides the following footprint design, which is suitable for the largest variety of PCBs.
The following footprint indicates the copper area that should be free of solder mask, and shall extend beyond the
indicated areas, especially for EP2 and EP3. To aid thermal dissipation, it is recommended to add thermal vias
under these EPADs to transfer and dissipate device heat to the other PCB copper layers. A PCB layout example
is available with the MASTERGAN2 evaluation board.
Figure 31. Suggested footprint (top view drawing)
MASTERGAN2
Suggested footprint
DS13597 - Rev 2.0
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10 Ordering information
Order code Package Package Marking Packaging
MASTERGAN2 QFN 9 x 9 x 1 mm MASTERGAN2 Tray
MASTERGAN2TR QFN 9 x 9 x 1 mm MASTERGAN2 Tape and Reel
MASTERGAN2
Ordering information
Table 11. Order codes
DS13597 - Rev 2.0
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Revision history
Date Version Changes
01-Dec-2020 1 Initial release.
21-Jun-2021 2
MASTERGAN2
Table 12. Document revision history
Corrected Table 2: CGL, CGH test conditions; Added Lines in Table 5: Td_GL and Td_GH; Added
description in Section 6.1 .
DS13597 - Rev 2.0
page 25/29
MASTERGAN2
Contents
Contents
1 Block diagram .....................................................................2
2 Pin description and connection diagram ...........................................3
2.1 Pin list ........................................................................3
3 Electrical Data .....................................................................4
3.1 Absolute maximum ratings.......................................................4
3.2 Recommended operating conditions ..............................................5
3.3 Thermal data ..................................................................5
4 Electrical characteristics...........................................................6
4.1 Driver ........................................................................6
4.2 GaN power transistor ...........................................................8
5 Device characterization values.....................................................9
6 Functional description ............................................................17
6.1 Logic inputs ..................................................................17
6.2 Bootstrap structure ............................................................17
6.3 VCC supply pins and UVLO function .............................................17
6.4 VBO UVLO protection ..........................................................18
6.5 Thermal shutdown.............................................................19
7 Typical application diagrams......................................................20
8 Package information..............................................................21
8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information ......................21
9 Suggested footprint ..............................................................23
10 Ordering information .............................................................24
Revision history .......................................................................25
Contents ..............................................................................26
List of tables ..........................................................................27
List of figures..........................................................................28
DS13597 - Rev 2.0
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MASTERGAN2
List of tables
List of tables
Table 1. Pin description......................................................................3
Table 2. Absolute maximum ratings .............................................................4
Table 3. Recommended operating conditions....................................................... 5
Table 4. Thermal data.......................................................................5
Table 5. Driver electrical characteristics ..........................................................6
Table 6. GaN power transistor electrical characteristics................................................ 8
Table 7. GaN power transistor characterization values ................................................9
Table 8. Inductive load switching characteristics.....................................................9
Table 9. Inputs truth table (applicable when device is not in UVLO)....................................... 17
Table 10. QFN 9 x 9 x 1 mm package dimensions ................................................... 21
Table 11. Order codes ...................................................................... 24
Table 12. Document revision history ............................................................. 25
DS13597 - Rev 2.0
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MASTERGAN2
List of figures
List of figures
Figure 1. MASTERGAN2 block diagram .........................................................2
Figure 2. Pin connection (top view) .............................................................3
Figure 3. Switching time definition ............................................................ 10
Figure 4. Typ I
Figure 5. Typ I
Figure 6. Typ I
Figure 7. Typ I
Figure 8. Typ R
Figure 9. Typ R
Figure 10. Typ R
Figure 11. Typ R
Figure 12. Typ I
Figure 13. Typ I
Figure 14. Typ R
Figure 15. Typ I
Figure 16. Typ I
Figure 17. Typ I
Figure 18. Typ I
Figure 19. Safe Operating Area (LS) at TJ=25°C ................................................... 14
Figure 20. Safe Operating Area (HS) at TJ=25°C ................................................... 14
Figure 21. Typical Gate Charge (LS) at TJ=25°C ................................................... 15
Figure 22. Typical Gate Charge (HS) at TJ=25°C ................................................... 15
Figure 23. LS Derating curve .................................................................15
Figure 24. HS Derating curve................................................................. 15
Figure 25. Typ R
Figure 26. VCC UVLO and Low Side ........................................................... 18
Figure 27. VBO UVLO and High Side ........................................................... 18
Figure 28. Thermal shutdown timing waveform .................................................... 19
Figure 29. Asymmetrical Active clamp flyback ..................................................... 20
Figure 30. QFN 9 x 9 x 1 mm package dimensions .................................................. 22
Figure 31. Suggested footprint (top view drawing) .................................................. 23
vs. VDS at TJ=25°C .........................................................10
D_LS
vs. VDS at TJ=125°C ........................................................ 10
D_LS
vs. VDS at TJ=25°C......................................................... 11
D_HS
vs. VDS at TJ=125°C ........................................................ 11
D_HS
DS(on)_LS
DS(on)_LS
DS(on)_HS
DS(on)_HS
D_LS
D_HS
DS(on)
SD_LS
SD_LS
SD_HS
SD_HS
Dboot
vs. ID at TJ=25°C....................................................... 11
vs. ID at TJ=125°C ...................................................... 11
vs. ID at TJ=25°C ...................................................... 12
vs. ID at TJ=125°C ..................................................... 12
vs. VDS ................................................................. 12
vs. VDS ................................................................ 12
vs. TJ normalized at 25°C ...................................................13
vs. V
vs. V
vs. V
vs. V
at TJ=25°C ...................................................... 13
SD_LS
at TJ=125°C .....................................................13
SD_LS
at TJ=25°C ..................................................... 14
SD_HS
at TJ=125°C .................................................... 14
SD_HS
vs. TJ ................................................................. 16
DS13597 - Rev 2.0
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MASTERGAN2
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DS13597 - Rev 2.0
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