ST MICROELECTRONICS MASTERGAN1 Datasheet

Download

MASTERGAN1

Datasheet

High power density 600V Half bridge driver with two enhancement mode GaN

HEMT

Features

• 600 V system-in-package integrating half-bridge gate driver and high-voltage power GaN transistors:

– QFN 9 x 9 x 1 mm package

– R

– I

DS(MAX)

• Reverse current capability

• Zero reverse recovery loss

• UVLO protection on low-side and high-side

• Internal bootstrap diode

• Interlocking function

• Dedicated pin for shutdown functionality

• Accurate internal timing match

• 3.3 V to 15 V compatible inputs with hysteresis and pull-down

• Overtemperature protection

• Bill of material reduction

• Very compact and simplified layout

• Flexible, easy and fast design.

DS(ON)

= 150 mΩ

= 10 A

Product status link

MASTERGAN1

Product label

Application

• Switch-mode power supplies

• Chargers and adapters

• High-voltage PFC, DC-DC and DC-AC Converters

• UPS Systems

• Solar Power

Description

The MASTERGAN1 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN transistors in half‑bridge configuration.

The integrated power GaNs have R breakdown voltage, while the high side of the embedded gate driver can be easily

supplied by the integrated bootstrap diode.

The MASTERGAN1 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions.

The input pins extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.

The MASTERGAN1 operates in the industrial temperature range, -40°C to 125°C.

The device is available in a compact 9x9 mm QFN package.

of 150 mΩ and 650 V drain‑source

DS(ON)

DS13417 - Rev 3 - October 2020 For further information contact your local STMicroelectronics sales office.

www.st.com

1 Block diagram

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGOFF

RGON

RGOFF

MASTERGAN1

Block diagram

Figure 1. Block diagram

DS13417 - Rev 3

page 2/27

2 Pin description and connection diagram

GND

SENSE

OUT

EP1

EP2

EP3

SENSE

OUT

SENSE

OUTb

BOOT

PGND

PVCC

N.C.

VCC

GND

LIN

HIN

SD/OD

N.C.

Figure 2. Pin connection (top view)

MASTERGAN1

Pin description and connection diagram

2.1 Pin list

Table 1. Pin description

Pin Number Pin Name Type Function

15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)

12, 13, 14, EP3 OUT Power Output Half-bridge output

4, 5, 6, 7, 8, 9, 10,

11, EP2

22 BOOT Power Supply Gate driver high-side supply voltage

21 OUTb Power Supply

27 VCC Power Supply Logic supply voltage

SENSE Power Supply Half-bridge sense (low-side GaN Source)

Gate driver high-side reference voltage, used only for Bootstrap capacitor connection. Internally connected to OUT.

DS13417 - Rev 3

page 3/27

Pin Number Pin Name Type Function

1 PVCC Power Supply Gate driver low-side supply voltage

28, EP1 GND Power Supply Logic ground

3 PGND Power Supply

26 HIN Logic Input High-Side driver logic input

24 LIN Logic Input Low-Side driver logic input

25 SD/OD Logic Input-Output Driver Shutdown input and Over-Temperature

2 GL Output Low-Side GaN gate.

20 GH Output High-Side GaN gate.

23, 29, 30, 31 N.C. Not Connected Leave floating

Gate driver low-side driver reference. Internally connected to SENSE.

MASTERGAN1

Pin list

DS13417 - Rev 3

page 4/27

3 Electrical Data

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings (each voltage referred to GND unless otherwise specified)

Symbol Parameter Test Condition Value Unit

VCC Logic supply voltage -0.3 to 11 V

PVCC-PGND

VCC-PGND Logic supply vs. Low-side driver ground -0.3 to 18.3 V

PVCC Low-side driver supply vs. logic ground -0.3 to 18.3 V

PGND Low-side driver ground vs. logic ground -7.3 to 11.3 V

BOOT Bootstrap voltage -0.3 to 620 V

CGL, CGH

RGL, RGH

Rout

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT.

CGx < 0.08/(Pvcc^2*Fsw)-(330*10

4. TCB is temperature of case exposed pad.

5. Range estimated by characterization, not tested in production.

6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.

GaN Drain-to-Source Voltage

Low-side driver supply voltage

BOOT to OUTb voltage

Maximum external capacitance between GL and PGND and between GH and OUTb

Minimum external pull-down resistance between GL and PGND and GH and OUTb

Drain current (per GaN transistor)

Half-bridge outputs slew rate (10% - 90%) 100 V/ns

Logic inputs voltage range -0.3 to 21 V

Junction temperature -40 to 150 °C

Storage temperature -40 to 150 °C

-12

MASTERGAN1

Electrical Data

TJ = 25 °C

(1)

(2)

Fsw = 2 MHz

DC @ TCB = 25°C

DC @ TCB = 100°C

Peak @ TCB = 25°C

(3)

(4), (5)

(4)

(5)

(4), (5), (6)

620 V

-0.3 to 7 V

680 pF

6.8 kΩ

9.7 A

6.4 A

17 A

DS13417 - Rev 3

page 5/27

3.2 Recommended operating conditions

Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified)

Symbol Parameter Note Min Max Unit

VS High voltage bus 0 520 V

VCC Supply voltage 4.75 9.5 V

PVCC-PGND

PVCC to PGND low side supply

PVCC Low-side driver supply 3 8.5 V

VCC-PVCC VCC to PVCC pin voltage -3 3 V

PGND

Low-side driver ground

(1)

DT Suggested minimum deadtime 5 ns

IN_MIN

Minimum duration of input pulse to obtain undistorted output pulse

BOOT to OUTb pin voltage

BOOT BOOT to GND voltage

Logic inputs voltage range 0 20 V

Junction temperature -40 125 °C

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT.

3. 5 V is recommended during high-hide turn-on.

(1)

(2)

MASTERGAN1

Recommended operating conditions

4.75 6.5 V

Best performance 5 6.5 V

-2 2 V

120 ns

4.4 6.5 V

Best performance 5 6.5 V

(3)

530 V

3.3

Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

th(J-CB)

th(J-A)

1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.

Thermal resistance junction to each GaN transistor exposed pad, typical 1.9 °C/W

Thermal resistance junction-to-ambient

(1)

17.5 °C/W

DS13417 - Rev 3

page 6/27

4 Electrical characteristics

4.1 Driver

Table 5. Driver electrical characteristics : VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise

specified (Each voltage referred to GND unless otherwise specified.)

Symbol Parameter Test condition Min Typ Max Unit

Logic section supply

VCC

QVCCU

QVCC

SVCC

thON

thOFF

hys

VCC vs. GND

VCC UV turn ON threshold

VCC UV turn OFF threshold

VCC UV hysteresis

VCC undervoltage quiescent supply current

VCC quiescent supply current

VCC switching supply current

MASTERGAN1

Electrical characteristics

(1)

VCC = PVCC = 3.8 V 320 410 μA

SD/OD = LIN = 5 V;

HIN = 0 V;

BOOT = 7 V

SD/OD = 5 V;

VBO = 6.5 V;

VS = 0 V; FSW = 500 kHz

4.2 4.5 4.75 V

3.9 4.2 4.5 V

0.2 0.3 0.45 V

680 900 μA

0.8 mA

Low-side driver section supply

QPVCC

SPVCC

BLEED

RON

ROFF

PVCC vs. PGND

GL vs. PGND Low side gate bleeder PVCC = PGND 75 100 125 kΩ

High-side floating section supply

BOthON

BOthOFF

BOhys

BOOT vs. OUTb

QBOU

QBO

SBO

BOOT BOOT switching supply current

PVCC quiescent supply current SD/OD = LIN = 5 V 150 μA

PVCC switching supply current

VS = 0 V

FSW = 500 kHz

1.4 mA

Low side turn on resistor I(GL) = 1 mA (source) 50 Ω

Low side turn off resistor I(GL) = 1 mA (sink) 2 Ω

UV turn ON threshold

VBO UV turn OFF threshold

UV hysteresis

VBO undervoltage quiescent supply current

(2)

VBO quiescent supply current

(2)

VBO = 3.4 V

VBO = 6 V; LIN = GND;

(2)

SD/OD = HIN = 5 V;

3.6 4.0 4.4 V

3.4 3.7 4.0 V

0.1 0.3 0.5 V

140 200 μA

217 μA

VBO = 6 V;

SD/OD = 5 V;

2 mA

VS = 0 V; FSW = 500 kHz

DS13417 - Rev 3

DBoot

BOOT vs. SGND High voltage leakage current BOOT = OUT = 600 V 11 μA

SD/OD = LIN = 5 V;

VCC vs. BOOT

Bootstrap diode on resistance

(3)

HIN = GND = PGND

140 175 Ω

page 7/27

MASTERGAN1

GaN power transistor

Symbol Parameter Test condition Min Typ Max Unit

VCC – BOOT = 0.5 V

RON

ROFF

Logic inputs

ihys

INh

INl

PD_IN

SDh

SDl

PD_SD

TSD

ON_OD

OL_OD

LIN, HIN, SD/OD

LIN, HIN

SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA

SD/OD Logic “0” input bias current SD/OD = 0 V 1 μA

SD/OD Pull-down resistor

SD/OD

SD/OD Open drain ON resistance

SD/OD

High side turn on resistor I(GH) = 1 mA (source) 50 Ω

High side turn off resistor I(GH) = 1 mA (sink) 2 Ω

Low level logic threshold voltage

High level logic threshold voltage

TJ = 25°C

Full Temperature range

TJ = 25°C

Full Temperature range

(4)

1.1 1.31 1.45

0.8

2 2.17 2.5

2.7

Logic input threshold hysteresis 0.7 0.96 1.2 V

Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA

Logic ‘0’ input bias current LIN, HIN = GND 1 μA

Input pull-down resistor LIN, HIN = 5 V 90 150 220 kΩ

Thermal shutdown unlatch threshold

SD/OD = 5 V

OpenDrain OFF

TJ = 25°C

(5)

250 330 450 kΩ

0.5 0.75 1 V

TJ = 25°C;

8 10 18 Ω

22 40 50 mA

Open Drain low level sink current

= 400 mV

TJ = 25°C;

VOD = 400 mV

(5)

4.2

Over temperature protection

TSD

HYS

Shutdown temperature

Temperature hysteresis

(4)

175 °C

20 °C

1. VCC UVLO is referred to VCC - GND.

2. V

3. R

= V

BD(on)

- V

BOOT

OUT.

is tested in the following way:

= [(VCC - V

BOOTa

) - (VCC - V

Where: Ia is BOOT pin current when V

BOOTb

BOOT

)] / [Ia - Ib]

= V

BOOTa

; Ib is BOOT pin current when V

BOOT

= V

BOOTb

4. Range estimated by characterization, not tested in production.

5. Tested on wafer.

GaN power transistor

Table 6. GaN power transistor electrical characteristics (V

Symbol Parameter Test condition Min Typ Max Unit

GaN on/off states

< 18 µA

(BR)DS

Drain-source breakdown voltage

DSS

VGS = 0 V

= 6 V; TJ = 25°C, unless otherwise specified. )

(1)

650 V

DS13417 - Rev 3

page 8/27

MASTERGAN1

GaN power transistor

Symbol Parameter Test condition Min Typ Max Unit

DSS

GS(th)

DS(on)

Zero gate voltage drain current

Gate threshold voltage

Gate to source voltage

Static drain-source on-resistance

1. Tested on wafer.

2. Value estimated by characterization, not tested in production.

VDS = 600 V

VGS = 0 V

VDS = V

GS, ID

VDS = 0 V

(2)

ID = 3.2 A

= 2.5 mA

TJ = 25°C

TJ = 125°C

0.7 µA

(1)

1.7 V

57 µA

150 220

(2)

330

mΩ

DS13417 - Rev 3

page 9/27

+ 18 hidden pages

ST MICROELECTRONICS MASTERGAN1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Application

Description

1 Block diagram

2 Pin description and connection diagram

2.1 Pin list

3 Electrical Data

3.1 Absolute maximum ratings

3.2 Recommended operating conditions

Thermal data

4 Electrical characteristics

4.1 Driver

GaN power transistor