ST MICROELECTRONICS MASTERGAN1 Datasheet

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MASTERGAN1

Datasheet

High power density 600V Half bridge driver with two enhancement mode GaN

HEMT

Features

• 600 V system-in-package integrating half-bridge gate driver and high-voltage power GaN transistors:

– QFN 9 x 9 x 1 mm package

– R

– I

DS(MAX)

• Reverse current capability

• Zero reverse recovery loss

• UVLO protection on low-side and high-side

• Internal bootstrap diode

• Interlocking function

• Dedicated pin for shutdown functionality

• Accurate internal timing match

• 3.3 V to 15 V compatible inputs with hysteresis and pull-down

• Overtemperature protection

• Bill of material reduction

• Very compact and simplified layout

• Flexible, easy and fast design.

DS(ON)

= 150 mΩ

= 10 A

Product status link

MASTERGAN1

Product label

Application

• Switch-mode power supplies

• Chargers and adapters

• High-voltage PFC, DC-DC and DC-AC Converters

• UPS Systems

• Solar Power

Description

The MASTERGAN1 is an advanced power system-in-package integrating a gate driver and two enhancement mode GaN transistors in half‑bridge configuration.

The integrated power GaNs have R breakdown voltage, while the high side of the embedded gate driver can be easily

supplied by the integrated bootstrap diode.

The MASTERGAN1 features UVLO protection on both the lower and upper driving sections, preventing the power switches from operating in low efficiency or dangerous conditions, and the interlocking function avoids cross-conduction conditions.

The input pins extended range allows easy interfacing with microcontrollers, DSP units or Hall effect sensors.

The MASTERGAN1 operates in the industrial temperature range, -40°C to 125°C.

The device is available in a compact 9x9 mm QFN package.

of 150 mΩ and 650 V drain‑source

DS(ON)

DS13417 - Rev 3 - October 2020 For further information contact your local STMicroelectronics sales office.

www.st.com

1 Block diagram

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGOFF

RGON

RGOFF

MASTERGAN1

Block diagram

Figure 1. Block diagram

DS13417 - Rev 3

page 2/27

2 Pin description and connection diagram

GND

SENSE

OUT

EP1

EP2

EP3

SENSE

OUT

SENSE

OUTb

BOOT

PGND

PVCC

N.C.

VCC

GND

LIN

HIN

SD/OD

N.C.

Figure 2. Pin connection (top view)

MASTERGAN1

Pin description and connection diagram

2.1 Pin list

Table 1. Pin description

Pin Number Pin Name Type Function

15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain)

12, 13, 14, EP3 OUT Power Output Half-bridge output

4, 5, 6, 7, 8, 9, 10,

11, EP2

22 BOOT Power Supply Gate driver high-side supply voltage

21 OUTb Power Supply

27 VCC Power Supply Logic supply voltage

SENSE Power Supply Half-bridge sense (low-side GaN Source)

Gate driver high-side reference voltage, used only for Bootstrap capacitor connection. Internally connected to OUT.

DS13417 - Rev 3

page 3/27

Pin Number Pin Name Type Function

1 PVCC Power Supply Gate driver low-side supply voltage

28, EP1 GND Power Supply Logic ground

3 PGND Power Supply

26 HIN Logic Input High-Side driver logic input

24 LIN Logic Input Low-Side driver logic input

25 SD/OD Logic Input-Output Driver Shutdown input and Over-Temperature

2 GL Output Low-Side GaN gate.

20 GH Output High-Side GaN gate.

23, 29, 30, 31 N.C. Not Connected Leave floating

Gate driver low-side driver reference. Internally connected to SENSE.

MASTERGAN1

Pin list

DS13417 - Rev 3

page 4/27

3 Electrical Data

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings (each voltage referred to GND unless otherwise specified)

Symbol Parameter Test Condition Value Unit

VCC Logic supply voltage -0.3 to 11 V

PVCC-PGND

VCC-PGND Logic supply vs. Low-side driver ground -0.3 to 18.3 V

PVCC Low-side driver supply vs. logic ground -0.3 to 18.3 V

PGND Low-side driver ground vs. logic ground -7.3 to 11.3 V

BOOT Bootstrap voltage -0.3 to 620 V

CGL, CGH

RGL, RGH

Rout

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT.

CGx < 0.08/(Pvcc^2*Fsw)-(330*10

4. TCB is temperature of case exposed pad.

5. Range estimated by characterization, not tested in production.

6. Value specified by design factor, pulse duration limited to 50 µs and junction temperature.

GaN Drain-to-Source Voltage

Low-side driver supply voltage

BOOT to OUTb voltage

Maximum external capacitance between GL and PGND and between GH and OUTb

Minimum external pull-down resistance between GL and PGND and GH and OUTb

Drain current (per GaN transistor)

Half-bridge outputs slew rate (10% - 90%) 100 V/ns

Logic inputs voltage range -0.3 to 21 V

Junction temperature -40 to 150 °C

Storage temperature -40 to 150 °C

-12

MASTERGAN1

Electrical Data

TJ = 25 °C

(1)

(2)

Fsw = 2 MHz

DC @ TCB = 25°C

DC @ TCB = 100°C

Peak @ TCB = 25°C

(3)

(4), (5)

(4)

(5)

(4), (5), (6)

620 V

-0.3 to 7 V

680 pF

6.8 kΩ

9.7 A

6.4 A

17 A

DS13417 - Rev 3

page 5/27

3.2 Recommended operating conditions

Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified)

Symbol Parameter Note Min Max Unit

VS High voltage bus 0 520 V

VCC Supply voltage 4.75 9.5 V

PVCC-PGND

PVCC to PGND low side supply

PVCC Low-side driver supply 3 8.5 V

VCC-PVCC VCC to PVCC pin voltage -3 3 V

PGND

Low-side driver ground

(1)

DT Suggested minimum deadtime 5 ns

IN_MIN

Minimum duration of input pulse to obtain undistorted output pulse

BOOT to OUTb pin voltage

BOOT BOOT to GND voltage

Logic inputs voltage range 0 20 V

Junction temperature -40 125 °C

1. PGND internally connected to SENSE.

2. OUTb internally connected to OUT.

3. 5 V is recommended during high-hide turn-on.

(1)

(2)

MASTERGAN1

Recommended operating conditions

4.75 6.5 V

Best performance 5 6.5 V

-2 2 V

120 ns

4.4 6.5 V

Best performance 5 6.5 V

(3)

530 V

3.3

Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

th(J-CB)

th(J-A)

1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.

Thermal resistance junction to each GaN transistor exposed pad, typical 1.9 °C/W

Thermal resistance junction-to-ambient

(1)

17.5 °C/W

DS13417 - Rev 3

page 6/27

4 Electrical characteristics

4.1 Driver

Table 5. Driver electrical characteristics : VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise

specified (Each voltage referred to GND unless otherwise specified.)

Symbol Parameter Test condition Min Typ Max Unit

Logic section supply

VCC

QVCCU

QVCC

SVCC

thON

thOFF

hys

VCC vs. GND

VCC UV turn ON threshold

VCC UV turn OFF threshold

VCC UV hysteresis

VCC undervoltage quiescent supply current

VCC quiescent supply current

VCC switching supply current

MASTERGAN1

Electrical characteristics

(1)

VCC = PVCC = 3.8 V 320 410 μA

SD/OD = LIN = 5 V;

HIN = 0 V;

BOOT = 7 V

SD/OD = 5 V;

VBO = 6.5 V;

VS = 0 V; FSW = 500 kHz

4.2 4.5 4.75 V

3.9 4.2 4.5 V

0.2 0.3 0.45 V

680 900 μA

0.8 mA

Low-side driver section supply

QPVCC

SPVCC

BLEED

RON

ROFF

PVCC vs. PGND

GL vs. PGND Low side gate bleeder PVCC = PGND 75 100 125 kΩ

High-side floating section supply

BOthON

BOthOFF

BOhys

BOOT vs. OUTb

QBOU

QBO

SBO

BOOT BOOT switching supply current

PVCC quiescent supply current SD/OD = LIN = 5 V 150 μA

PVCC switching supply current

VS = 0 V

FSW = 500 kHz

1.4 mA

Low side turn on resistor I(GL) = 1 mA (source) 50 Ω

Low side turn off resistor I(GL) = 1 mA (sink) 2 Ω

UV turn ON threshold

VBO UV turn OFF threshold

UV hysteresis

VBO undervoltage quiescent supply current

(2)

VBO quiescent supply current

(2)

VBO = 3.4 V

VBO = 6 V; LIN = GND;

(2)

SD/OD = HIN = 5 V;

3.6 4.0 4.4 V

3.4 3.7 4.0 V

0.1 0.3 0.5 V

140 200 μA

217 μA

VBO = 6 V;

SD/OD = 5 V;

2 mA

VS = 0 V; FSW = 500 kHz

DS13417 - Rev 3

DBoot

BOOT vs. SGND High voltage leakage current BOOT = OUT = 600 V 11 μA

SD/OD = LIN = 5 V;

VCC vs. BOOT

Bootstrap diode on resistance

(3)

HIN = GND = PGND

140 175 Ω

page 7/27

MASTERGAN1

GaN power transistor

Symbol Parameter Test condition Min Typ Max Unit

VCC – BOOT = 0.5 V

RON

ROFF

Logic inputs

ihys

INh

INl

PD_IN

SDh

SDl

PD_SD

TSD

ON_OD

OL_OD

LIN, HIN, SD/OD

LIN, HIN

SD/OD Logic “1” input bias current SD/OD = 5 V 11 15 20 μA

SD/OD Logic “0” input bias current SD/OD = 0 V 1 μA

SD/OD Pull-down resistor

SD/OD

SD/OD Open drain ON resistance

SD/OD

High side turn on resistor I(GH) = 1 mA (source) 50 Ω

High side turn off resistor I(GH) = 1 mA (sink) 2 Ω

Low level logic threshold voltage

High level logic threshold voltage

TJ = 25°C

Full Temperature range

TJ = 25°C

Full Temperature range

(4)

1.1 1.31 1.45

0.8

2 2.17 2.5

2.7

Logic input threshold hysteresis 0.7 0.96 1.2 V

Logic ‘1’ input bias current LIN, HIN = 5 V 23 33 55 μA

Logic ‘0’ input bias current LIN, HIN = GND 1 μA

Input pull-down resistor LIN, HIN = 5 V 90 150 220 kΩ

Thermal shutdown unlatch threshold

SD/OD = 5 V

OpenDrain OFF

TJ = 25°C

(5)

250 330 450 kΩ

0.5 0.75 1 V

TJ = 25°C;

8 10 18 Ω

22 40 50 mA

Open Drain low level sink current

= 400 mV

TJ = 25°C;

VOD = 400 mV

(5)

4.2

Over temperature protection

TSD

HYS

Shutdown temperature

Temperature hysteresis

(4)

175 °C

20 °C

1. VCC UVLO is referred to VCC - GND.

2. V

3. R

= V

BD(on)

- V

BOOT

OUT.

is tested in the following way:

= [(VCC - V

BOOTa

) - (VCC - V

Where: Ia is BOOT pin current when V

BOOTb

BOOT

)] / [Ia - Ib]

= V

BOOTa

; Ib is BOOT pin current when V

BOOT

= V

BOOTb

4. Range estimated by characterization, not tested in production.

5. Tested on wafer.

GaN power transistor

Table 6. GaN power transistor electrical characteristics (V

Symbol Parameter Test condition Min Typ Max Unit

GaN on/off states

< 18 µA

(BR)DS

Drain-source breakdown voltage

DSS

VGS = 0 V

= 6 V; TJ = 25°C, unless otherwise specified. )

(1)

650 V

DS13417 - Rev 3

page 8/27

MASTERGAN1

GaN power transistor

Symbol Parameter Test condition Min Typ Max Unit

DSS

GS(th)

DS(on)

Zero gate voltage drain current

Gate threshold voltage

Gate to source voltage

Static drain-source on-resistance

1. Tested on wafer.

2. Value estimated by characterization, not tested in production.

VDS = 600 V

VGS = 0 V

VDS = V

GS, ID

VDS = 0 V

(2)

ID = 3.2 A

= 2.5 mA

TJ = 25°C

TJ = 125°C

0.7 µA

(1)

1.7 V

57 µA

150 220

(2)

330

mΩ

DS13417 - Rev 3

page 9/27

5 Device characterization values

The information in Table 7 and Table 8 represents typical values based on characterization and simulation results and are not subject to the production test.

Table 7. GaN power transistor characterization values

Symbol Parameter Test condition Min Typ Max Unit

OSS

O(ER)

O(TR)

RRM

1. C

2. C

O(ER)

O(TR)

Total gate charge

Output charge

Output capacitance stored energy 2.7 µJ

Output capacitance 20 pF

Effective output capacitance energy

(1)

Effective output capacitance time

(2)

Reverse recovery charge 0 nC

Reverse recovery current 0 A

is the fixed capacitance that would give the same stored energy as C

is the fixed capacitance that would give the same charging time as C

VGS = 6 V,

TJ = 25°C

= 0 to 400 V

VGS = 0 V,

= 400 V

= 0 V,

VDS = 0 to 400 V

MASTERGAN1

Device characterization values

2 nC

20 nC

31 pF

50 pF

while VDS is rising from 0 V to the stated

OSS

while VDS is rising from 0 V to the stated

OSS

(on)

C(on)

t(off)

C(off)

1. t

2. t

Symbol

(1)

off

(on)

C(on)

(2)

Table 8. Inductive load switching characteristics

Parameter Test condition Min Typ Max Unit

Turn-on time

Crossover time (on) 15 ns

Turn-off time 70 ns

Crossover time (off) 15 ns

Shutdown to high/low-side propagation delay

Turn-on switching losses 12.5 µJ

Turn-off switching losses 2.5 µJ

and t

include the propagation delay time of the internal driver

(off)

and t

are the switching times of GaN transistor itself under the internally given gate driving conditions

C(off)

VS = 400 V,

VGS = 6 V,

ID = 3.2 A

See Figure 3

70 ns

DS13417 - Rev 3

page 10/27

Figure 3. Switching time definition

(ON)

(OFF)

C(ON)

C(OFF)

10%I

10%V

10%I

10%V

(a) turn-on

(b) turn-off

2 3

VDS (V)

(A)

TJ=25°C

2 3

VDS (V)

(A)

TJ=125°C

MASTERGAN1

Device characterization values

Figure 4. Typ ID vs. VDS at TJ=25°C

Figure 5. Typ ID vs. VDS at TJ=125°C

page 11/27

DS13417 - Rev 3

5 10 15 20 25

0.14

0.15

0.16

0.17

0.18

0.19

0.20

0.21

0.22 TJ=25°C

ID (A)

DS(on)

(Ω)

2 4

6 8 10

0.35

0.37

0.39

0.41

0.43

0.45

0.47

0.49

0.51 TJ=125°C

ID (A)

DS(on)

(Ω)

2 3

VDS (V)

(A)

VGS=6V

TJ=25°C

TJ=50°C

TJ=75°C

TJ=125°C

TJ=100°C

Normalized R

DS(on)

(1 at 25°C)

1.0

0.5

1.5

2.0

2.5

3.0

Temperature (°C)

-50

-10

110

150

MASTERGAN1

Device characterization values

Figure 6. Typ R

Figure 8. Typ ID vs. V

vs. ID at TJ=25°C

DS(on)

Figure 7. Typ R

Figure 9. Typ R

vs. ID at TJ=125°C

DS(on)

vs. TJ, normalized at 25°C

DS(on)

DS13417 - Rev 3

page 12/27

VSD (V)

(A)

VGS=6V

TJ=25°C

VGS=0V

1 2 3 4 5 6 7 8 9 10

TJ=125°C

VSD (V)

(A)

1 2 3 4 5 6 7 8 9 10

VGS=6V

VGS=0V

100

125

CaseBottom

(°C)

150

DISS

(W)

Device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.

MASTERGAN1

Device characterization values

Figure 10. Typ ISD vs. VSD, at TJ=25°C

Figure 12. Safe Operating Area at TJ=25°C

Figure 11. Typ ISD vs. VSD, at TJ=125°C

Figure 13. Derating curve

DS13417 - Rev 3

page 13/27

0 0.5

1.5

2.5

QG (nC)

(V)

400 V

100 V

DBoot

(ohm)

100

150

200

250

300

Temperature (°C)

-50

-10

110

150

MASTERGAN1

Device characterization values

Figure 14. Typ Gate Charge at TJ=25°C

Figure 15. Typ R

Dboot

vs T

DS13417 - Rev 3

page 14/27

6 Functional description

6.1 Logic inputs

The MASTERGAN1 features a half-bridge gate driver with three logic inputs to control the internal high-side and low-side GaN transistors.

The devices are controlled through the following logic inputs:

SD/OD: Shutdown input, active low;

•

• LIN: low-side driver inputs, active high;

• HIN: high-side driver inputs, active high.

Table 9. Inputs truth table (applicable when device is not in UVLO)

Input pins GaN transistors status

SD/OD LIN HIN LS HS

H L L OFF OFF

H L H OFF ON

H H L ON OFF

1. X: Don’t care

2. Interlocking

(1)

(2)

MASTERGAN1

Functional description

(1)

(2)

OFF OFF

6.2

6.3

The logic inputs have internal pull-down resistors. The purpose of these resistors is to set a proper logic level in case, for example, there is an interruption in the logic lines or the controller outputs are in tri-state conditions.

If logic inputs are left floating, the gate driver outputs are set to low level and the correspondent GaN transistors are turned off.

The internal logic is able to transfer the control signal pulse longer than T

= 120 ns and introduces a very

IN_MIN

short propagation delay to output.

Bootstrap structure

A bootstrap circuitry is typically used to supply the high-voltage section. MASTERGAN1 integrates this structure, realized by a patented integrated high-voltage DMOS, to reduce the external components.

The Boostrap integrated circuit is connected to VCC pin and is driven synchronously with the low-side driver.

The use of an external bootstrap diode in parallel to the integrated structure is possible, in particular if the operating frequency is approximately higher than 500 kHz.

VCC supply pins and UVLO function

The VCC pin supplies current to the logic circuit, level-shifters in the low-side section and the integrated bootstrap diode.

The PVCC pin supplies low-side output buffer. During output commutations the average current used to provide gate charge to the high-side and low-side GaN transistors flows through this pin.

The PVCC pin can be connected either to the same supply voltage of the VCC pin or to a separated voltage source. In case the same voltage source is used, it is suggested to connect VCC and PVCC pins by means of a small decoupling resistance. The use of dedicated bypass ceramic capacitors located as close as possible to each supply pin is highly recommended.

DS13417 - Rev 3

page 15/27

VCC = PVCC

VCC

thON

VCC

thOFF

UVLO VCC

VCC rise

LIN

GL-PGND

PVCC

VCC

VCCthON VCCthOFF

HIN

UVLO VBO

VBOrise

(GH-OUTB)

VBO

BOthON

VBOthOFF

VBO

MASTERGAN1

VBO UVLO protection

The MASTERGAN1 VCC supply voltage is continuously monitored by an under-voltage lockout (UVLO) circuitry that turns both the high-side and low-side GaN transistors off when the supply voltage goes below the V

threshold. The UVLO circuitry turns on the GaN, according to LIN and HIN status, as soon as the supply voltage goes above the V

CCthON

voltage. A V

hysteresis is provided for noise rejection purpose.

CChys

Figure 16. VCC UVLO and Low Side

CC_thOFF

6.4 VBO UVLO protection

Dedicated undervoltage protection is available on the bootstrap section between BOOT and OUTb supply pins. In order to avoid intermittent operation, a hysteresis sets the turn-off threshold with respect to the turn-on threshold.

When VBO voltage goes below V reaches V the HIN pin's rising edge, that activates the high side transistor's turn-on.

threshold the device returns to normal operation and the output remains off until the detection of

BOthON

BOthOFF

threshold the high-side GaN transistor is switched off. When VBO voltage

Figure 17. VBO UVLO and High Side

DS13417 - Rev 3

page 16/27

6.5 Thermal shutdown

THERMAL SHUTDOWN CIRCUIT

GH/GL

OD gate

(internal)

Fast shut down

the driver outputs are switched off

disable time

SD/OD

TSDTHYSTTSD -

VihV

0 V

TSDVOD

t1t

VPU

SD/OD

FROM / TO

CONTROLLER

THERMAL

SHUTDOWN

LOGIC

ON_ODRPD_SD

OD_ext

immediately after overtemperature

The integrated gate driver has a thermal shutdown protection.

When junction temperature reaches the T leaving the half-bridge in 3-state and signaling the state forcing

junction temperature is below T

GaN are driven again according to inputs when SD/OD rises above Vih.

The thermal smart shutdown system gives the possibility to increase the time constant of the external RC network (that determines the disable time after the overtemperature event) up to very large values without delaying the protection.

temperature threshold, the device turns off both GaN transistors

TSD

SD/OD pin low. SD/OD pin is released when

TSD-THYS

and SD/OD is below V

TSD

Figure 18. Thermal shutdown timing waveform

MASTERGAN1

Thermal shutdown

DS13417 - Rev 3

page 17/27

7 Typical application diagrams

PVCC

FROM/TO CONTROLLER

H.V.

CBOOT

CVCC

COD

VCC

VPU

CbuS

FROM/TO CONTROLLER

VOUT

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGON

RGOFF

RGON

PVCC

FROM/TO CONTROLLER

H.V.

CBOOT

CVCC

COD

VOUT

VCC

VPU

CbuS

FROM/TO CONTROLLER

TO CONTROLLER

Driver

Logic,

interlocking,

overtemp

Level Shifter

VCC UVLO

UVLO

Vbo

PGNDPVCC

OUTbBOOT

VCC

HIN

LIN

SD/OD

GND

OUT

SENSE

HON

HOFF

LON

LOFF

BLEED

RGON

RGOFF

RGON

Figure 19. Typical application diagram – Resonant LLC converter

MASTERGAN1

Typical application diagrams

DS13417 - Rev 3

Figure 20.

Typical application diagram – Active clamp flyback

page 18/27

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

Table 10. QFN 9 x 9 x 1 mm package dimensions

MASTERGAN1

Package information

Symbol

A3 0.10

b 0.25 0.30 0.35

D 8.96 9.00 9.04

E 8.96 9.00 9.04

D1 3.30 3.40 3.50

E1 2.06 2.16 2.26

D2 1.76 1.86 1.96

E2 3.10 3.20 3.30

D3 1.70 1.80 1.90

E3 3.10 3.20 3.30

e 0.60

K 0.24

L 0.35 0.45 0.55

N 31

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

Min. Typ. Max.

0.90 0.95 1.00

Dimensions (mm)

Note: 1. Dimensioning and tolerances conform to ASME Y14.5-2009.

2. All dimensions are in millimeters.

3. N total number of terminals.

4. Dimensions do not include mold protrusion, not to exceed 0.15 mm.

5. Package outline exclusive of metal burr dimensions.

DS13417 - Rev 3

page 19/27

Figure 21. QFN 9 x 9 x 1 mm package dimensions

TOP VIEW

SIDE

VIEW

BOTTOM VIEW

MASTERGAN1

QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

DS13417 - Rev 3

page 20/27

9 Suggested footprint

TOP VIEW

Dimensions in mm

The MASTERGAN1 footprint for the PCB layout is usually defined based on several design factors such as assembly plant technology capabilities and board component density. For easy device usage and evaluation, ST provides the following footprint design, which is suitable for the largest variety of PCBs.

The following footprint indicates the copper area which should be free from the solder mask, while the copper area shall extend beyond the indicated areas especially for EP2 and EP3. To aid thermal dissipation, it is recommended to add thermal vias under these EPADs to transfer and dissipate device heat to the other PCB copper layers. A PCB layout example is available with the MASTERGAN1 evaluation board.

Figure 22. Suggested footprint (top view drawing)

MASTERGAN1

Suggested footprint

DS13417 - Rev 3

page 21/27

10 Ordering information

Order code Package Package Marking Packaging

MASTERGAN1 QFN 9 x 9 x 1 mm MASTERGAN1 Tray

MASTERGAN1TR QFN 9 x 9 x 1 mm MASTERGAN1 Tape and Reel

MASTERGAN1

Ordering information

Table 11. Order codes

DS13417 - Rev 3

page 22/27

Revision history

Table 12. Document revision history

Date Version Changes

15-Jul-2020 1 Initial release.

10-Aug-2020 2

21-Oct-2020 3

Changed R

Changed Figure 1, Figure 2, Figure 13, Figure 19 and Figure 20 ; added test conditions of some parameters in Table 2 and Table 5; updated text in

Section Features.

unit in Table 6

DS(on)

MASTERGAN1

DS13417 - Rev 3

page 23/27

MASTERGAN1

Contents

1 Block diagram .....................................................................2

2 Pin description and connection diagram ...........................................3

2.1 Pin list ........................................................................3

3 Electrical Data .....................................................................5

3.1 Absolute maximum ratings.......................................................5

3.2 Recommended operating conditions ..............................................6

3.3 Thermal data ..................................................................6

4 Electrical characteristics...........................................................7

4.1 Driver ........................................................................7

4.2 GaN power transistor ...........................................................8

5 Device characterization values....................................................10

6 Functional description ............................................................15

6.1 Logic inputs ..................................................................15

6.2 Bootstrap structure ............................................................15

6.3 VCC supply pins and UVLO function .............................................15

6.4 VBO UVLO protection ..........................................................16

6.5 Thermal shutdown.............................................................17

7 Typical application diagrams......................................................18

8 Package information..............................................................19

8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information ......................19

9 Suggested footprint ..............................................................21

10 Ordering information .............................................................22

Revision history .......................................................................23

Contents ..............................................................................24

List of tables ..........................................................................25

List of figures..........................................................................26

DS13417 - Rev 3

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MASTERGAN1

List of tables

Table 1. Pin description......................................................................3

Table 2. Absolute maximum ratings (each voltage referred to GND unless otherwise specified) ....................5

Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified) ............. 6

Table 4. Thermal data.......................................................................6

Table 5. Driver electrical characteristics : VCC = PVCC = 6 V; SENSE = GND; TJ = 25°C, unless otherwise specified (Each

voltage referred to GND unless otherwise specified.) ........................................... 7

Table 6. GaN power transistor electrical characteristics (V

Table 7. GaN power transistor characterization values ............................................... 10

Table 8. Inductive load switching characteristics .................................................... 10

Table 9. Inputs truth table (applicable when device is not in UVLO)....................................... 15

Table 10. QFN 9 x 9 x 1 mm package dimensions ................................................... 19

Table 11. Order codes ...................................................................... 22

Table 12. Document revision history ............................................................. 23

= 6 V; TJ = 25°C, unless otherwise specified. ) .........8

DS13417 - Rev 3

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MASTERGAN1

List of figures

Figure 1. Block diagram ....................................................................2

Figure 2. Pin connection (top view) .............................................................3

Figure 3. Switching time definition ............................................................ 11

Figure 4. Typ ID vs. VDS at TJ=25°C ........................................................... 11

Figure 5. Typ ID vs. VDS at TJ=125°C .......................................................... 11

Figure 6. Typ R

Figure 7. Typ R

Figure 8. Typ ID vs. VDS................................................................... 12

Figure 9. Typ R

Figure 10. Typ ISD vs. VSD, at TJ=25°C ..........................................................13

Figure 11. Typ ISD vs. VSD, at TJ=125°C ......................................................... 13

Figure 12. Safe Operating Area at TJ=25°C ....................................................... 13

Figure 13. Derating curve ................................................................... 13

Figure 14. Typ Gate Charge at TJ=25°C ......................................................... 14

Figure 15. Typ R

Figure 16. VCC UVLO and Low Side ........................................................... 16

Figure 17. VBO UVLO and High Side ........................................................... 16

Figure 18. Thermal shutdown timing waveform ....................................................17

Figure 19. Typical application diagram – Resonant LLC converter ....................................... 18

Figure 20. Typical application diagram – Active clamp flyback .......................................... 18

Figure 21. QFN 9 x 9 x 1 mm package dimensions.................................................. 20

Figure 22. Suggested footprint (top view drawing) .................................................. 21

vs. ID at TJ=25°C ......................................................... 12

DS(on)

vs. ID at TJ=125°C ........................................................ 12

DS(on)

vs. TJ, normalized at 25°C................................................... 12

DS(on)

vs TJ.................................................................. 14

Dboot

DS13417 - Rev 3

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MASTERGAN1

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DS13417 - Rev 3

page 27/27

ST MICROELECTRONICS MASTERGAN1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Application

Description

1 Block diagram

2 Pin description and connection diagram

2.1 Pin list

3 Electrical Data

3.1 Absolute maximum ratings

3.2 Recommended operating conditions

Thermal data

4 Electrical characteristics

4.1 Driver

GaN power transistor

5 Device characterization values

6 Functional description

6.1 Logic inputs

Bootstrap structure

VCC supply pins and UVLO function

6.4 VBO UVLO protection

6.5 Thermal shutdown

7 Typical application diagrams

8 Package information

8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information

9 Suggested footprint

10 Ordering information

Revision history

Contents

List of tables

List of figures