M93C86-x M93C76-x M93C66-x
PDIP8 (BN)
SO8 (MN)
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm
M93C56-x M93C46-x
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE™ serial access EEPROM
Datasheet - production data
Features
• Industry standard MICROWIRE™ bus
• Single supply voltage:
–2.5 V to 5.5 V for M93Cx6-W
–1.8 V to 5.5 V for M93Cx6-R
• Dual organization: by word (x16) or byte (x8)
• Programming instructions that work on: byte,
d or entire memory
wor
• Self-timed programming cycle with auto-erase:
5 ms
• READY/
• 2 MHz clock rate
• Sequential read operation
• Enhanced ESD/latch-up behavior
• More than 4 million write cycles
• More than 200-year data retention
• Packages
– SO8, TSSOP8, UFDFPN8 packages:
– PDIP8 package:
BUSY signal during programming
OPACK2®)
EC
ECOPACK1®
Table 1. Device summary
Reference
December 2015 DocID4997 Rev 17 1/35
This is information on a product in full production.
M93C46-x
M93C56-x
M93C66-x
M93C76-x
M93C86-x
Part
nu
mber
M93C46-W
M93C46-R 1.8 V to 5.5 V
M93C56-W
M93C56-R 1.8 V to 5.5 V
M93C66-W
M93C66-R 1.8 V to 5.5 V
M93C76-W
M93C76-R 1.8 V to 5.5 V
M93C86-W
M93C86-R 1.8 V to 5.5 V
Memory
size
1 Kbit
2 Kbit
4 Kbit
8 Kbit
16 Kbit
Supply
voltage
2.5 V to 5.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
www.st.com
Contents M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.3 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.4 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Contents
11.3 UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.4 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID4997 Rev 17 3/35
3
List of tables M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Memory size versus organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Memory cell da ta ret en tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC characteristics (M93Cx6-W, M93Cx6-R, device grade 6). . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. M93Cx6 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. READ, WRITE, WEN, WDS sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 26
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID4997 Rev 17 5/35
5
Description M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
!)
$
6
##
-#X
6
33
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1
3
/2'
1 Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable P
through the MICROWIRE™ bus protocol. The memory array can be configured either in
bytes (x8b) or in words (x16b).
ROgrammable Memory (EEPROM) devices accessed
The M93Cx6-W devices operate within a voltage
supply range from 2.5 V to 5.5 V and the
M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these
devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature
ange of - 40 °C / + 85 °C.
r
Table 2. Memory size versus organization
Device Number of bits Number of 8-bit bytes Number of 16-bit words
M93C86 16384 2048 1024
M93C76 8192 1024 512
M93C66 4096 512 256
M93C56 2048 256 128
M93C46 1024 128 64
Figure 1. Logic diagram
Table 3. Signal names
Signal name Function Direction
S Chip Select Input
D Serial Data input Input
Q Serial Data output Output
C Serial Clock Input
ORG Organization Select Input
V
CC
V
6/35 DocID4997 Rev 17
SS
Supply voltage Ground -
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description
6
33
1
/2'
$5#
36
##
$
!)"
-#X
Figure 2. 8-pin package connections (top view)
1. See Section 11: Package information for package dimensions, and how to identify pin-1.
2. DU = Don't Use. The DU (do not use) pin does not con
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to V
or VSS.
CC
tribute to the normal operation of the device. It is
DocID4997 Rev 17 7/35
34
Connecting to the serial bus M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
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-XXX
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3
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22 2
6
##
6
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6
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6
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6
33
6
33
6
33
6
33
2
2 Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only on
line at a time, the other devices are high impedan ce.
e device drives the Serial Data output (Q)
The pull-down resistor R (represented in Figure 3) ensures that no device is s
elected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
imp
edance at the same time (for example, if the bus master is reset du ring the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the t
requirement is met. The typical value of R is 100 kΩ.
SLCH
Figure 3. Bus master and memory devices on the serial bus
8/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Operating features
3 Operating features
3.1 Supply voltage (VCC)
3.1.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
DC supply voltage, it is recommended to decouple the V
(usually of the order of 10 nF to 100 nF) close to the V
This voltage must remain stable and valid until the end of the transmission of the instr uction
and, for a Write instruction, until the completion of the internal write cycle (t
3.1.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to V
recommended to connect the S line to V
3.1.3 Power-up and device reset
(min), VCC(max)] range must be applied. In order to secure a sta ble
CC
via a suitable pull-down resistor.
SS
line with a suitable capacitor
CC
CC/VSS
package pins.
, it is therefore
SS
).
W
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V
instruction until V
lower than the minimum V
Section 10: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state:
• Standby Power mode
• deselected (assuming that there is a pull-down resistor on the S line)
3.1.4 Power-down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in th e S ta ndby Power mode (that is,
there should be no internal Write cycle in progress).
), the device does not respond to any
has reached the power on reset threshold voltage (this threshold is
CC
operating voltage defined in Operating conditions, in
CC
CC
DocID4997 Rev 17 9/35
34
Memory organization M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
06Y9
9FF
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4 Memory organization
The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization
Select (ORG) is left unconnected (or connected to V
when Organization Select (ORG) is connected to Ground (V
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set
either to V
between V
or VCC to reach the device minimum power consumption (as any voltage
SS
and VCC applied to ORG input may increase the device Standby current).
SS
Figure 4. M93Cx6 ORG input connection
) the x16 organization is selected;
CC
) the x8 organization is
SS
10/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
5 Instructions
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in
Table 4 to Table 6. Each instruction
READ, WRITE, WEN, WDS sequences:
• Each instruction is preceded by a ri sing edge on Chip Select
(C) being held low.
• A start bit, which is the first ‘1’ read on Seria
Serial Clock (C).
• Two op-code bits, read on Serial Data Input (D) du
(C). (Some instructions also use the first two bits of the address to define the op-code).
• The address bits of the byte or word that
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 4). For the M93C56 and M93C6 6, the ad d re ss is ma de up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and
M93C86, the address is made up of 10 bit s for the x16 o rganization or 11 bits for the x8
ganization (see Table 6).
or
consists of the following parts, as shown in Figure 5:
Input (S) with Serial Clock
l Data Input (D) during the rising edge of
ring the rising edge of Serial Clock
is to be accessed. For the M93C46, the
The M93Cx6 devices are fabricated in CMOS te
slow as 0 Hz (static input signals) or as fast as
chnology and are therefore able to run as
the maximum ratings specified in “AC
characteristics” tables, in Section 10: DC and AC parameters.
Instruction Description
READ
WRITE
WEN Write Enable 1 00 11X XXXX - 10 11 XXXX - 9
WDS Write Disable 1 00
ERASE
ERAL Erase All Memory 1 00
WRAL
1. X = Don't Care bit.
Read Data from
Memory
Write Data to
Memory
Erase Byte or
rd
Wo
Write All Memory
with same Data
T a ble 4. Instruction set for the M93C46
x8 origination (ORG = 0) x16 origination (ORG = 1)
Start
Op-
t
code
bi
1 10 A6-A0 Q7-Q0 - A5-A0 Q15-Q0 -
1 01 A6-A0 D7-D0 18 A5-A0 D15-D0 25
1 11 A6-A0 - 10 A5-A0 - 9
1 00
Address
(1)
00X
XXX
X
10X
XXX
X
01X
X
XXX
Data
D7-D0 18 01 XXXX D15-D0 25
Required
clock
cycles
- 10 00 XXXX - 9
- 10 10 XXXX - 9
Address
(1)
Data
Required
cycles
clock
DocID4997 Rev 17 1 1/35
34
Instructions M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Table 5. Instruction set for the M93C56 and M93C66
x8 origination (ORG = 0) x16 origination (ORG = 1)
Instruction Description
Start
READ Read Data from Memory 1 10 A8-A0
WRITE Write Data to Memory 1 01 A8-A0
WEN Write Enable 1 00
WDS Write Disable 1 00
bi
Op-
code
Address
(1) (2)
t
1 1XXX
XXXX
0 0XXX
XXXX
Required
Data
Q7-
Q0
D7-
D0
- 12
- 12
clock
Address
(1) (3)
Data
cycles
- A7-A0
Q15-
Q0
20 A7-A0 D15-D0 27
11XX
XXXX
00XX
XXXX
- 11
- 11
Required
clock
cycles
ERASE Erase Byte or Word 1 11 A8-A0 - 12 A7-A0 - 11
ERAL Erase All Memory 1 00
WRAL
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Write All Memory with
e Data
sam
1 00
1 0XXX
XXXX
0 1XXX
XXXX
- 12
D7-
D0
20
10XX
XXXX
01XX
XXXX
- 11
D15-D0 27
-
Table 6. Instruction set for the M93C76 and M93C86
x8 Origination (ORG = 0) x16 Origination (ORG = 1)
Instruction Description
READ
WRITE
Read Data from
Memory
Write Data to
Memory
Start
WEN Write Enable 1 00
WDS Write Disable 1 00
Op-
t
code
bi
Address
(1)(2)
Data
Required
clock
cycles
Address
(1) (3)
Data
Required
clock
cycles
1 10 A10-A0 Q7-Q0 - A9-A0 Q15-Q0 -
1 01 A10-A0 D7-D0 22 A9-A0 D15-D0 29
1 1X XXXX
XXXX
00X XXXX
XXXX
- 14
- 14
11 XXXX
XXXX
00 XXXX
XXXX
- 13
- 13
ERASE Erase Byte or Word 1 11 A10-A0 - 14 A9-A0 - 13
ERAL Erase All Memory 1 00
WRAL
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
Write All Memory
with same Data
1 00
10X XXXX
XXXX
01X XXXX
XXXX
- 14
D7-D0 22
10 XXXX
XXXX
01 XXXX
XXXX
- 13
D15-D0 29
12/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
5.1 Read Data from Memory
The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the
internal address register and clocks out the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)
and a continuous stream of data can be read ( the address counter automatically rolls over to
00h when the highest address is reached).
5.2 Erase and Write data
5.2.1 Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After a
Write Enable (WEN) instruction has been executed, erasing and writing remains enabled
until a Write Disable (WDS) instruction is executed, or until V
reset threshold voltage. To protect the memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read
Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write
Disable (WDS) instructions.
falls below the power-on
CC
5.2.2 Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Sele ct Input ( S) must be t aken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is br ought low before or af ter
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/
Once the Write cycle has been started, it is internally self-timed (the ex ternal clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.
BUSY line, as described later in this document.
DocID4997 Rev 17 13/35
34
Instructions M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Figure 5. READ, WRITE, WEN, WDS sequences
2EAD
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8N8$
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14/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
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5.2.3 Write All
As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/
Figure 6. WRAL sequence
BUSY line, as described next.
1. For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
DocID4997 Rev 17 15/35
34
Instructions M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
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5.2.4 Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/
status.
Figure 7. ERASE, ERAL sequences
BUSY line, as described in Section 6: READY/BUSY
1. For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
5.2.5 Erase All
The Erase All Memory (ERAL) instruction erases the whol e memory (all memory bit s are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/
READY/BUSY status.
16/35 DocID4997 Rev 17
BUSY line, as described in Section 6:
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x READY/BUSY status
6 READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
, before this status information
SLSH
7 Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
DocID4997 Rev 17 17/35
34
Clock pulse counter M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
!)
3
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8 Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the master (the microcontroller). This can lead to a
misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to
the writing of erroneous data at an erroneous address.
To avoid this pr oblem, the M93Cx6 has an on-chip co unter that count s the clock pulses from
art bit until the falling edge of the Chip Select Input (S). If the number of clock pulses
the st
received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is
aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each
instruction, and for each member of the
M93Cx6 family, are summarized in Table 4: Instruction set for the M93C46 to Table 6:
Instruction set for the M93C76 and M93C86. For example, a Write Dat a to Memory (WRITE)
instruction on the M93C56 (or M93C66) expects 2
0 clock cycles (for the x8 organization)
from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 8. Write sequence with one clock glitch
18/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Maximum ratings
9 Maximum ratings
Stressing the device outside the ratings listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
T
T
LEAD
Storage temperature –65 150 °C
STG
Lead temperature during soldering
Table 7. Absolute maximum ratings
PDIP - 260
other packages See note
(2)
(1)
°C
V
V
V
V
1. TLEAD max must not be applied for more than 10 s.
2. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS directive 2011/65/EU of July 2011).
3. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012), C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V
OUT
Input range –0.50 VCC+1 V
IN
Supply voltage –0.50 6.5 V
CC
Electrostatic discharge voltage (human body model)
ESD
(3)
- 4000 V
DocID4997 Rev 17 19/35
34
DC and AC parameters M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Symbol Parameter Min. Max. Unit
Table 8. Operating conditions (M93Cx6-W)
V
T
Supply voltage 2.5 5.5 V
CC
Ambient operating temperature –40 85 °C
A
Table 9. Operating conditions (M93Cx6-R)
Symbol Parameter Min. Max. Unit
V
T
Supply voltage 1.8 5.5 V
CC
Ambient operating temperature –40 85 °C
A
Table 10. Cycling performance
(1)
Symbol Parameter Test conditions Min. Max. Unit
TA ≤ 25 °C,
VCC(min) < VCC < VCC(max)
Ncycle Write cycle endurance
TA = 85 °C,
(min) < VCC < VCC(max)
V
CC
1. Cycling performance for products identified by process letter K.
Table 11. Memory cell data retention
- 4,000,000
Write cycle
- 1,200,000
(1)
Parameter Test conditions Min. Unit
Data retention TA = 55 °C 200 Year
1. For products identified by process letter K. The data retention behavior is checked in production, while the
200-year limit is defined from characterization and qualification results.
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
C
Load capacitance 100 pF
L
- Input rise and fall times - 50 ns
- Input voltage levels 0.2 VCC to 0.8 V
- Input timing reference voltages 0.3 V
- Output timing reference voltages 0.3 V
to 0.7 V
CC
to 0.7 V
CC
20/35 DocID4997 Rev 17
CC
CC
CC
V
V
V
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters
-36
9
&&
9
&&
9
&&
9
&&
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
-#88
Figure 9. AC testing input output waveforms
Symbol Parameter Test condition
C
OUT
C
IN
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.
Output capacitance V
Input capacitance VIN = 0V - 6 pF
Table 14. DC characteristics (M93Cx6-W, device grade 6)
Table 13. Input and output capacitance
(1)
= 0V - 8 pF
OUT
Te st condition (in addition to
Symbol Parameter
th
e conditions defined in
Table 8 and Table 12)
I
Input leakage current 0V ≤ VIN ≤ V
I
LI
Output leakage current 0V ≤ V
LO
≤ VCC, Q in Hi-Z - ±2.5 µA
OUT
V
= 5 V, S = VIH, f = 2 MHz,
CC
CC
Q = open
I
Operating supply current
CC
= 2.5 V, S = VIH, f = 2 MHz,
V
CC
Q = open
V
= 2.5 V, S = VSS, C = VSS,
CC
ORG = VSS or VCC,
pin7 = VCC, VSS or Hi-Z
I
CC1
V
V
V
V
1. 5 µA for previous devices identified with the process letter G.
2. Tested only for current devices identified with the process letter K.
Standby supply current
V
= 5.5 V, S = VSS, C = VSS,
CC
ORG = V
pin7 = VCC, V
Input low voltage (D, C, S) - –0.45 0.2 V
IL
Input high voltage (D, C, S) - 0.7 VCCVCC + 1 V
IH
V
= 5 V, IOL = 2.1 mA - 0.4 V
Output low voltage (Q)
OL
Output high voltage (Q)
OH
CC
V
= 2.5 V, IOL = 100 µA - 0.2 V
CC
V
= 5 V, IOH = – 400 µA 0.8 V
CC
= 2.5 V, IOH = – 100 µA VCC–0.2 - V
V
CC
or VCC,
SS
SS
or Hi-Z
Min Max Unit
Min. Max. Unit
- ±2.5 µA
- 2 mA
- 1 mA
- 2
- 3
CC
(1)
(2)
CC
- V
µA
µA
V
DocID4997 Rev 17 21/35
34
DC and AC parameters M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Table 15. DC characteristics (M93Cx6-R)
Symbol Parameter Test condition Min. Max. Unit
I
Input leakage current 0V ≤ VIN ≤ V
LI
Output leakage current 0V ≤ V
I
LO
I
CC
I
CC1
Operating supply current
Standby supply current
V
V
CC
V
OUT
= 5 V, S = VIH, f = 2 MHz,
CC
= 1.8 V, S = VIH, f = 1 MHz,
= 1.8 V, S = VSS, C = VSS,
CC
ORG = V
pin7 = VCC, V
V
Input low voltage (D, C, S) - –0.45 0.2 V
IL
Input high voltage (D, C, S) - 0.8 V
V
IH
V
V
1. 2 µA for previous devices identified with process letter G.
Output low voltage (Q) VCC = 1.8 V, IOL = 100 µA - 0.2 V
OL
Output high voltage (Q) VCC = 1.8 V, IOH = –100 µA VCC–0.2 - V
OH
CC
≤ VCC, Q in Hi-Z - ±2.5 µA
Q = open
Q = open
or VCC,
SS
or Hi-Z
SS
- ±2.5 µA
- 2 mA
- 1 mA
- 1
CCVCC
(1)
CC
+ 1 V
µA
V
Table 16. AC characteristics (M93Cx6-W, M93Cx6-R
(1)
, device grade 6)
Test conditions specified in Table 8 and Table 12
Symbol Alt. Parameter Min. Max. Unit
able.
CLCH
f
SK
t
CSS
t
CS
t
SKH
t
SKL
t
DIS
t
DIH
t
SKS
t
CSH
t
SV
t
DF
t
PD0
t
PD1
t
WP
≥ 1 / fC.
f
C
t
SLCH
t
SHCH
(2)
t
SLSH
(3)
t
CHCL
(3)
t
CLCH
t
DVCH
t
CHDX
t
CLSH
t
CLSL
t
SHQV
t
SLQZ
t
CHQL
t
CHQV
t
W
1. All M93Cx6-R devices operate with a clock frequency of 1MHz, as defined in Table 17. Only the new
M93Cx6-R devices (identified with the process letter K) can operate with the 2 MHz timing values defined
in this t
2. Chip Select Input (S) must be brought low for a minimum of t
3. t
CHCL
+ t
Clock frequency D.C. 2 MHz
Chip Select low to Clock high 50 - ns
Chip Select setup time 50 - ns
Chip Select low to Chip Select high 200 - ns
Clock high time 200 - ns
Clock low time 200 - ns
Data in setup time 50 - ns
Data in hold time 50 - ns
Clock setup time (relative to S) 50 - ns
Chip Select hold time 0 - ns
Chip Select to READY/BUSY status - 200 ns
Chip Select low to output Hi-Z - 100 ns
Delay to output low - 200 ns
Delay to output valid - 200 ns
Erase or Write cycle time - 5 ms
between consecutive instruction cycles.
SLSH
22/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters
Table 17. AC characteristics (M93Cx6-R)
(1)
Test conditions specified in Table 9 and Table 12
Symbol Alt. Parameter Min. Max. Unit
f
C
t
SLCH
t
SHCH
t
SLSH
t
CHCL
t
CLCH
t
DVCH
t
CHDX
t
CLSH
t
CLSL
t
SHQV
t
SLQZ
t
CHQL
t
CHQV
t
W
1. The new M93Cx6-R devices identified with the process letter K can operate with a clock frequency of
2 MHz and an Erase (or Write) cycle of 5 ms, as shown in Table 16.
2. Chip Select Input (S) must be brought low for a minimum of t
3. t
CHCL
(2)
(3)
(3)
+ t
f
Clock frequency D.C. 1 MHz
SK
Chip Select low to Clock high 250 - ns
CLCH
t
CSS
t
t
SKH
t
SKL
t
t
t
SKS
t
CSH
t
t
t
PD0
t
PD1
t
Chip Select setup time 50 - ns
Chip Select low to Chip Select high 250 - ns
CS
Clock high time 250 - ns
Clock low time 250 - ns
Data in setup time 100 - ns
DIS
Data in hold time 100 - ns
DIH
Clock setup time (relative to S) 100 - ns
Chip Select hold time 0 - ns
Chip Select to READY/BUSY status - 400 ns
SV
Chip Select low to output Hi-Z - 200 ns
DF
Delay to output low - 400 ns
Delay to output valid - 400 ns
Erase or Write cycle time - 10 ms
WP
between consecutive instruction cycles.
SLSH
≥ 1 / fC.
DocID4997 Rev 17 23/35
34
DC and AC parameters M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
AI
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Figure 10. Synchronous timing (Start and op-code input)
Figure 11. Synchronous timing (Read)
Figure 12. Synchronous timing (Write)
24/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Package information
0$)0"
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11 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
11.1 PDIP8 package information
Figure 13. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline
1. Drawing is not to scale.
Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
Symbol
Typ. Min. Max. Typ. Min. Max.
A - - 5.33 - - 0.2098
A1 - 0.38 - - 0.015 A2 3.3 2.92 4.95 0.1299 0.115 0.1949
b 0.46 0.36 0.56 0.0181 0.0142 0.022
b2 1.52 1.14 1.78 0.0598 0.0449 0.0701
c 0.25 0.2 0.36 0.0098 0.0079 0.0142
D 9.27 9.02 10.16 0.365 0.3551 0.4
E 7.87 7.62 8.26 0.3098 0.3 0.3252
E1 6.35 6.1 7.11 0.25 0.2402 0.2799
package mechanical data
millimeters inches
(1)
DocID4997 Rev 17 25/35
34
Package information M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
62$B9
(
FFF
E
'
F
(
K[Û
$
N
PP
/
$
*$8*(3/$1(
H
$
/
Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data (continued)
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
e 2.54 - - 0.1 - eA 7.62 - - 0.3 - eB - - 10.92 - - 0.4299
L 3.3 2.92 3.81 0.1299 0.115 0.15
1. Values in inches are converted from mm and rounded to 4 decimal digits.
(1)
11.2 SO8N package information
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data
millimeters inches
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091
D 4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1 3.800 3.900 4.000 0.1496 0.1535 0.1575
e - 1.270 - - 0.0500 h 0.250 - 0.500 0.0098 - 0.0197
26/35 DocID4997 Rev 17
(1)
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Package information
2B621B)3B9
[
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data (continued)
millimeters inches
Symbol
Min. T yp. Max. Min. Typ. Max.
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
(1)
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint
1. Dimensions are expressed in millimeters.
DocID4997 Rev 17 27/35
34
Package information M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
=:EB0(B9
7RSYLHZ
3LQ
,'PDUNLQJ
6LGHYLHZ
6HDWLQJSODQH
HHH
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11.3 UFDFN8 package information
Figure 16. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package outline
1. Max. package warpage is 0.05 mm.
2. Exposed copper is not systematic and can appear partially or
3. Drawing is not to scale.
4. The central pad (the area E2 by D2 in the above illustration) must be either connected to V
(not connected) in the end application.
28/35 DocID4997 Rev 17
totally according to the cross section.
or left floating
ss
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Package information
T able 20. UFDFN8 - 8-le ad, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat
package mechanical data
millimeters inches
Symbol
Min Typ Max Min Typ Max
A 0.450 0.550 0.600 0.0177 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
(2)
b
0.200 0.250 0.300 0.0079 0.0098 0.0118
D 1.900 2.000 2.100 0.0748 0.0787 0.0827
D2 1.200 - 1.600 0.0472 - 0.0630
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E2 1.200 - 1.600 0.0472 - 0.0630
e - 0.500 - 0.0197
K 0.300 - - 0.0118 - L 0.300 - 0.500 0.0118 - 0.0197
L1 - - 0.150 - - 0.0059
L3 0.300 - - 0.0118 - aaa - - 0.150 - - 0.0059
bbb - - 0.100 - - 0.0039
(1)
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
(3)
eee
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
- - 0.080 - - 0.0031
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Package information M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
76623$0B9
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11.4 TSSOP8 package information
Figure 17.TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline
1. Drawing is not to scale.
Table 21. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package mechanical data
(1)
millimeters inches
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
CP - - 0.100 - - 0.0039
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
α 0° - 8° 0° - 8°
1. Values in inches are converted from mm and rounded to four decimal digits.
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M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Part numbering
12 Part numbering
Table 22. Ordering information scheme
Example: M93C86 – W MN 6 T P
Device type
M93 = MICROWIRE™ serial EEPROM
Device function
86 = 16 Kbit (2048 x 8)
76 = 8 Kbit (1024 x 8)
66 = 4 Kbit (512 x 8)
56 = 2 Kbit (256 x 8)
46 = 1 Kbit (128 x 8)
Operating voltage
W = V
R = V
= 2.5 to 5.5 V
CC
= 1.8 to 5.5 V
CC
Package
BN = PDIP8
MN = SO8 (150 mils width)
MC = UFDFPN8 2 x 3 mm (MLP8)
DW = TSSOP8 (169 mils width)
(1)
(2)
(2)
(2)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Packing
blank = tube packing
T = tape and reel packing
Plating technology
P or G = ECOPACK2
1. ECOPACK1®: RoHS-compliant.
2. ECOPACK2®: RoHS compliant and free of brominated, chlorinated and antimony-oxide flame
retardants.
®
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Part numbering M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineer ing Sample notifica tion letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be co ntacted
prior to any decision to use these Engineering samples to run qualification activity.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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13 Revision history
Table 23. Document revision history
Date Revision Changes
Modified footnote in Table 14 and Table 15 on page 23
Updated Figure 14: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual
01-Apr-2010 9
flat package no lead 2 x 3 mm, outline and Table 22: UFDFPN8
(MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm,
data
29-Apr-2010 10
Updated Figure 31: Available M93C66-x products (package, voltage
range, temperature grade) UFDFPN option.
Updated Table 7: Absolute maximum ratings, MLP8 package data in
Section 12: Package mechanical data and process data in Section 9:
Clock pulse counter.
Deleted Table 29: Available M93C46-x products (package, voltage
12-Apr-2011 11
range, temperature grade), Table
(package, voltage range, temperature grade), Table 31: Available
M93C66-x products (package, voltage range, temperature grade),
32: Available M93C76-x products (package, voltage range,
Table
temperature grade) and Table 33: Available M93C86-x products
(package, voltage range, temperature grade).
Updated Table 1: Device summary and Table 8: Operating conditions
05-Oct-2011 12
(M93Cx6).
Modified footnote 2 in Table 7.
Document reformatted.
Updated:
– Part number names
– Table 1: Device summary and package figure on cover page
– Section 1: Description
– Introductory paragraph in Section 9: Maximum ratings
– Note
(2)
under Table 7: Absolute maximum ratings
– Table 8: Operating conditions (M93Cx6) and Table 8: Operating
conditions (M93Cx6-W)
– Introductory paragraph in Section 11: Package information
23-Apr-2013 13
– Figure 15: UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat
Package No lead 2 x 3 mm, outline and Table 20: UFDFPN8 8-lead
Ultra thin Fine pitch Dual Flat Package No lead
– Table 22: Ordering information scheme
Renamed:
– Figure 2: 8-pin package connections (top view)
–Table 16: AC characteristics (M93Cx6, device grade 6)
Deleted:
– Section: Common I/O operation
– Table : DC characteristics (M93Cx6, device grade 3), Table: DC
characteristics (M93Cx6-W, device grade 3), and Table: AC
characteristics (M93Cx6-W, device grade 3)
30: Available M93C56-x products
x 3 mm, data
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Revision history M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Table 23. Document revision history (continued)
Date Revision Changes
Updated:
– Table 1: Device summary: added “M93C46-R” and “M93C86-R”,
deleted M93Cxx part numbers.
– Features: Single supply voltage, write cycles and data retention
– Section 1: Description
– Note
– Section 10: DC and AC parameters: updated the introduction and
26-Oct-2013 14
15-Nov-2013 15 Removed Table 14 Cycling performance by byte
– Figure 9: AC testing input output waveforms
– Table 14: DC characteristics (M93Cx6-W, device grade 6),
– Table 22: Ordering information scheme.
Added:
– Figure 4: M93Cx6 ORG input connection
– Table 10: Cycling performance and Table 11: Memory cell data
(2)
under Table 7: Absolute maximum ratings.
deleted tables related to M93Cxx part numbers.
Table 15: DC characteristics (M93Cx6-R), Table 16: AC
characteristics (M93Cx6-W, M93Cx6-R, device grade 6) and
Table 17: AC characteristics (M93Cx6-R).
retention.
06-Nov-2015 16
21-Dec-2015 17
Updated:
– Features
– Table 1: Device summary;
– Notes of Table 7: Absolute maximum ratings;
– Table 22: Ordering information scheme
– Table 11: Package information
Updated:
– Figure 16: UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin
profile fine pitch dual flat package outline
– Table 20: UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin
profile fine pitch dual flat package mechanical data
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M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
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