ST MICROELECTRONICS M48Z35Y-70PC Datasheet

M48Z35

M48Z35Y

256 Kbit (32Kb x 8) ZEROP OWER® SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and
BATTERY

■ READ CYCLE TIME EQUALS WRITE CYCLE

TIME

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48Z35: 4.50V ≤ V
– M48Z35Y: 4.20V ≤ V

■ SELF-CONTAINED BATTERY in th e CAPHAT

PFD

PFD

≤ 4.75V

≤ 4.50V

DIP PACKAGE

■ PACKAGING INCLUDES a 28-LEAD SOIC and

SNAPHAT

■ SOIC PACKAGE PROVIDES D IREC T

®

TOP (to be Ordered Separately)

CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32K x8 SRAMs

DESCRIPTION

The M48Z35/35Y ZEROPOWER

®

RAM is a 32
Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithi c chip is avail­able in two special packages to provide a highly in­tegrated battery backed-up memory solution.

Table 1. Signal Names

A0-A14 Address Inputs

SNAPHAT (SH)

Battery

28

28

1

SOH28 (MH)

Figure 1. Logic Diagram

V

CC

15

A0-A14

W

E

G

M48Z35

M48Z35Y

1

PCDIP28 (PC)

Battery CAPHAT

8

DQ0-DQ7

DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
V

CC

SS

Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground

V

SS

AI01616D

1/18August 1999

M48Z35, M48Z35Y

Figure 2A. DIP Pin Connections

A14 V

1

A12

2
3

A7

4

A6

5

A5

6

A4

7

A3
A2
A1
A0

DQ0

8
9
10
11

M48Z35

M48Z35Y

12
13

DQ2

14

SS

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or a ny other conditions above those indicat ed in the operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoo ts bel ow –0.3V are not al l owed on any pin whi l e i n the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHA T sockets.

Ambient Operating Temperature Grade 1

Storage Temperature (VCC Off) SNAPHAT

Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V

Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01617D

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

(1)

Grade 6

SOIC

Figure 2B. SOIC Pin Connections

A14 V
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

1
2
3
4
5
6
7

M48Z35Y

8
9
10
11
12

DQ2

SS

13
14

0 to 70

–40 to 85
–40 to 85

–55 to 125

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI02303C

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

°C

°C

2/18

M48Z35, M48Z35Y

≤

V

or

PFD

V

CC

SO

(1)

(min)

(2)

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

Table 3. Operating Modes

Mode

Deselect
Write
Read
Read

Deselect
Deselect

Note: 1. X = VIH or VIL; VSO = Battery Back-up Swit ch ov er Volta ge.

2. See T able 7 for deta ils .

4.75V to 5.5V

4.5V to 5.5V

V

to V

SO

Figure 3. Block Diagram

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

X X High Z Standby
X

V

IL

V

IH

POWER

V

PFD

V

IL

V

IH

V

IH

32K x 8

SRAM ARRAY

D

IN

D

OUT

High Z Active

Active
Active

A0-A14

DQ0-DQ7

E

W

V

CC

The M48Z35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the n umber of writes that
can be performed. The 28 pin 600mil DIP

CAPHAT™ houses the M48Z35/35Y silicon with a
long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-

G

V

SS

AI01619B

nection to a separate SNAPHAT housing cont ain­ing the battery. The unique design allows the
SNAPHAT battery p acka ge t o b e m ount ed o n t op
of the SOIC package after the c ompletion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPH AT housing
is keyed to prevent reverse insertion.

3/18

M48Z35, M48Z35Y

Table 4. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer
driven.

≤

5ns

The SOIC and battery packages are shipped sep­arately in plastic anti-static tubes or in Tape & Reel
form.

For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".

The M48Z35/35Y also has its own Power-fail De­tect circuit. The control circuitry constantly moni­tors the single 5V supply for an out of tolerance
condition. When V

is out of tolerance, the circuit

CC

write protects the S RAM, p roviding a high degree
of data security in the midst of unpredictable s ys­tem operation brought on by low V

. As VCC falls

CC

below approximately 3V, the control circuitry con­nects the battery which maintains data until valid
power returns.

READ MODE

The M48Z35/35Y is in the Read Mode whenever

(Write Enable) is high, E (Chip Enable) is low.

W
The device architecture allows ripple-through ac­cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t

) after the last

AVQV

address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G

access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
(t

GLQV

) or Output Enable Access time

ELQV

).

The state of the eight three-s tate Da ta I/O si gnals
is controlled by E

and G. If the outputs are activat-

Figure 4. AC Testing Load Circuit

DEVICE
UNDER

TEST

CL includes JIG capacitance

ed before t

, the data lines will be driven to an

AVQV

indeterminate state until t
puts are changed while E

645Ω

CL = 100pF or
5pF

. If the Ad dres s In-

AVQV

and G remain active,

1.75V

AI03211

output dat a will rem ain v alid for Outp ut Dat a Hold
time (t

) but will go indeterminate until the next

AXQX

Addr e ss Access.

WRITE MODE

The M48Z35/35Y is in the Write Mode whenever

and E are low. The start of a write is referenced

W
from the latter occurring f alling edge of W

or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E
of t

EHAX

or W must return high for a minimum

from Chip Enable or t

from Write En-

WHAX

able prior to the initiation of another read or write
cycle. Data -in must be vali d t
of write and remain valid for t

prior to the end

DVWH

afterward. G

WHDX

should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E
will disab le the ou t pu t s t

and G, a low on W

after W falls.

WLQZ

4/18

M48Z35, M48Z35Y

Table 5. Capacitance

(T

= 25 °C)

A

(1, 2)

Symbol Parameter Test Condition Min Max Unit

C

C

IO

Note: 1. Effective capacitan ce measured wi th power su pply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselect ed.

Input Capacitance

IN

(3)

Input / Output Capacitance

V

V

OUT

IN

= 0V

= 0V

10 pF
10 pF

Table 6. DC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

I

LO

I

CC

I

CC1

I

CC2

V

IL

V

IH

V

OL

V

OH

Note: 1. Outputs deselected .

2. Negativ e s p i k e s of –1V allo wed for up t o 10 ns once pe r cycle .

Input Leakage Current

(1)

Output Leakage Current
Supply Current Outputs open 50 mA
Supply Current (Standby) TTL

Supply Current (Standby) CMOS

(2)

Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2
Output Low Voltage

Output High Voltage

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC – 0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±1 µA
±5 µA

3mA
3mA

V

+ 0.3

CC

0.4 V

2.4 V

V

Table 7. Power Down/Up Trip Points DC Characteristics

(1)

(TA = 0 to 70 °C or –40 to 85 °C)

Symbol Parameter Min Typ Max Unit

V

PFD

V

PFD

V

SO

t

DR

Note: 1. All voltages referenced to VSS.

2. At 25 ° C.

Power-fail Deselect Voltage (M48Z35) 4.5 4.6 4.75 V
Power-fail Deselect Voltage (M48Z35Y) 4.2 4.35 4.5 V
Battery Back-up Switchover Voltage (M48Z35/35Y) 3.0 V

(2)

Expected Data Retention Time 10 YEARS

5/18

M48Z35, M48Z35Y

Table 8. Power Down/Up AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C)

A

Symbol Parameter Min Max Unit

t

PD

t

F

t

FB

t

R

t

RB

t

REC

Note: 1. V

2. V

3. t

E or W at VIH before Power Down

(1)

V

(max) to V

PFD

(2)

V

(3)

PFD

es V

PFD

PFD

(min) = 20ms for industri al tempera ture grade (6) device.

REC

(min) to VSS VCC Fall Time

PFD

V

(min) to V

PFD

VSS to V
V

PFD

(max) to V

(min).

(min) to VSS fall time of less than tFB may cause corruption of RA M data.

(min) VCC Rise Time

PFD

(max) to Inputs Recognized

(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-

PFD

(min) VCC Fall Time

PFD

(max) VCC Rise Time

PFD

Figure 5. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

tF

tPD

INPUTS

tFB

tDR

tRB

DON'T CARE

0 µs

300 µs

10 µs
10 µs

1µs

40 200 ms

tR

tREC

RECOGNIZEDRECOGNIZED

6/18

OUTPUTS

VALID VALID

(PER CONTROL INPUT)

HIGH-Z

(PER CONTROL INPUT)

AI01168C