5 V, 64 Kbit (8 Kb x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM and power-
fail control circuit
■ Unlimited WRITE cycles
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(V
= power-fail deselect voltage):
PFD
–M48Z08: V
4.5 V ≤ V
–M48Z18: V
4.2 V ≤ V
■ Self-contained battery in the CAPHAT™ DIP
package
■ Pin and function compatible with JEDEC
standard 8 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
= 4.75 to 5.5 V;
CC
≤ 4.75 V
PFD
= 4.5 to 5.5 V;
CC
≤ 4.5 V
PFD
M48Z08
M48Z18
28
1
PCDIP28
Battery CAPHAT™
June 2011 Doc ID 2424 Rev 8 1/20
www.st.com
1
Contents M48Z08, M48Z18
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 16
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 2424 Rev 8 3/20
List of figures M48Z08, M48Z18
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 16
Figure 11. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 Description
1 Description
The M48Z08/18 ZEROPOWER® RAM is an 8 K x 8 non-volatile static RAM which is pin and
function compatible with the DS1225.
The monolithic chip provides a highly integrated battery-backed memory solution.
The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special write timing or limitations on the
number of writes that can be performed.
The 28-pin, 600 mil DIP CAPHAT
button cell in a single package.
Figure 1. Logic diagram
™
houses the M48Z08/18 silicon with a long-life lithium
V
CC
Table 1. Signal names
A0-A12 Address inputs
DQ0-DQ7 Data inputs / outputs
E
G Output enable
W WRITE enable
V
CC
V
SS
NC Not connected internally
13
A0-A12
W
E
G
Chip enable
Supply voltage
Ground
M48Z08
M48Z18
V
SS
8
DQ0-DQ7
AI01022
Doc ID 2424 Rev 8 5/20
Description M48Z08, M48Z18
Figure 2. DIP connections
Figure 3. Block diagram
NC V
1
A12
2
A7
3
A6
4
A5
5
A4
6
7
A3
A2
A1
A0
DQ0
8
9
10
11
M48Z08
M48Z18
12
DQ2
13
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
AI01183
A0-A12
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
POWER
V
PFD
8K x 8
SRAM ARRAY
V
SS
DQ0-DQ7
E
W
G
AI01394
6/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 Operation modes
2 Operation modes
The M48Z08/18 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
. As VCC falls below
CC
approximately 3 V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2. Operating modes
Mode V
Deselect
WRITE V
READ V
READ V
Deselect V
Deselect ≤ V
1. See Table 10 on page 15 for details.
SO
CC
4.75 to 5.5 V
or
4.5 to 5.5 V
to V
PFD
SO
(min)
(1)
(1)
E G W DQ0-DQ7 Power
V
IH
IL
IL
IL
X X X High Z CMOS standby
X X X High Z Battery backup mode
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High Z Active
is out of
CC
Active
Active
Note: X = V
or VIL; VSO = Battery backup switchover voltage.
IH
2.1 READ mode
The M48Z08/18 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
65,536 locations in the static storage array. Thus, the unique address specified by the 13
address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E
the E
and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
The state of the eight three-state data I/O signals is controlled by E
activated before t
the address inputs are changed while E
for output data hold time (t
) after the last
AVQ V
and G access times are also satisfied. If
) or output enable access time (t
ELQV
GLQV
).
and G. If the outputs are
, the data lines will be driven to an indeterminate state until t
AVQ V
and G remain active, output data will remain valid
) but will go indeterminate until the next address access.
AXQX
AVQ V
. If
Doc ID 2424 Rev 8 7/20
Operation modes M48Z08, M48Z18
Figure 4. READ mode AC waveforms
tAVAV
A0-A12
E
G
DQ0-DQ7
Note: WRITE enable (W
tAVQV tAXQX
tELQV
tELQX
tGLQV
tGLQX
) = high.
VAL ID
tEHQZ
tGHQZ
VAL ID
Table 3. READ mode AC characteristics
Symbol Parameter
t
AVAV
t
AVQ V
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. CL = 30 pF.
READ cycle time 100 ns
Address valid to output valid 100 ns
Chip enable low to output valid 100 ns
Output enable low to output valid 50 ns
(2)
Chip enable low to output transition 10 ns
(2)
Output enable low to output transition 5 ns
(2)
Chip enable high to output Hi-Z 50 ns
(2)
Output enable high to output Hi-Z 40 ns
Address transition to output transition 5 ns
(1)
M48Z08/M48Z18
Min Max
AI01385
Unit
2.2 WRITE mode
The M48Z08/18 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W
A WRITE is terminated by the earlier rising edge of W
valid throughout the cycle. E
or t
in must be valid t
from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-
WHAX
DVW H
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E
falls.
8/20 Doc ID 2424 Rev 8
or W must return high for a minimum of t
prior to the end of WRITE and remain valid for t
and G, a low on W will disable the outputs t
or E.
or E. The addresses must be held
from chip enable
EHAX
afterward. G
WHDX
after W
WLQZ
M48Z08, M48Z18 Operation modes
Figure 5. WRITE enable controlled, WRITE mode AC waveform
tAVAV
A0-A12
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VAL ID
tAVWH
tWLWH
tWHDX
DATA INPUT
tDVWH
Figure 6. Chip enable controlled, WRITE mode AC waveforms
tAVAV
A0-A12
tAVEL
VAL ID
tAVEH
tELEH
tWHAX
tWHQX
AI01386
tEHAX
E
W
DQ0-DQ7
tAVWL
tDVEH
tEHDX
DATA INPUT
AI01387B
Doc ID 2424 Rev 8 9/20
Operation modes M48Z08, M48Z18
Table 4. WRITE mode AC characteristics
Symbol Parameter
(1)
M48Z08/M48Z18
Unit
Min Max
t
AVAV
t
AVW L
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVW H
t
DVE H
t
WHDX
t
EHDX
t
WLQZ
t
AVW H
t
AVEH
t
WHQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. CL = 30 pF.
goes low simultaneously with W going low, the outputs remain in the high impedance state.
3. If E
WRITE cycle time 100 ns
Address valid to WRITE enable low 0 ns
Address valid to chip enable 1 low 0 ns
WRITE enable pulse width 80 ns
Chip enable low to chip enable 1 high 80 ns
WRITE enable high to address transition 10 ns
Chip enable high to address transition 10 ns
Input valid to WRITE enable high 50 ns
Input valid to chip enable 1 high 30 ns
WRITE enable high to input transition 5 ns
Chip enable high to input transition 5 ns
(2)(3)
WRITE enable low to output Hi-Z 50 ns
Address valid to WRITE enable high 80 ns
Address valid to chip enable high 80 ns
(2)(3)
WRITE enable high to output transition 10 ns
2.3 Data retention mode
With valid VCC applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
. The M48Z08/18 may respond to transient noise spikes on V
F
into the deselect window during the time the device is sampling V
of the power supply lines is recommended.
When V
drops below VSO, the control circuit switches power to the internal battery which
CC
preserves data. The internal button cell will maintain data in the M48Z08/18 for an
accumulated period of at least 11 years when V
As system power returns and V
power supply is switched to external V
(min) plus t
(min). E should be kept high as V
rec
inadvertent write cycles prior to system stabilization. Normal RAM operation can resume t
after V
exceeds V
CC
application note AN1012.
falls within the V
CC
rises above VSO, the battery is disconnected, and the
CC
(max). For more information on battery storage life refer to the
PFD
. Write protection continues until VCC reaches V
CC
PFD
(max), V
CC
CC
PFD
is less than VSO.
rises past V
(min) window. All outputs
PFD
. Therefore, decoupling
CC
(min) to prevent
PFD
(min), the
fall time
CC
that reach
CC
PFD
rec
10/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 Operation modes
2.4 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 7) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a Schottky diode from V
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 7. Supply voltage protection
V
CC
bus. These transients can be reduced if
CC
that drive it to values below VSS by as much as
CC
to VSS (cathode connected to VCC, anode to VSS).
CC
V
bus. The energy stored in the
CC
CC
0.1µF DEVICE
V
SS
AI02169
Doc ID 2424 Rev 8 11/20
Maximum ratings M48Z08, M48Z18
3 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
T
A
T
STG
T
SLD
V
IO
V
CC
I
O
P
D
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Ambient operating temperature 0 to 70 °C
Storage temperature (VCC off, oscillator off) –40 to 85 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltages –0.3 to 7 V
Supply voltage –0.3 to 7 V
Output current 20 mA
Power dissipation 1 W
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
12/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 DC and AC parameters
4 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6. Operating and AC measurement conditions
Parameter M48Z08 M48Z18 Unit
Supply voltage (VCC) 4.75 to 5.5 4.5 to 5.5 V
Ambient operating temperature (T
Load capacitance (CL) 100 100 pF
Input rise and fall times ≤ 5 ≤ 5ns
Input pulse voltages 0 to 3 0 to 3 V
Input and output timing ref. voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the point where data is no longer driven.
) 0 to 70 0 to 70 °C
A
Figure 8. AC testing load circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
OUT
CL = 100pF or 30pF
Table 7. Capacitance
Symbol Parameter
C
C
IO
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Input capacitance - 10 pF
IN
(3)
Input / output capacitance - 10 pF
(1)(2)
Min Max Unit
AI01398
Doc ID 2424 Rev 8 13/20
DC and AC parameters M48Z08, M48Z18
Table 8. DC characteristics
Symbol Parameter Test condition
(1)
Min Max Unit
I
I
LO
I
CC
I
CC1
I
CC2
V
V
V
V
OH
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted
2. Outputs deselected.
Input leakage current 0 V ≤ VIN ≤ V
LI
(2)
Output leakage current 0 V ≤ V
OUT
≤ V
CC
CC
Supply current Outputs open 80 mA
Supply current (standby) TTL E = V
IH
Supply current (standby) CMOS E = VCC – 0.2 V 3 mA
Input low voltage –0.3 0.8 V
IL
Input high voltage 2.2 VCC + 0.3 V
IH
Output low voltage IOL = 2.1 mA 0.4 V
OL
Output high voltage IOH = –1 mA 2.4 V
±1 µA
±1 µA
3mA
Figure 9. Power down/up mode AC waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
INPUTS
tF
tFB
tDR
DON'T CARE
NOTE
tR
tRECtPD tRB
RECOGNIZEDRECOGNIZED
OUTPUTS
VAL ID VAL ID
(PER CONTROL INPUT)
HIGH-Z
(PER CONTROL INPUT)
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E
V
rises past V
CC
rises above V
PFD
(min). Some systems may perform inadvertent WRITE cycles after VCC
PFD
(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system
is running.
AI00606
high as
14/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 DC and AC parameters
Table 9. Power down/up AC characteristics
Symbol Parameter
(1)
Min Max Unit
t
PD
(2)
t
F
t
FB
t
R
t
RB
t
rec
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. V
PFD
until 200 µs after V
3. V
PFD
E or W at VIH before power down 0 - µs
V
(3)
(max) to V
PFD
V
(min) to VSS VCC fall time 10 - µs
PFD
V
(min) to V
PFD
VSS to V
PFD
(min) VCC fall time 300 - µs
PFD
(max) VCC rise time 0 - µs
PFD
(min) VCC rise time 1 - µs
E or W at VIH before power-up 2 - ms
(max) to V
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
(min) fall time of less than tF may result in deselection/write protection not occurring
PFD
passes V
CC
PFD
(min).
Table 10. Power down/up trip points DC characteristics
Symbol Parameter
V
PFD
V
t
DR
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: T
noted).
3. At 25 °C, VCC = 0 V.
Power-fail deselect voltage
Battery backup switchover voltage 3.0 V
SO
(3)
Expected data retention time 11 Years
(1)(2)
Min Typ Max Unit
M48Z08 4.5 4.6 4.75 V
M48Z18 4.2 4.3 4.5 V
= 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
A
Doc ID 2424 Rev 8 15/20
Package mechanical data M48Z08, M48Z18
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark
Figure 10. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
B1 B
Note: Drawing is not to scale.
A2
A1AL
e1
e3
D
N
E
1
eA
C
PCDIP
Table 11. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 33.02 1.3
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N28 28
mm inches
16/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 Part numbering
6 Part numbering
Table 12. Ordering information scheme
Example: M48Z 08 –100 PC 1 TR
Device Type
M48Z
Supply voltage and write protect voltage
08 = V
18 = VCC = 4.5 to 5.5 V; V
Speed
–100 = 100 ns
Package
PC = PCDIP28
Temperature range
1 = 0 to 70 °C
Shipping method
blank = ECOPACK
TR = ECOPACK® package, tape & reel
= 4.75 to 5.5 V; V
CC
®
package, tubes
= 4.5 to 4.75 V
PFD
= 4.2 to 4.5 V
PFD
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 2424 Rev 8 17/20
Environmental information M48Z08, M48Z18
7 Environmental information
Figure 11. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
18/20 Doc ID 2424 Rev 8
M48Z08, M48Z18 Revision history
8 Revision history
Table 13. Document revision history
Date Revision Changes
Mar-1999 1 First issue
19-Jul-2001 2
19-Dec-2001 2.1 Remove all references to “clock”
21-Dec-2001 2.2 Changes to text to reflect addition of M48Z08Y option
20-May-2002 2.3 Modify reflow time and temperature footnotes (Ta ble 5 )
10-Sep-2002 2.4
01-Apr-2003 3 v2.2 template applied; updated test condition (Ta bl e 1 0 )
28-Aug-2004 4 Reformatted; removed references to ‘crystal’ (Figure 1)
14-Dec-2005 5 Updated template, Lead-free text, removed footnote (Ta bl e 8 , 12)
24-Mar-2009 6
27-May-2010 7
07-Jun-2011 8
2-socket SOH and 2-pin SH packages removed; reformatted;
temperature information added to tables (Ta bl e 7 , 8, 3, 4, 9, 10)
Remove all references to “SNAPHAT” and M48Z08Y part (Figure 1;
Ta bl e 5 , 6, 3, 4, 10, 12)
Reformatted document; added text to Section 5: Package mechanical
data; added Section 7: Environmental information.
Updated Section 3: Maximum ratings, Ta bl e 1 1 ; reformatted document;
minor textual changes.
Updated footnote of Table 5: Absolute maximum ratings; updated
Section 7: Environmental information.
Doc ID 2424 Rev 8 19/20
M48Z08, M48Z18
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20/20 Doc ID 2424 Rev 8
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