5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM and power-
fail control circuit
■ Unlimited WRITE cycles
■ READ cycle time equals WRITE cycle time
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(V
= power-fail deselect voltage):
PFD
–M48Z02: V
4.5 V ≤ V
–M48Z12: V
4.2 V ≤ V
■ Self-contained battery in the CAPHAT™ DIP
package
■ Pin and function compatible with JEDEC
standard 2 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
= 4.75 to 5.5 V;
CC
≤ 4.75 V
PFD
= 4.5 to 5.5 V;
CC
≤ 4.5 V
PFD
M48Z02
M48Z12
24
1
PCDIP24
Battery CAPHAT™
June 2011 Doc ID 2420 Rev 9 1/22
www.st.com
1
Contents M48Z02, M48Z12
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 17
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 2420 Rev 9 3/22
List of figures M48Z02, M48Z12
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 17
Figure 12. Shipping tube dimensions for PCDIP24 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 Description
1 Description
The M48Z02/12 ZEROPOWER® RAM is a 2 K x 8 non-volatile static RAM which is pin and
function compatible with the DS1220.
A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48Z02/12 silicon with a
long-life lithium button cell to form a highly integrated battery-backed memory solution.
The M48Z02/12 button cell has sufficient capacity and storage life to maintain data
functionality for an accumulated time period of at least 10 years in the absence of power
over commercial operating temperature range.
The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
Figure 1. Logic diagram
V
CC
11
A0-A10
W
E
G
Table 1. Signal names
A0-A10 Address inputs
DQ0-DQ7 Data inputs / outputs
E Chip enable
G Output enable
W WRITE enable
M48Z02
M48Z12
V
SS
8
DQ0-DQ7
AI01186
V
CC
V
SS
Supply voltage
Ground
Doc ID 2420 Rev 9 5/22
Description M48Z02, M48Z12
Figure 2. DIP connections
Figure 3. Block diagram
LITHIUM
CELL
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ2
SS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
1
2
3
4
5
6
7
8
9
10
11
12
M48Z02
M48Z12
POWER
V
PFD
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
2K x 8
SRAM ARRAY
AI01187
A0-A10
DQ0-DQ7
E
W
V
CC
6/22 Doc ID 2420 Rev 9
G
V
SS
AI01255
M48Z02, M48Z12 Operation modes
2 Operation modes
The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
. As VCC falls below
CC
approximately 3 V, the control circuitry connects the battery which maintains data operation
until valid power returns.
Table 2. Operating modes
Mode V
CC
E G W
DQ0-
DQ7
is out of
CC
Power
Deselect
WRITE V
READ V
READ V
Deselect VSO to V
Deselect ≤ V
1. See Table 10 on page 16 for details.
Note: X = V
or VIL; VSO = battery backup switchover voltage.
IH
4.75 to 5.5 V
2.1 READ mode
The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E
the E
and G access times are not met, valid data will be available after the latter of the chip
enable access time (t
The state of the eight three-state data I/O signals is controlled by E
activated before t
the address inputs are changed while E
for output data hold time (t
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High Z Active
AVQ V
or
4.5 to 5.5 V
(min)
PFD
(1)
SO
(1)
V
IH
IL
IL
IL
X X X High Z CMOS standby
X X X High Z Battery backup mode
and G access times are also satisfied. If
) or output enable access time (t
ELQV
GLQV
).
and G. If the outputs are
, the data lines will be driven to an indeterminate state until t
AVQ V
and G remain active, output data will remain valid
) but will go indeterminate until the next address access.
AXQX
Active
Active
) after the last
AVQ V
. If
Doc ID 2420 Rev 9 7/22
Operation modes M48Z02, M48Z12
Figure 4. READ mode AC waveforms
tAVAV
A0-A10
E
G
DQ0-DQ7
Note: WRITE enable (W
tAVQV tAXQX
tELQV
tELQX
tGLQV
tGLQX
) = high.
VAL ID
tEHQZ
tGHQZ
VAL ID
AI01330
Table 3. READ mode AC characteristics
M48Z02/M48Z12
Symbol Parameter
t
AVAV
t
AVQ V
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
READ cycle time 70 150 200 ns
Address valid to output valid 70 150 200 ns
Chip enable low to output valid 70 150 200 ns
Output enable low to output valid 35 75 80 ns
Chip enable low to output transition 5 10 10 ns
Output enable low to output transition 5 5 5 ns
Chip enable high to output Hi-Z 25 35 40 ns
Output enable high to output Hi-Z 25 35 40 ns
Address transition to output transition 10 5 5 ns
(1)
Unit–70 –150 –200
Min Max Min Max Min Max
2.2 WRITE mode
The M48Z02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W
earlier rising edge of W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G
, a low on W will disable the outputs t
8/22 Doc ID 2420 Rev 9
or E. The addresses must be held valid throughout the cycle. E or W
from chip enable or t
EHAX
afterward. G should be kept high during WRITE
WHDX
WLQZ
or E. A WRITE is terminated by the
from WRITE enable prior
WHAX
DVW H
after W falls.
prior to the
M48Z02, M48Z12 Operation modes
Figure 5. WRITE enable controlled, WRITE AC waveform
tAVAV
A0-A10
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VAL ID
tAVWH
tWLWH
tDVWH
Figure 6. Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A10
tAVEL
VAL ID
tAVEH
tELEH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI01331
tEHAX
E
W
DQ0-DQ7
tAVWL
tDVEH
tEHDX
DATA INPUT
AI01332B
Doc ID 2420 Rev 9 9/22
Operation modes M48Z02, M48Z12
Table 4. WRITE mode AC characteristics
M48Z02/M48Z12
Symbol Parameter
(1)
Unit–70 –150 –200
Min Max Min Max Min Max
t
AVAV
t
AVW L
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVW H
t
DVEH
t
WHDX
t
EHDX
t
WLQZ
t
AVW H
t
AVEH
t
WHQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
WRITE cycle time 70 150 200 ns
Address valid to WRITE enable low 0 0 0 ns
Address valid to chip enable 1 low 0 0 0 ns
WRITE enable pulse width 50 90 120 ns
Chip enable low to chip enable 1 high 55 90 120 ns
WRITE enable high to address transition 0 10 10 ns
Chip enable high to address transition 0 10 10 ns
Input valid to WRITE enable high 30 40 60 ns
Input valid to chip enable high 30 40 60 ns
WRITE enable high to input transition 5 5 5 ns
Chip enable high to input transition 5 5 5 ns
WRITE enable low to output Hi-Z 25 50 60 ns
Address valid to WRITE enable high 60 120 140 ns
Address valid to chip enable high 60 120 140 ns
WRITE enable high to output transition 5 10 10 ns
2.3 Data retention mode
With valid VCC applied, the M48Z02/12 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
falls within the V
CC
PFD
(max), V
(min) window. All outputs
PFD
become high impedance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
into the deselect window during the time the device is sampling V
. The M48Z02/12 may respond to transient noise spikes on V
F
. Therefore, decoupling
CC
(min), the
PFD
CC
fall time
CC
that reach
of the power supply lines is recommended.
The power switching circuit connects external V
when V
too low, an internal Battery Not OK (BOK
after power up. If the BOK
rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is
CC
) flag will be set. The BOK flag can be checked
flag is set, the first WRITE attempted will be blocked. The flag is
to the RAM and disconnects the battery
CC
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7
on page 11 illustrates how a BOK
check routine could be structured.
For more information on a battery storage life refer to the application note AN1012.
10/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 Operation modes
Figure 7. Checking the BOK flag status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
COMPLEMENT
OF FIRST
(BATTERY OK)
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
IS DATA
READ?
YES
(BATTERY LOW)
NO
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
AI00607
Doc ID 2420 Rev 9 11/22
Operation modes M48Z02, M48Z12
2.4 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a Schottky diode from V
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 8. Supply voltage protection
V
CC
bus. These transients can be reduced if
CC
that drive it to values below VSS by as much as
CC
to VSS (cathode connected to VCC, anode to VSS).
CC
bus. The energy stored in the
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
12/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 Maximum ratings
3 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
T
A
T
STG
T
SLD
V
IO
V
CC
I
O
P
D
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Ambient operating temperature Grade 1 0 to 70 °C
Storage temperature (VCC off, oscillator off) –40 to 85 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltages –0.3 to 7 V
Supply voltage –0.3 to 7 V
Output current 20 mA
Power dissipation 1 W
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 2420 Rev 9 13/22
DC and AC parameters M48Z02, M48Z12
4 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Tabl e 6 :
Operating and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Table 6. Operating and AC measurement conditions
Parameter M48Z02 M48Z12 Unit
Supply voltage (VCC) 4.75 to 5.5 4.5 to 5.5 V
Ambient operating temperature (T
Load capacitance (CL) 100 100 pF
Input rise and fall times ≤ 5 ≤ 5ns
Input pulse voltages 0 to 3 0 to 3 V
Input and output timing ref. voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the point where data is no longer driven.
) Grade 1 0 to 70 0 to 70 °C
A
Figure 9. AC testing load circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
OUT
CL = 100pF
Table 7. Capacitance
Symbol Parameter
C
C
IO
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
Input capacitance - 10 pF
IN
(3)
Input / output capacitance - 10 pF
(1)(2)
Min Max Unit
AI01019
14/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 DC and AC parameters
Table 8. DC characteristics
Symbol Parameter Test condition
(1)
Min Max Unit
I
I
LO
I
CC
I
CC1
I
CC2
V
V
V
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. Outputs deselected.
Input leakage current 0V ≤ VIN ≤ V
LI
(2)
Output leakage current 0V ≤ V
OUT
≤ V
CC
CC
Supply current Outputs open 80 mA
Supply current (standby) TTL E = V
IH
Supply current (standby) CMOS E = VCC – 0.2 V 3 mA
Input low voltage –0.3 0.8 V
IL
Input high voltage 2.2 VCC + 0.3 V
IH
Output low voltage IOL = 2.1 mA 0.4 V
OL
Output high voltage IOH = –1 mA 2.4 V
OH
±1 µA
±1 µA
3mA
Figure 10. Power down/up mode AC waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
INPUTS
tF
tFB
tDR
DON'T CARE
NOTE
tR
tRECtPD tRB
RECOGNIZEDRECOGNIZED
OUTPUTS
VAL ID VAL ID
(PER CONTROL INPUT)
HIGH-Z
(PER CONTROL INPUT)
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E
V
rises past V
CC
rises above V
PFD
(min). Some systems may perform inadvertent WRITE cycles after VCC
PFD
(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system
is running.
AI00606
high as
Doc ID 2420 Rev 9 15/22
DC and AC parameters M48Z02, M48Z12
Table 9. Power down/up AC characteristics
Symbol Parameter
(1)
Min Max Unit
t
PD
(2)
t
F
t
FB
t
R
t
RB
t
REC
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2. V
PFD
until 200 µs after V
3. V
PFD
E or W at VIH before power down 0 - µs
V
(3)
(max) to V
PFD
V
(min) to VSS VCC fall time 10 - µs
PFD
V
(min) to V
PFD
VSS to V
(min) VCC rise time 1 - µs
PFD
(min) VCC fall time 300 - µs
PFD
(max) VCC rise time 0 - µs
PFD
E or W at VIH after power up 2 - ms
(max) to V
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
(min) fall time of less than tF may result in deselection/write protection not occurring
PFD
passes V
CC
PFD
(min).
Table 10. Power down/up trip points DC characteristics
Symbol Parameter
V
PFD
V
t
DR
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: T
noted).
3. At 25 °C, VCC = 0 V.
Power-fail deselect voltage
Battery backup switchover voltage 3.0 V
SO
(3)
Expected data retention time 10 YEARS
(1)(2)
Min Typ Max Unit
M48Z02 4.5 4.6 4.75 V
M48Z12 4.2 4.3 4.5 V
= 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
A
16/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 Package mechanical data
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline
B1 B
Note: Drawing is not to scale.
Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical
data
Symb
Typ Mi n Max Typ Mi n Max
A2
A1AL
e1
e3
D
N
E
1
eA
mm inches
C
PCDIP
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 34.29 34.80 1.350 1.370
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 27.94 1.1
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N24 24
Doc ID 2420 Rev 9 17/22
Package mechanical data M48Z02, M48Z12
Figure 12. Shipping tube dimensions for PCDIP24 package
1011292_E
Note: All dimensions are in inches.
18/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 Part numbering
6 Part numbering
Table 12. Ordering information scheme
Example: M48Z 02 –70 PC 1
Device type
M48Z
Supply voltage and write protect voltage
02 = V
12 = VCC = 4.5 to 5.5 V; V
Speed
–70 = 70 ns (M48Z02/12)
–150 = 150 ns (M48Z02/12)
–200 = 200 ns (M48Z02/12)
Package
PC = PCDIP24
Temperature range
1 = 0 to 70 °C
1. Not recommended for new design. Contact local ST sales office for availability.
= 4.75 to 5.5 V; V
CC
= 4.5 to 4.75 V
PFD
= 4.2 to 4.5 V
PFD
(1)
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest you.
Doc ID 2420 Rev 9 19/22
Environmental information M48Z02, M48Z12
7 Environmental information
Figure 13. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
20/22 Doc ID 2420 Rev 9
M48Z02, M48Z12 Revision history
8 Revision history
Table 13. Document revision history
Date Revision Changes
May-1999 1 First issue
09-Jul-2001 2
17-Dec-2001 2.1 Remove references to “clock” in document
20-May-2002 2.2 Updated V
01-Apr-2003 3 v2.2 template applied; test condition updated (Ta b l e 1 0)
22-Apr-2003 3.1 Fix error in ordering information (Ta ble 1 2 )
12-Dec-2005 4
02-Nov-2007 5
03-Dec-2008 6 Added Section 7: Environmental information; minor formatting changes.
27-May-2010 7 Updated Section 3, Tabl e 1 1, text in Section 5; reformatted document.
21-Jan-2011 8
07-Jun-2011 9 Updated footnote of Table 5: Absolute maximum ratings.
Reformatted; temperature information added to tables (Ta bl e 5 , 6, 7, 8,
3, 4, 9, 10); Figure updated (Figure 10)
noise and negative going transients text
CC
Update template, Lead-free text, and remove references to ‘crystal’ and
footnote (Ta bl e 8 , 12)
Reformatted document; added lead-free second level interconnect
information to cover page and Section 5: Package mechanical data;
updated Ta b le 5 , 6, 8, 9, 10, 12.
Updated Table 12: Ordering information scheme for 200 ns version of
devices; updated Section 7; added Figure 12; minor textual updates.
Doc ID 2420 Rev 9 21/22
M48Z02, M48Z12
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22/22 Doc ID 2420 Rev 9
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