The L6920 is a high efficiency step-up controller requiring only three external components to realize the
conversion from the battery voltage to the selected
output voltage.
The start up is guaranteed at 1V and the device is operating down to 0.6V.
Internal synchronous rectifier is implemented with a
120m
Ω
P-channel MOSFET and, in order to improve
the efficiency, a variable frequency control is implemented.
Figure 1. Application Circuit
L1
V
CC
2.5V3.3V
February 2005
C2
LX
SHDN
LBI
REF
7
5
L6920D
2
4
OUT
8
V
OUT
FB
1
500mA
C3C1
LBO
3
GND
6
Rev. 2
1/13
L6920
8
Table 1. Pin Description
PinNameFunction
1FB
Output voltage selector. Connect FB to GND for Vout=5V or to OUT for Vout=3.3V. Connect FB to an
external resistor divider for adjustable output voltage (from 2V to 5.2V) [see R4 and R5, fig. 7].
2LBIBattery low voltage detector input. The internal threshold is set to 1.23V.
A resistor divider is needed to adjust the desired low battery threshold:
R1
V
LBI
3
LBO
Battery low voltage detector output. If the voltage at the LBI pin drops below the internal
⎛⎞
1.23V=1
⋅
⎝⎠
[see R1 and R2, fig. 7]
------- -+
R2
threshold typ. 1.23V, LBO goes low.
LBO is an open drain output and so a pull-up resistor (about 200KΩ) has to be added for
The
correct output setting [see R3, fig. 7].
4REF1.23V reference voltage. Bypass this output to GND with a 100nF capacitor for filtering high
frequency noise. No capacitor is required for stability
5
SHDN
Shutdown pin. When pin 5 is below 0.2V the device is in shutdown, when pin 5 is above 0.6V the
device is operating.
6GNDGround pin
7LXStep-up inductor connection
8OUTPower OUTPUT pin
Figure 2. Pin Connection (Top view)
FB
LBI
LBO
REF
8
2
3
4
TSSOP
7
6
5
OUT1
LX
GND
SHDN
Table 2. Absolute Maximum Ratings
SymbolParameterValueUnit
V
ccmax
Vcc to GND6V
LBI, SHDN, FB to GND6V
V
out max
Vout to GND6V
Table 3. Thermal Data
SymbolParameterValueUnit
R
th j-amb
T
Thermal Resistance Junction to Ambient250°C/W
Maximum Junction Temperature 150°C
j
2/13
L6920
Table 4. Electrical Characteristcs
= 2V, FB = GND, T
(V
in
SymbolParameterTest ConditionMin. Typ.Max.Unit
SECTION
V
CC
V
Minimum operating Input Voltage0.6V
in
V
Minimum Start Up Input Voltage1V
in
= -40°C to 85°C and Tj < 125°C unless otherwise specified)
amb
Quiescent CurrentIl =0 mA, FB = 1.4V, V
I
q
I
Shut Down CurrentVin = 5V, Il =0 mA0.11µA
sd
IrevReverse battery currentV
LBI = SHDN = 2V, T
Il =0 mA, FB = 1.4V, V
LBI = SHDN = 2V, T
= -4V, Tj = T
in
amb
= T
j
= T
j
= 3.3V
out
amb
= 5V
out
amb
915µA
1118µA
0.12µA
POWER SECTION
on-N
on-P
Active switch ON resistance120250mΩ
Synchronous switch ON
120250mΩ
R
R
resistance
CONTROL SECTION
V
tOutput voltageFB = OUT, Il =0 mA3.23.33.4V
ou
FB = GND, I
=0 mA4.955.1V
l
Output voltage rangeExternal divider25.2V
V
V
LBI threshold1.181.231.27V
LBI
< 70°C1.2051.231.255V
j
< 250µA 0.20.4V
sink
LBO
LBO logic LOW
0°C < T
I
I
LX switch current limit0.811.2A
lim
T
onmax
T
offmin
Maximum on timeV
Minimum off timeV
SHDNSHDN logic LOW
SHDN logic HIGH
V
Reference Voltage1.181.231.27V
ref
= 2V to 5.3V3.7556.25µs
out
= 2V to 5.3V0.7511.25µs
out
0.2V
0.6V
3/13
L6920
Figure 3.
Efficiency vs. Output Current
100
90
80
Vin = 1.2V
70
60
η [%]
50
EFFICIENCY
40
30
20
10
0
0.010.11101001000
Figure 4.
Efficiency vs. Output Current
100
90
80
LOAD CURRENT [ mA]
Vout = 3.3V
L = 47µH
C = 100µF
Vin = 1.2V
70
Vin = 2.4V
Vin = 3.6V
Vin = 2.4V
Figure 5. Startup Voltage vs Output Current
1.4
1.2
1
0.8
0.6
Startup voltage (V)
0.4
0.2
0
306090120150180
Output current (mA)
L = 47µH
C = 22µF
60
50
η [%]
EFFICIENCY
40
30
20
10
0
0.010.11101001000
f
Vout = 5V
L = 47µH
C = 100µF
LOAD CURRENT [mA]
4/13
L6920
3Detailed Description
The L6920 is a high efficiency, low voltage step-up DC/DC converter particularly suitable for 1 to 3 cells (Li-Ion/
polymer, NiMH respectively) battery up conversion.
µ
These performances are achieved via a strong reduction of quiescent current (10
chronous rectification, that implies also a reduced cost in the application (no external diode required).
Operation is based on maximum ON time - minimum OFF time control, tailored by a current limit set to 1A. A
simplified block diagram is shown here below.
Figure 6. Simplified Block Diagram
A only) and adopting a syn-
V
REF
SHDN
LBO
-
+
VBG
FBY
V
OUT
GND
R1,R
Y
VBG
2
-
+
Toff min
1µsec
VBG
A
B
C
-
+
4Principle of Operation
A
B
C
OPAMP
(CR)
LBI
ZERO CROSSING
RQS
Ton max
5µsec
-
+
- +
CURRENT LIMIT
OUT
VOUT
LX
-
+
GND
FB
D99IN1041
V
OUT
V
IN
In L6920 the control is based on a comparator that continuously checks the status of output voltage.
If the output voltage is lower than the expected value, the control function of the L6920 directs the energy stored
in the inductor to be transferred to the load. This is accomplished by alternating between two basic steps:
- TON phase: the energy is transferred from the battery to the inductor by shorting LX node to ground via the Nchannel power switch. The switch is turned off if the current flowing in the inductor reaches 1A or after a maximum on time set to 5
µ
s.
- TOFF phase: the energy stored in the inductor is transferred to the load through the synchronous switch for at
least a minimum off time equal to 1
µ
s. After this, the synchronous switch is turned off as soon as the output
voltage goes lower than the regulated voltage or the current flowing in the inductor goes down to zero.
So, in case of light load, the device works in PFM mode, as shown in figures 7 to 10.
5/13
L6920
Figure 7.
PFM mode Condition: V
= 5V; Vin =1.5V.
out
Trace1: Vout (50mV~/div) Trace 4: IL (100mA/div)
Time div.: 5µs/div
Figure 8.
Trace1: V
Heavier load - Train pulses overlapping.
(100mV~/div) Trace 4: IL (200mA/div)
out
Time div.: 10 µs/div
Figure 9.
below I
Heavy load - Inductor current ripples
Trace1: V
lim
(100mV~/div)
out
Trace 4: IL
(200mA/div) Time div.: 20 µs/div
Figure 10.
Heavy load and High ESR. Regulation
falls in continuous mode of operation. Trace1:
(100mV~/div) Trace 4: IL (200mA/div). Time
V
out
div.: 5 µs/div
When Iload is heavier, the pulse trains are overlapped. Figures 7 - 8 show some possible behaviors.
Considering that current in the inductor is limited to 1A, the maximum load current is defined by the following
relationship:
Where
η
is the efficiency and I
I
load_lim
lim
=1A.
V
in
⎛⎞
-----------
V
out
–
I
limToff min
⎝⎠
–
V
outVin
------------------------- -
⋅
2L⋅
η⋅⋅=
eq. (1)
Of course, if Iload is greater than Iload_lim the regulation is lost (figure 11).
6/13
L6920
Figure 11. No regulation. I
V
Trace1:
(100mV~/div) Trace 4: IL (200mA/div).
out
load
> I
load_lim
Time div.: 5 µs/div
4.1 Start-up
One of the key features of L6920 is the startup at supply voltage down to 1V (please see the diagram in
Figure 5. in case of heavy load).
The device leaves the startup mode of operation as
soon as VOUT goes over 1.4V. During startup, the
synchronous switch is off and the energy is transferred to the load through its intrinsic body diode.
The N-channel switches with a very low RDSon
thanks to an internal charge pump used to bias the
power mos gate. Because of this modified behavior,
TON/TOFF times are lengthened. Current limit and
zero crossing detection are still available.
4.2 Shutdown
In shutdown mode (
SHDN
pulled low) all internal circuitries are turned off, minimizing the current provided by the battery (I
< 100 nA, in typical case).
SHDN
Both switches are turned off, and the low battery
comparator output is forced in high impedance state.
The synchronous switch body diode causes a parasitic path between power supply and output that can't
be avoided also in shutdown.
4.3 Low battery detection
The L6920 includes a low battery detector comparator. Threshold is VREF voltage and a 1.3% hysteresis is added to avoid oscillations when input crosses
the threshold slowly. The
LBO
is an open drain out-
put so a pull up resistor is required for a proper use.
4.4 Reverse polarity
A protection circuit has been implemented to avoid
that L6920 and the battery are destroyed in case of
wrong battery insertion.
In addition, this circuit has been designed so that the
current required by the battery is zero also in reverse
polarity.
5Application Information
5.1 Output voltage selection
Output voltage must be selected acting on FB pin.
Three choices are available: fixed 3.3V, 5V or adjustable output set via an external resistor divider.
Table 5. Output Voltage Selection
V
= 3.3VFB pin connected to OUT (see
OUT
= 5VFB pin connected to GND
V
OUT
2V ≤ V
≤ 5.2VFB pin connected to a resistive
OUT
application circuit)
divider
V
OUT
=
⎛⎞
1.23V 1
⎝⎠
R4
------- -+
R5
7/13
L6920
Figure 12. Demoboard Circuit
+VBATT
R1
N.C.
LBI
R2
N.C.
VREF
C4
100nF
GND
not mounted components
VBATT
2
4
6
L6920
F.B.
Panasonic
ELL6RH100M
L1 10µH
7
VOUT
8
R3
N.C.
LBO
3
SHDN
5
1
J1
C3
N.C.
1
2
3
1
2
J2
3
C2
47µF
C1
47µF
R4 N.C.
R5 N.C.
Panasonic
EEFCDJ470R
Panasonic
EEFCDJ470R
D01IN1310
+VBATT
GND
VOUT
GND
LBO
SHDN
Table 6.
Jumper Position Function
1-2Device enabled
J1
2-3Device disabled
NoneAdjustable using R4 and R5 [not mounted]
J2
1-23.3V output voltage
2-35V output voltage
R4, R5 should be selected in the range of 100kΩ - 10MΩ to minimize consumption and error due to current sunk
by FB pin (few nA).
5.2 Output capacitor selection
The output capacitor affects both efficiency and output ripple so its choice has to be considered with particular
care.
The capacitance value should be in the range of about 10
µ
F-100µF.
An additional, smaller, low ESR capacitor can be in parallel for high frequency filtering. A typical value can be
around 1
µ
F.
If very high performances, in terms of efficiency and output voltage ripple, are required, a very low ESR capacitor has to be chosen.
Ceramic capacitors are the lowest ESR but they are very expensive.
Other possibilities are low-ESR tantalum capacitors, available from KEMET, AVX and other sources. POSCAP
capacitors from SANYO and polymeric capacitors from PANASONIC are also good.
Below there is a list of some capacitors suppliers. The cap values and rated voltages are only a suggested pos-
sibility
8/13
Table 7. Capacitors distributors main list
ManufacturerSeriesCap Value (µF)Rated Voltage (V)ESR (mΩ)
AVXTPS15 to 4706.350 to 1500
L6920
KEMETT510/T494/
T495
PANASONICEEFCD22 to 476.350 to 700
SANYO POSCAPTPA/B/C22 to 2306.340 to 80
SPRAGUE595D100 to 3906.3160 to 700
10 to 470630 to 1000
5.3 Inductor selection
Usually, inductors ranging between 5µH to 40µH satisfy most of the applications.
Small value inductors have smaller physical size and guarantee a faster response to load transient but in steady
state condition a bigger ripple on output voltage is generated. In fact the output ripple voltage is given by Ipeak
multiplied by ESR. Furthermore, as shown in equation (1), inductor size affects also the maximum current deliverable to the load. Lastly, a low series resistance is suggested if very high efficiency values are needed. Anyway, the saturation current of the choke should be higher than the peak current limit of the device (1A).
Good surface mounting inductors are available from COILCRAFTS, COILTRONICS, MURATA and other souces. In the following table are listed some suggested components.
Table 8. Inductors distributors main list
ManufacturerSeriesInductor Value (uH)Saturation Current (A)
CoilcraftDO1813HC22 to 331 to 1.2
DO16084.7 to 150.9 to 1.5
CoiltronicsUP1B22 to 331 to 1.2
TP34.7 to 150.97 to 1.6
BIHM76-222 to 331 to 1.2
HM76-14.7 to 101 to 1.5
MurataLQN6C10 to 221.2 to 1.7
PanasonicELL6SH10 to 220.9 to 1.5
ELL6RH5.1 to1011 to 1.55
SumidaCR434.7 to 100.84 to 1.15
5.4 Layout Guidelines
The board layout is very important in order to minimize noise, high frequency resonance problems and electromagnetic interference.
It is essential to keep as small as possible the high switching current circulating paths to reduce radiation and
resonance problems. So, the output and input cap should be very close to the device.
The external resistor dividers, if used, should be as close as possible to the pins of the device (FB and LBI) and
as far as possible from the high current circulating paths, to avoid pick up noise.
Large traces for high current paths and an extended groundplane, help to reduce the noise and increase the
efficiency.
For an example of recommended layout see the following evaluation board.
9/13
L6920
Figure 13. Demoboard Components (Top side).
Figure 14. Demoboard Layout (Top side).
4.5cm
4cm
Figure 15. Demoboard Layout (Bottom side).
4.5cm
4cm
4.5cm
4cm
10/13
6Package Information
Figure 16. TSSOP8 Mechanical Data & Package Dimensions
L6920
DIM.
A1.200.047
A10.0500.150 0.0020.006
A20.800 1.000 1.050 0.031 0.039 0.041
b0.1900.300 0.0070.012
c0.0900.200 0.0030.008
D (1) 2.900 3.000 3.100 0.114 0.118 0.122
E6.200 6.400 6.650 0.244 0.252 0.260
E1 (1) 4.300 4.400 4.500 0.169 0.173 0.177
e0.6500.026
L0.450 0.600 0.750 0.018 0.024 0.027
L11.0000.039
k0˚ (min.) 8˚ (max.)
aaa0.1000.004
Note: 1. D and F does n ot include mold flash o r protrusio ns.
mminch
MIN.TYP. MAX. MIN.TYP. MAX.
Mold flash or potrusions shall not excee d 0.15mm
(.006inch) per side .
OUTLINE AND
MECHANICAL DATA
TSSOP8
(Body 4.4mm)
0079397 (Jedec MO-153-AA)
11/13
L6920
7Revision History
Table 9. Revision History
DateRevisionDescription of Changes
May 20031First Issue.
February 20052Modified the max. value of the I
parameter in the Table 4 pag. 3.
sd
12/13
L6920
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