L6598
Fi
HIGH VOLTAGE RESONANT CONTROLLER
1 FEATURES
■ HIGH VOLTAGE RAIL UP TO 600V
■ dV/dt IMMUNITY ±50V/ns IN FULL
TEMPERATURE RANGE
■ DRIVER CURRENT CAPABILITY:
250mA SOURCE
450mA SINK
■ SWITCHING TIMES 80/40ns RISE/FALL WITH
1nF LOAD
■ CMOS SHUT DOWN INPUT
■ UNDER VOLTAGE LOCK OUT
■ SOFT START FREQUENCY SHIFTING
TIMING
■ SENSE OP AMP FOR CLOSED LOOP
CONTROL OR PROTECTION FEATURES
■ HIGH ACCURACY CURRENT CONTROLLED
OSCILLATOR
■ INTEGRATED BOOTSTRAP DIODE
■ CLAMPING ON Vs
■ SO16, DIP16 PACKAGES
2 DESCRIPTION
The device is manufactured with the BCD OFF LINE
gure 1. Packages
DIP-16
SO-16N
Table 1. Order Codes
Part Number Package
L6598 DIP-16
L6598D SO-16N
L6598D013TR Tape & Reel
technology, able to ensure voltage ratings up to
600V, making it perfectly suited for AC/DC Adapters
and wherever a Resonant Topology can be beneficial. The device is intended to drive two P ower MOS,
in the classical Half Bridge Topology. A dedicated
Timing Section allows the designer to set Soft Start
Time, Soft Start and Minimum Frequency. An Error
Amplifier, together with the two Enable inputs, are
made available. In addition, the integrated Bootstrap
Diode and the Zener Clamping on low voltage supply, reduces to a minimum the external parts needed
in the applications.
Figure 2. Block Diagram
OP AMP
Ifmin
Ifstart
VCO
+
-
V
REF
V
REF
OPOUT
OPIN-
OPIN+
Rfmin
Rfstart
Cf
June 2004
5
6
7
4
2
3
CONTROL
LOGIC
V
S
12
UV
DETECTION
DEAD
TIME
Iss
BOOTSTRAP
1
Css
DRIVER
DRIVING
LOGIC
HVG
DRIVER
LEVEL
SHIFTER
LVG DRIVER
+
-
+
-
Vthe1
Vthe2
D98IN887A
16
15
14
Vs
11
10
8
9
V
HVG
OUT
LVG
GND
EN1
EN2
BOOT
H.V.
C
BOOT
LOAD
1/17
L6598
Figure 3. Pin Connection
Css
Rfstart
Cf
Rfmin
OPOUT
OPIN-
OPIN+
1
2
3
4
5
6
7 GND
15
14
13
12
11
10
VBOOT16
HVG
OUT
N.C.
V
S
LVG
EN1 8 EN29
D98IN888
Table 2. Thermal Data
Symbol Parameter SO16N DIP16 Unit
R
th j-amb
Thermal Resistance Junction to Ambient 120 80 °C/W
Table 3. Pin Function
N. Name Function
1CSSSoft Start Timing Capacitor
2R
3CfOscillator Frequency Setting - see also R
4R
5OP
6OP
7OP
8 EN1 Half Bridge Latch ed En able
9 EN2 Half Bridge Unlatched Enable
10 GND Ground
11 LVG Low Side Driver Output
12 V
13 N.C. Not Connected
14 OUT High Side Driver Reference
15 HVG High Side Driver Output
16 V
Soft Start Frequency Setting - Low Impedance Voltage Source - See also C
fstart
, R
fmin
fstart
Minimum Oscillation Frequency Setting - Low Impedance Voltage Source - See also C
fmin
Sense OP AMP Output - Low Impedance
out
Sense Op Amp Inverting Input - High Impedance
on-
Sense Op Amp Non Inverting Input - High Impedance
on+
Supply Volatge with Internal Zener Clamp
s
Bootstrapped Supply Voltage
boot
f
f
2/17
Table 4. Absolute Maximum Ratings
Symbol Parameter Value Unit
L6598
V
dV
dV
EN1
I
EN1
I
S
V
LVG
V
OUT
V
HVG
V
BOOT
BOOT/dt
OUT/dt
V
ir
V
ic
, V
, I
V
opc
V
opd
V
opo
T
stg
Supply Current at Vcl (*) 25 mA
Low Side Output 14.6 V
High Side Reference -1 to V
High Side Output -1 to V
-18 V
BOOT
BOOT
Floating Supply Voltage 618 V
VBOOT pin Slew Rate (repetitive) ±50 V/ns
OUT pin Slew Rate (repetitive) ±50 V/ns
Forced Input Voltage (pins Rfmin, Rfstart) -0.3 to 5 V
Forced Input Volatge (pins Css, Cf) -0.3 to 5 V
Enable Input Voltage -0.3 to 5 V
EN2
Enable Input Current ±3 mA
EN2
Sense Op Amp Common Mode Range -0.3 to 5 V
Sense Op Amp Differential Mode Range -5 to 5 V
Sense Op Amp Output Voltage (forced) 4.6 V
Storage Temperature -40 to +150 °C
V
T
T
amb
(*) The device is provided of an internal Clamping Zener between GND and the Vs pin, It must not be supplied by a low impedance voltage
source.
Note : ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (Human Body Model).
Junction Temperature -40 to +150 °C
j
Ambient Temperature -40 to +1 25 °C
Table 5. Recommended Operating Conditions
Symbol Parameter Value Unit
V
S
V
out
V
boot
f
max
(*) If the condition Vboot - Vout < 18 is guaranteed, Vo ut can range from -3 to 580V.
Supply Voltage 10 to V
(*) High Side Reference -1 to Vboot-V
(*) Floating Supply Rail 500 V
Maximum Switching Frequency 400 kHz
cl
cl
V
V
3/17
L6598
Table 6. Electrical Characteristcs
= 12V; V
(V
S
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
SUPPLY VOLTAGE
V
suvp
V
suvn
V
suvh
V
cl
I
su
I
q
HIGH VOLTAGE SECTION
I
bootleak
I
outleak
R
don
HIGH/LOW SIDE DRIVERS
I
hvgso
I
hvgsi
I
lvgso
I
lvgsi
t
rise
t
15,11 Low/High Side Output Rise
fall
OSCILLATOR
DC 14 Output Duty Cycle 48 50 52 %
f
min
f
start
V
t
2, 4 Voltage to Current Converters
ref
d
TIMING SECTION
k
ss
SENSE OP AMP
6, 7 Input Bias Current 0.1 µA
io
ic
V
R
I
I
out+
V
l
IB
out
out-
BOOT
- V
OUT
= 12V; T
amb
= 25°C)
12 VS Turn On Threshold 10 10.7 11.4 V
VS Turn Off Threshold 7.3 8 8.7 V
Supply Voltage Under Voltage
2.7 V
hysteresis
Supply Voltage Clamping 14.6 15.6 16.6 V
Start Up Current Vs < V
Quiescent Current, fout =
Vs > V
suvn
suvp
23mA
250 µA
60kHz, no load
16 BOOT pin Leakage Current V
14 OUT pin Leakage Current V
= 580V 5 µA
BOOT
= 562V 5 µA
OUT
16 Bootstrap Driver On Resistance 100 150 300 Ω
15 High Side Driver Source Current V
High Side Driver Sink Current V
11 Low Side Driver Source Current V
Low Side Driver Sink Current V
HVG-VOUT
HVG-VBOOT
LVG-GND
LVG - VS
C
load
= 0 170 250 mA
= 0 300 450 mA
= 0 170 250 mA
= 0 300 450 mA
= 1nF 80 120 ns
Time
C
= 1nF 40 80 ns
load
Minimum Output Oscilla tio n
Cf = 470pF; R
= 50k 58.2 60 61.8 kHz
fmin
Frequency
Soft Start Ou tpu t Osc illa tio n
Frequency
Cf = 470pF; R
R
= 47k
fstart
fmin
= 50k;
114 120 126 kHz
1.922.1V
Threshold
14 Dead Time between Low and
0.2 0.27 0.35 µs
High Side Conduction
1 Soft Start Timing consta nt Css = 330nF 0.115 0.15 0.185 s/µF
Input Offset Voltage -10 10 mV
5 Output Re sis tan ce 200 300 Ω
Source Output Current V
Sink Output Current V
6,7 OP AMP input common mode
= 4.5V 1 mA
out
= 0.2V 1 mA
out
-0.2 3 V
range
4/17
L6598
9
Table 6. Electrical Characteristcs (continued)
(V
= 12V; V
S
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
GBW Sense Op Amp Gain Band
G
dc
COMPARATORS
V
the1
V
the2
t
pulse
(*) Guaranted by design
Figure 4. EN2 Timing Diagrams
BOOT
- V
OUT
= 12V; T
amb
= 25°C)
0.5 1 MHz
Width Product (*)
DC Open Loop Gain 60 80 dB
8 Enabling Comparator Threshold 0.56 0.6 0.64 V
9 Enabling Comparator Threshold 1.05 1.2 1.35 V
8,9 Minimum Pulse lenght 200 ns
V
S
f
OUT
f
start
f
min
EN2
V
Css
Figure 5. EN1 Timing Diagrams
HVG
LVG
EN1
EN2
T
SS
T
SS
D98IN88
D98IN890
5/17
L6598
Figure 6. Oscillator/Output Timing Diagram
C
f
HVG
LVG
D98IN897
3 BLOCK’S DIAGRAM DESCRIPTION
3.1 High/Low Side driving section
An High and Low Side driving Section provide the proper driving to the external Power MOS or IGBT. An high
sink/source driving current (450 /250 mA typ) ensure fast switc hing times also when size 4 Power MOS are used.
The internal logic ensures a minimum dead time to avoid cross-conduction of the power devices.
3.2 Timing and Oscillator Section
The device is provided of a soft start function. It consists in a period of time, TSS, in which the switching frequency shifts from f
start
to f
. This feature is explained in the following description (ref. fig.7 and fig.8).
min
Figure 7. Soft Start and frequency shifting block
Iss
IfminIfstart
Iosc
gm OSC
Css
6/17
L6598
During the soft start time the current ISS charges the capacitor CSS, generating a voltage ramp whi ch is delivered
to a transconductance amplifier, as shown in fig. 7. Thus this voltage signal is converted in a growing current
which is subtracted to I
start is equal to:
I
osc
. Therefore the current which drives the oscillator to set the frequency during the so ft
fstart
gmI
I
fminIfstartgmVCss
t()–()+ I
fminIfstart
+==
ss
--------------
C
ss
t–
[1]
V
REF
I
where [2]
At the start-up (t=0) the oscillator frequency is set by:
I
At the end of soft start (t = T
only by I
Since the second term of eq.1 is equal to zero, we have:
Note that there is not a fixed threshold of the voltage across C
the frequency shifting), and T
the I
(i.e. R
min
current has been designed to be a fraction of I
SS
I
SS
fmin
):
I
fstart
------------- -
K
fmin
0() I
osc
) the second term of eq.1 decreases to zero and the switching frequency is set
SS
I
fstart
depends on CSS, I
SS
→
T
------------- -
,
I
R
==
fminIfstart
()I
I
oscTss
gmI
ss
--------------
– 0T
C
ss
C
------------------------- -
SS
gmI
fsart
fmin
+ V
T
SS
fstart
ssIfstart
K
fstart
V
--------------- -
R
REF
fmin
→
SS
, gm, and ISS (eq. 5). Making TSS independent of I
, so:
fstart
→
T
SS
REF
, 2V== =
V
fstart
V
------------- -==
R
SS
REF
----------------+
R
fstart
[4]
ssIfstart
gmI
ss
ss
1
T
[3]
[5]
–→== =
SSkSSCSS
[6]
1
------------- -
R
fmin
REF
fmin
C
----------------------- -==
in which the soft start finishes (i.e. the end of
C
-----------
gmK
fstart
,
In this way the soft start time depends only on the capacitor C
Start Timing Constant) is 0.15 s/
The current I
wave on the oscillator capacitor C
to compute an approximate value of the oscillator frequency in normal operation is:
The degree of approximation depends on the frequency value, but i t remains very good in the range from 30kHz
to 100kHz (figg.9-13)
is fed to the oscillator as shown in fig. 7. It is twice mirrored ( x4 and x8) generating the triangular
osc
µ
F.
. Referring to the internal structure of the oscillator (fig.7), a good relationship
f
f
min
1.41
--------------------=
R
fminCf
. The typical value of the kSS constant (Soft
SS
[7]
7/17
L6598
Figure 8. Oscillator Block
X 4Iosc
Vth+
Vth-
+
S
R
+
X 8
Cf
8/17
L6598
)
Figure 9. Typ. fmin vs. Rfmin @ Cf = 470pF
f
min
(KHz)
D98IN891
100
80
60
40
20
20 40 60 80 100 R
fmin
(KΩ)
Figure 10. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
∆f
(KHz)
80
Rfmin=33KΩ
D98IN892
Figure 12. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
∆f
(KHz)
100
Rfmin=100KΩ
80
60
40
20
20 40 60 80 100 R
D98IN894
fstart
Figure 13. fmin @ different Rf vs Cf
fmin
(KHz)
400
Rf=19.9Kohm - calc.
Rf=19.9Kohm - mea s.
(KΩ)
60
40
20
20 40 60 80 100 R(KΩ
Figure 11. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
∆f
(KHz)
100
Rfmin=50KΩ
80
60
40
D98IN893
200
Rf=90Kohm - meas.
Rf=90Kohm - ca lc.
200
400
Cf (pF)
0
0
20
20 40 60 80 100 R
fstart
(KΩ)
9/17
L6598
3.3 Bootstrap Section
The supply of the high voltage section is obtained by means of a bootstrap circuitry. This solution normally requires an high voltage fast recovery diode for charging the boots trap capacitor (fig. 14a). In the device a patented integrated structure, replaces this external diode. It is realised by means of a high voltage DMOS, driven
synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 14b.
Figure 14. Bootstrap driver
BOOT
D
S
C
V
BOOT
LVG
S
V
V
V
BOOT
OUT
V
V
BOOT
OUT
C
BOOT
ab
To drive the synchronised DMOS it is necessary a voltage higher than the supply voltage Vs. This voltage is
obtained by means of an internal charge pump (fig. 14b).
The diode connected in series to the DMOS has been added to av oid undesi rable turn on of i t. The introductio n
of the diode prevents any current can flow from the V
turned off when the internal capacitor of the pump is not fully discharged.
The bootstrap driver introduces a voltage drop during the recharging of the capacitor C
side driver is on), which i ncreases with the frequency and with the siz e of the external power MOS. It is the sum
of the drop across the R
and of the diode threshold voltage. At low frequency this drop is very small and
DSON
can be neglected. Anyway increasing the frequency it must be taken in to account. In fact the drop, reducing
the amplitude of the driving signal, can s ignificantly increase the R
dissipation).
To be considered that in resonant powe r supplies the current whi ch flows in the power MOS decr eases increas ing the switching frequency and generally the increases of R
is negligible. The following equation is useful to compute the drop on the bootstrap driver:
[8]
V
dropIch eargRdson
V
diode
where Q
T
charge
is the gate charge of the external power MOS, R
g
is the time in which the bootstrap driver remains on (about the semiperiod of the switching frequency
minus the dead time). The typical resistance value of the bootstrap DMOS is 150 Ohm. For example using a
power MOS with a total gate charge of 30nC the drop on the bootstrap driver is about 3V, at a switching frequency of 200kHz. In fact:
pin to the VS one in case that the supply is quickly
boot
(i.e. when the low
boot
of the external power MOS (and so the
DSON
is not a problem because power dissipation
DSON
Q
g
V
→+
drop
dson
-------------------
T
ch earg
is the on resistance of the bootstrap DMOS, and
R
+==
dsonVdiode
30nC
V
drop
------------------
2.23µs
150Ω 0.6V~2.6V+=
To summarise, if a si gnifi cant dr op on the bootstrap driver (at high switc hing frequency when large power MOS
are used) represents a problem, an exter nal diod e can be used, av oi ding the drop o n the R
10/17
of the DMOS.
DSON
L6598
3.4 OP AMP Section
The integrated OP AMP is designed to offer Low Output Impedance, wide band, High i nput Impedance and wide
Common Mode Range. It can be readily used to implement protection features or a closed loop control . For this
purpose the OP AMP Output can be properly connected to R
3.5 Comparators
Two CMOS comparators are available to perform protection schemes. Short pulses ( >= 200ns) on Comparator s
Input are recognised. The EN1 input (active High), has a threshold of 0.6V (typical value) forces the device in a
latched shut down state (e.g. LVG Low, HVG low, Osc illator s topped), as i n the Under Vol tage Conditions . Normal Operating conditions are resumed after a power-off power-on sequence. The EN2 input (active high), with
a threshold of 1.2V (typical value) restarts a Soft Start sequence (see Timing Diagrams). In addition the EN2
Comparator, when activated, removes a latched shutdown caused by EN1.
Figure 15. Switching Time Waveform Definitions
pin to adjust the oscillation frequency.
fmin
HVG
90%
LVG
10% 10%
t
r
90%
10% 10%
t
r
t
f
Figure 16. Dead Time and Duty Cycle Waveform Definition
T
1
t
d
50%
HVG
90%
50%
90%
t
f
D98IN898
t
d
T
T
period
1
Dc =
LVG
50%
50%
T
period
50%
D98IN899
11/17
L6598
)
Figure 17. Typ. fmin vs. Temperature
f
min
(KHz)
70
60
50
40
-50 0 50 100
Figure 18. Typ. fstart vs. Temperature
f
fstart
(KHz)
130
D98IN895
D98IN896
T(˚C
Figure 20. Start Up Current vs Temperature
Isu
(µA)
200
150
100
50
-50
050
100
T (°C)
Figure 21. Quiescent Current vs Temperature
Iq
(mA)
2.3
2.1
Iq @ Vclamp
120
110
100
-50 0 50 100
T(˚C)
Figure 19. Vs thresholds and clamp vs temp.
Vs
(V)
14
12
10
8
6
-50 0
50
100
Vclamp
Vsuvp
Vsuvn
T (°C)
Iq @ 12V
1.9
1.7
1.5
-50
0
50
100
T (°C)
Figure 22. HVG Source and Sink Current vs.
Temperature
Ihvg
(mA)
500
400
Ihvg sink curr.
300
200
100
-50
050
Ihvg source cur r.
100
T (°C)
12/17
L6598
Figure 23. LVG Source and Sink Current vs.
Temperature
Ilvg
(mA)
500
400
Ilvg sink curr.
300
200
100
-50
050
Ilvg source cu rr.
100
T (°C)
Figure 25. Wide Range AC/DC Adapter Application
Figure 24. Soft Start Timing Constant vs.
Temperature
kss
(s/µF)
0.16
0.14
0.12
-50
050
100
T (°C)
85 to 270
Vac
L6598
VCO
&
CONTROL
L6561/2
Vo
DRIVER
TL431
ENABLE
D98IN874A_MOD2
13/17
L6598
Figure 26. DIP-16 Mechanical Data & Package Dimensions
DIM.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
DIP16
14/17
Figure 27. SO-16N Mechanical Data & Package Dimensions
L6598
DIM.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45° (typ.)
(1)
D
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
(1)
F
G 4.60 5.30 0.181 0.208
L 0.4 1.27 0.150 0.050
M 0.62 0.024
S8° (max.)
(1) "D" and "F " do not includ e mold f lash or prot rusions - Mol d
flash or protrusions shall not exceed 0.15mm (.006inc.)
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
9.8 10 0.386 0.394
3.8 4.0 0.150 0.157
OUTLINE AND
MECHANICAL DA T A
SO16 (Narrow)
0016020 D
15/17
L6598
Figure 28. Revision History
Date Revision Description of Chan g es
June 2004 5 Changed the impagination following the new release of “Corporate
Technical Pubblication Design Guide”.
Done a few of corrections in the text.
16/17
L6598
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of use of such information nor for any infringem ent of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notic e. T his publication supersedes an d replaces all information pre vio us ly supplied. STMicroelectronic s products are not
authorized for use as critical comp onents in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of ST M icroelectronics.
All other names are the property of their res pec t iv e ow ners
© 2004 STMicroelectronics - All right s reserved
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17/17
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