ST MICROELECTRONICS L 6205 N Datasheet

DMOS DUAL FULL BRIDGE DRIVER

■

OPERATING SUPPLY VOLTAGE FROM 8 TO 52V

■

5.6A OUTPUT PEAK CURRENT (2.8A DC)

■

R

■

OPERATING FREQUENCY UP TO 100KHz

■

NON DISSIPATIVE OVERCURRENT
PROTECTION

■

PARALLEL ED OPERATION

■

CROSS CONDUCTION PROTECTION

■

THERMAL SHUTDOWN

■

UNDER VOLTAGE LOCKOUT

■

INTEGRATED FAST FREE WHEELING DIODES

TYPICAL APPLICATIONS

■

BIPOLAR STEPPER MOTOR

■

DUAL OR QUAD DC MOTOR

DESCRIPTION

The L6205 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-

0.3Ω TYP. VA L U E @ Tj = 25 °C

DS(ON)

L6205

PowerDIP20

(16+2+2)

BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar c ir cuits on
the same chip. Available in PowerDIP20 (16+2+2),
PowerSO20 and SO20(16+2+2) packages, the
L6205 features a non-dissipative protection of the
high side PowerMOSFETs and thermal shutdown.

PowerSO20

ORDERING NUMBERS:

L6205N (PowerDIP 20)
L6205PD (PowerSO20)
L6205D (SO20)

SO20

(16+2+2)

BLOCK DIAGRAM

VBOOT

VCP

EN
IN1
IN2

EN
IN1
IN2

A
A
A

B
B
B

V

BOOT

CHARGE

PUMP

VOLTAGE

REGULA TOR

OCD

THERMAL

PROTECTION

10V
5V

OCD

VS

V

BOOT

OVER

A

B

CURRENT

DETECTION

GA TE

LOGIC

OVER

CURRENT

DETECTION

GA TE

LOGIC

10V 10V

V

BOOT

BRIDGE A

BRIDGE B

A

OUT1
OUT2

SENSE

V

S

B

OUT1
OUT2
SENSE

A
A

A

B
B

B

April 2002

D99IN1091A

1/18

L6205

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Test conditions Value Unit

V

V

IN,VEN

V

SENSE

V

BOOT

I

S(peak)

Supply Voltage 60 V

S

Input and Enable Voltage Range -0.3 to +7 V
DC Sensing Voltage Range -1 to +4 V
Bootstrap Peak Voltage VS + 10 V
Pulsed Supply Current (for each

t

< 1ms 7.1 A

PULSE

VS pin), internally limited by the
overcurrent protection

I

S

DC Supply Current (for each VS

2.8 A

pin)

V

OD

Differential Voltage Between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSE

, T

T

stg

Storage and Operating

OP

VSA = VSB = 60V
SENSEA =

B

60 V

SENSEB = GND

-40 to 150 °C

Temperature Range

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter MIN MAX Unit

V

V

V

SENSE

I

OUT

F

T

S

OD

j

sw

Supply Voltage 12 52 V
Differential Voltage Between

52 V
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSE

B

Sensing voltage

(pulsed tw<t

(DC)

)

rr

-6

-1

6

1
DC Output Current 2.8 A
Operating Junction Temperature -25 +125 °C
Commutation Frequency 100 kHz

V
V

2/18

L6205

THERMA L D ATA

Symbol Description PowerDIP20 SO20 PowerSO20 Unit

R

th-j-pins

R

th-j-case

R

th-j-amb1

R

th-j-amb1

R

th-j-amb1

R

th-j-amb2

<1> Mounted on a multilayer FR4 PCB with a dis sipating copp er surface on the bottom side of 6 cm2 (with a thi ckness of 35 µm).
<2> Mounted on a multilayer FR4 PCB with a dis sipating copp er surface on the top side of 6 cm2 (with a thickness of 35 µm).
<3> Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16 via holes

and a groun d l ayer.

<4> Mounted on a multilayer FR4 PCB withou t any heat sinkin g surface on the board.

MaximumThermal Resistance Junction-Pins 12 14 - °C/W
Maximum Thermal Resistance Junction-Case - - 1 °C/W

MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
MaximumThermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient

1

2

3

4

40 51 - °C/W

--35°C/W

--15°C/W

56 77 62 °C/W

PIN CONNECTIONS

IN1
IN2

SENSE

OUT1

GND GND
GND

OUT1

SENSE

IN1
IN2

1

A

2

A

3

A

4

A

5
6
7

B

8

B

9

B

10

B

PowerDIP20/SO20

(Top View)

D99IN1093A

20
19
18
17
16

14
13
12
11

EN

A

VCP
OUT2
VS

A

GND15
VS

B

OUT2
VBOOT
EN

B

GND GND

VS

A

A

OUT2

A

VCP

EN

A

IN1

A

IN2

A

B

SENSE

OUT1

A
A

GND

1
2
3
4
5
6
7
8
9

D99IN1092A

20
19
18
17
16
15
14
13
12
11

VS

B

OUT2
VBOOT
EN

B

IN2

B

IN1

B

SENSE
OUT1
GND10

B

B

B

PowerSO20

3/18

L6205

PIN DESCRIPTION

PACKAGE

SO20/

PowerDIP20

PowerSO20

PIN # PIN #

1 6 IN1
2 7 IN2
3 8 SENSE

4 9 OUT1

5, 6, 15, 16 1, 10, 11,

20

7 12 OUT1
8 13 SENSE

9 14 IN1
10 15 IN2
11 16 EN

Name Type Function

A

A

Logic Input Bridge A Logic Input 1.
Logic Input Bridge A Logic Input 2.

Power Supply Bridge A Source Pin. This pin must be connected to Power

A

Ground directly or through a sensing power resistor.

Power Output Bridge A Output 1.

A

GND GND Signal Ground terminals. In PowerDIP and SO packages,

these pins are also used for heat dissipation toward the
PCB.

Power Output Bridge B Output 1.

B

Power Supply Bridge B Source Pin. This pin must be connected to Power

B

Ground directly or through a sensing power resistor.

B

B

B

Logic Input Bridge B Logic Input 1.
Logic Input Bridge B Logic Input 2.

Logic Input (*) Bridge B Enable. LOW logic level switches OFF all Power

MOSFETs of Bridge B. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.

12 17 VBOOT Supply

Voltage
13 18 OUT2
14 19 VS

17 2 VS

18 3 OUT2

Power Output Bridge B Output 2.

B

Power Supply Bridge B Power Supply Voltage. It must be connected to

B

Power Supply Bridge A Power Supply Voltage. It must be connected to

A

Power Output Bridge A Output 2.

A

Bootstrap Voltage needed for driving the upper
PowerMOSFETs of both Bridge A and Bridge B.

the supply voltage together with pin VS

the supply voltage together with pin VS

.

A

.

B

19 4 VCP Output Charge Pump Oscillator Output.
20 5 EN

Logic Input (*) Bridge A Enable. LOW logic level switches OFF all Power

A

MOSFETs of Bridge A. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.

(*) Also connected at the output drain of the Overc urrent and Th ermal protec tion MOSFET. T herefore, it ha s t o be driven put t i ng in series a

resistor with a value in the range of 500Ω - 22KΩ, recommended 10k

Ω

4/18

L6205

ELECTRICAL CHARACTERISTICS

= 25 °C, Vs = 48V, unless otherwise specified)

(T

amb

Symbol Parameter Test Conditions Min Typ Max Unit

V

Supply Voltage 8 52 V

S

I

Quiescent Supply Current All Bridges OFF; -25°C<Tj <125°C 5.5 10 mA

S

T

Thermal Shutdown Temperature 150 °C

j

Output DMOS Transistors

I

R

DS(ON)

DSS

Leakage Current VS = 52V 10 µA
High-side Switch ON Resistance Tj = 25 °C0.340.4Ω

Low-side Switch ON Resistance Tj = 25 °C 0.28 0.34 Ω

Source Drain Diodes

V

Forward ON Voltage ISD = 2.8A, EN = LOW 1.2 1.4 V

SD

t

Reverse Recovery Time If = 2.8A 300 ns

rr

Forward Recovery Time 200 ns

t

fr

Switching Characteristics

t

D(on)EN

t

D(on)IN

t

t

D(off)EN

t

D(off)IN

Enable to out turn ON delay time
Input to out turn ON delay time

ON

Output rise time
Enable to out turn OFF delay time
Input to out turn OFF delay time

(5)

T

=125 °C 0.53 0.59 Ω

j

Tj =125 °C 0.47 0.53 Ω

(5)

I

=2.8A, Resistive Load 250 ns

LOAD

(5)

I

=2.8A, Resistive Load 600 ns

LOAD

I

=2.8A, Resistive Load 20 105 300 ns

LOAD

(5)

I

=2.8A, Resistive Load 450 ns

LOAD

(5)

I

=2.8A, Resistive Load 500 ns

LOAD

t

OFF

t

dt

f

CP

UVLO comp

V

th(ON)

V

th(OFF)

Logic Input

V

INL

V

INH

I

INH

Output Fall Time

(5)

I

=2.8A, Resistive Load 20 78 300 ns

LOAD

Dead Time Protection 1 µs

Charge pump frequency

-25°C<Tj <125°C 0.75 1 MHz

Turn ON threshold 6.6 7 7.4 V
Turn OFF threshold 5.6 6 6.4 V

Low level logic input voltage -0.3 0.8 V
High level logic input voltage 2 7 V
High level logic input current 5 V Logic Input Voltage 70 µA

5/18

L6205

ELECTRICAL CHARACTERISTICS

(T

= 25 °C, Vs = 48V, unless otherwise specified)

amb

(continued)

Symbol Parameter Test Conditions Min Typ Max Unit

I

Low level logic input current GND Logic Input Voltage -10 µA

INL

Over Current Protection

I

S OVER

Input Supply Over Current

-25°C<Tj <125°C 4 5.6 7.1 A

Protection Threshold

R

OPDR

<(5)> See Fig. 1.

Open Drain ON Resistance I = 4mA 60 Ω

Figure 1. Switching Characteristic Definition

or

I

E

N

N

50%

t

I

OUT

90%

10%

D02IN1348

t

D(OFF)

t

(OFF)

t

D(ON)

t

(ON)

t

6/18

L6205

5V

D01IN1329

9

0

CIRCUIT DESCRIPTION

POWER STAGES and CHARGE PUMP

The L6205 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd­son=0.3ohm (typical value @25°C), with intrinsic fast
freewheeling diode. Cross conduction protection is
achieved using a dead time (td = 1

µ

s typical) be­tween the switch off and swit ch on of two P ower MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis­tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 2. The oscillator output
(VCP) is a square wave at 750kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.

Table 1. Charge Pump External Components

Values

C

BOOT

C

P

R

P

D1 1N4148
D2 1N4148

220nF
10nF
100Ω

Figure 2. Char ge Pump Circuit

V

S

D1

R

C

VCP VBOOT VS

C

BOOT

D2

P

P

B

D01IN1328

VS

A

puts may be driven in one of two configurations as
shown in figures 4 or 5. If driven by an open drain
(collector) structure, a pull-up resistor R
pacitor C

are connected as shown in Fig. 4. If the

EN

and a ca-

EN

driver is a standard Push-Pull structure the resistor
R

and the capacitor CEN are connected as shown

EN

in Fig. 5. The resistor R

Ω

range from 500
R

and CEN are respectively 10KΩ and 100nF.

EN

to 22KΩ. Recommended values for

should be chosen in the

EN

More information on selecting the values is found in
the Overcurrent Protection section.

Figure 3. Logi c Inp ut s I nte rn a l St ructure

Figure 4. EN

and ENB Pins Open Collector

A

Driving

5V

5V

D02IN134

5V

D02IN135

OPEN

COLLECTOR

OUTPUT

Figure 5. EN

PUSH-PULL

OUTPUT

R

EN

ENA or EN

B

C

EN

and ENB Pins Push-Pull Driving

A

R

EN

ENA or EN

B

C

EN

LOGIC INPUTS

Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and

µ

C compatible logic inputs. The internal structure is
shown in Fig. 3. Typical value for turn- on and turn-off
thresholds are respectively Vthon=1.8V and
Vthoff=1.3V.
Pins EN

and ENB have identical input structure w ith

A

the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also c onnected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The EN

A

and ENB in-

TRUTH TABLE

INPUTS OUTPUTS

EN IN1 IN2 OUT1 OUT2

L X X High Z High Z
H L L GND GND
H H L Vs GND
HLHGNDVs
HHHVsVs

X = Don't care
High Z = High Impedance Output

7/18

L6205

NON-DISSIPATIV E OVERCURRENT PROTECTION

In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated for full protection.
This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this
internal over current detection, the external current sense resistor normally used and its associated power dis­sipation are eliminated. Fig ure 6 shows a simpl ified s chematic of the over curr ent detection cir c uit for the B ridge
A. Bridge B is provided of an analogous circuit.

To implement the over current detection, a sens ing element that deli vers a small but precise fraction of the out­put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur­rent I
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typ­ical) by an internal open dr ain MOS with a pull dow n capa bility of 4mA. By usi ng an external R-C on the EN pin,
the off time before recovering normal operation can be easily programmed by means of the accurate thresholds
of the logic inputs. Figure 7 shows the OCD operation.

Figure 6. Overcurrent Protection Simplified Schematic

. When the output c urrent r eaches the detec tion thresh old ( typi cally 5.6A) the OCD comparator signals

REF

POWER SENSE

1 cell

TO GATE

R

DS(ON)

60Ω TYP.

LOGIC

INTERNAL

OPEN-DRAIN

OCD

COMPARATOR

µC or LOGIC

+5V

RENEN

C

EN

A

Figure 7. Overcurrent Protection Wavefor ms

I

OUTA (or B)

V

ENA (orB)

5.6A

V

DD

OUT1

A

I

POWER DMOS

n cells

I

/ n

1A

(I1A+I2A) / n

I

REF

OVER TEMPERATURE

VS

A

1A I2A

+

OUT2

A

POWER DMOS

I

/ n

2A

HIGH SIDE DMOSs OF

THE BRIDGE A

POWER SENSE

n cells

D02IN1353

1 cell

8/18

V

TH ON

ON

BridgeA (or B)

OFF

T

D(OFF)

T

DISABLE

L6205

APPLICATION INF ORMATION

A typical application using L6205 is shown in Fig. 8. Typical component values for the application are shown in
Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins (VS
reduce high frequency transients generated by the switching. The capaci tors connected from the EN
inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is
detected (see Overcurrent Protection). The two current sources (SENSE
to Power Ground with a trac e length as short as possible in th e layout. To incr ease noise i mmunity, unused logi c
pins (except EN
description). It is recommended to keep Power Ground, Signal Ground and Charge Pump Ground (low side of
C

BOOT

Table 2. Component Values for Typical Application

C
C
C
C
C
C

and VSB) and ground near the L6205 to improve the high fr equenc y fil tering on the power supply and

A

and SENSEB) should be connected

A

and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin

A

capacitor) separated on PCB.

1
2
BOOT
P
ENA
ENB

100uF D
100nF D
220nF R

10nF R
100nF R
100nF

1
2
ENA
ENB
P

1N4148
1N4148

2K2Ω
2K2Ω
100Ω

and EN

A

B

Figure 8. Typ ic a l App li ca ti on

+

VS

8-52V

DC

POWER

GROUND

-

SIGNAL

GROUND

C

1

C

BOOT

VS

A

17

VS

C

P

VBOOT

SENSE

SENSE

OUT1
OUT2

OUT1
OUT2

VCP

B

14

19

12

A

3

B

8

A

4

A

18

B
B

13

C

2

D

1

R

P

D

2

LOAD

A

LOAD

B

20

11

9

10

1

2

16
157

6
5

D02IN1345

EN

EN

IN1

IN2

IN1

IN2

GND
GND
GND
GND

R

ENA

A

C

ENA

R

ENB

B

C

ENB

B

B

A

A

ENABLE

ENABLE

IN1

B

IN2

B

IN1

A

IN2

A

A

B

9/18

L6205

PARALLELED OPERATION

The outputs of the L6205 can be paralleled to increase the output current capability or reduce the power dissi­pation in the device at a given current level. It must be noted, however, that the internal wire bond connections
from the die to the power o r sense pins of the package m ust ca rry curr ent in both of the as sociated half bridges.
When the two halves of one full bridge (for example OUT1
current rating is not increased since the total current must still flow through one bond wire on the power supply
or sense pin. In addition, the over current detection senses the sum of the current in the upper devices of each
bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detec­tion threshold.

For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 9. The current in the two devices
connected in parallel will share very well since the R

DS(ON)

In this configuration the resulting Bridge has the following characteristics.

- Equivalent Device: FULL BRIDGE

- R

0.15Ω Typ. Value @ TJ = 25°C

DS(ON)

- 5.6A max RMS Load Current

- 11.2A OCD Threshold

Figure 9. Parallel connection for higher curren t

VS

C

P

VBOOT

SENSE

SENSE

OUT1

OUT2

OUT1

VS

VCP

A
B

A

B

A

A

B

B

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

C

1

LOAD

C

BOOT

C

2

D

1

R

P

D

2

and OUT2A) are connected in parallel, the peak

A

of the devices on the same die is well matched.

17

19

12

3

8

4

18

7

13

EN

1114

10

16
15

B

EN

IN1

1

IN2

2

IN1

9

IN2

GND
GND
GND

6

GNDOUT2

5

R

C

EN

EN

D02IN1359

A

A

A

B

B

EN20

IN1

IN2

To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge
2 of the Bridge A can be connected in parallel and the same done for the B ridge B as shown in Figure 10. In
this configuration, the pe ak c urrent for eac h hal f bridge is still l imited by the bond wires for the s upply and s ense
pins so the dissipation in the device will be reduced, but the peak current rating is not increased. This configu­ration, the resulting bridge has the following characteristics.

- Equivalent Device: FULL BRIDGE

- R

0.15Ω Typ. Value @ TJ = 25°C

DS(ON)

- 2.8A max RMS Load Current

- 5.6A OCD Threshold

10/18

Figure 10. Parallel connection with lower Over current Threshold

VS

A

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

LOAD

C

1

C

BOOT

C

2

D

1

D

C

R

2

P

P

VBOOT

SENSE

SENSE

OUT1

OUT2

OUT1

OUT2

VS

VCP

17

B

14

19

12

A

3

B

8

A

4

A

18

B

B

13

L6205

EN

20

10

16
157

A

EN

IN1

1

IN2

2

IN1

9

IN2

R

EN

B

C

A

A

B

B

EN11

EN

IN

A

IN

B

GND
GND
GND

6

GND

5

D02IN1360

It is also possible to parallel the four Half Bridges to obtain a simple Hal f Bridge as show n in Fig. 11 The resul ting
half bridge has the following characteristics.

- Equivalent Device: HALF BRIDGE

- R

0.075Ω Typ. Value @ TJ = 25°C

DS(ON)

- 5.6A max RMS Load Current

- 11.2A OCD Threshold

Figure 11. Paralleling the four Half Bridges

VS

C

P

VBOOT

SENSE

SENSE

OUT1

OUT2

OUT1

OUT2

VS

VCP

A

17

B

19

12

A

3

B

8

A

4

A

18

B

7

B

13

EN

B

1114

EN

IN1

1

IN2

2

IN1

9

IN2

10

GND

16

GND

15

GND

6

GND

5

R

C

EN

EN

EN20

IN

D02IN1366

A

A

A

B

B

VS

8-52V

+

DC

POWER

GROUND

-

SIGNAL

GROUND

C

1

C

BOOT

C

2

D

1

R

P

D

2

LOAD

11/18

L6205

OUTP UT CURRENT CAPABILITY AND IC POW ER DISSIPATION

In Fig. 12 and Fig. 13 are show n the approxi mate r elation between the output cur rent and the IC po wer dissipa­tion using PWM current control driving two loads, for two different driving types:

– One Full Bridge ON at a time (Fig. 12) in which only one load at a time is energized.
– Two Full Bridges ON at the same time (Fig. 13) in which two loads at the same time are energized.

For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guar­antee a safe operating junction temperature (125°C maximum).

Figure 12. IC Power Dissipation versus Output Curr ent with One Full Bridge ON at a time.

ONE FULL BRIDGE ON AT A TIME

10

I

A

I

OUT

8

6

PD [W]

4

I

B

I

OUT

Test Conditions:

2

Supply Voltage = 24V

No PWM

0

0 0.5 1 1.5 2 2.5 3

[A]

I

OUT

f

= 30 kHz (slow decay)

SW

Figure 13. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.

TWO FULL BRIDGES ON AT THE SAME TIME

10

8

6

PD [W]

4

2

0

00.511.522.53

I

[A]

OUT

I

A

I

B

I

OUT

I

OUT

Test Conditions:
Supply Voltage = 24V

No PWM

= 30 kHz (slow decay)

f

SW

THERMAL MANAGEMENT

In most applications the power di ssipation in the IC is t he m ain factor that sets the maximum current that can be de­liver by t he device in a safe operating con dit ion. Therefore, it has to be ta ken into account very carefully . Besides the
available space on t he PCB, the r ight package should be chosen considering the power dissipation. Heat sinking can
be achieved using copper on the PCB with proper area and thickness. Figures 15, 16 and 17 show the Junction-to­Ambient Thermal Resistance values for the PowerSO20, PowerDIP20 and SO20 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board
with 6cm

2

dissipating footprint (cop per thicknes s of 35µ m), the R

is about 35°C/W. Fig. 14 shows mount-

th j-amb

ing methods for this package. Using a multi- layer board wi th vias to a ground plane, thermal impedance can be
reduced down to 15°C/W.

12/18

Figure 14. Mounting the PowerSO pack age.

L6205

Slug soldered

to PCB with

dissipating area

Slug soldered

to PCB with

dissipating area

plus ground layer

Slug soldered to PCB with

dissipating area plus ground layer

contacted through via holes

Figure 15. PowerSO20 Junction -Am bient thermal resi stance versus on-bo ard co pper area.

ºC / W

43

38

33

28

23

18

13

12345678910111213

Without Ground Layer

With Ground Layer

With Ground Layer+16 via
Holes

sq. cm

On-Board Copper Area

Figure 16. PowerDIP20 Junction-Ambient thermal resistance versus on-board copper area.

ºC / W

49
48
47
46
45
44
43
42
41
40
39

1 2 3 4 5 6 7 8 9 101112

Copper Area is on Bottom
Side

Copper Area is on Top Side

sq . cm

On-Board Copper Area

Figure 17. SO20 Junction-Ambient thermal resi stance versus on-bo ard copp er area.

ºC / W

68
66
64
62
60

58
56
54
52
50
48

123456789101112

Copper Area is on Top Side

sq. cm

On-Board Copper Area

13/18

L6205

Figure 18. Typical Quiescent Current vs.

Supply Voltage

Iq [mA]

5.6

5.4

fsw = 1kHz Tj = 25°C

Tj = 85°C

Tj = 125°C

5.2

5.0

4.8

4.6
0 102030405060

V

[V]

S

Figure 19. Normalized Typical Quiescen t

Current vs. Switching Frequency

Iq / (Iq @ 1 kHz)

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9
0 20406080100

f

SW

[kHz]

Figure 21. Ty pi c al Hi gh-Side RDS( ON ) v s.

Supply Voltage

R

[Ω]

DS(ON)

0.380

0.376

0.372

0.368

0.364

0.360

0.356

0.352

0.348

0.344

0.340

0.336
0 5 10 15 20 25 30

Figure 22. Nor m ali ze d R

Tj = 25°C

V

[V]

S

DS(ON)

vs.Junction

Temperature (typical value)

/ (R

R

DS(ON)

1.8

1.6

1.4

1.2

1.0

0.8
0 20 40 60 80 100 120 140

DS(ON)

@ 25 °C)

Tj [°C]

Figure 20. Typical Low-Side R

DS(ON)

Voltage

R

[Ω]

DS(ON)

0.300

0.296

Tj = 25°C

0.292

0.288

0.284

0.280

0.276
0 5 10 15 20 25 30

14/18

VS [V]

vs. Supply

Figure 23. Typical Drain-Source Diode Forward

ON Characteristic

I

[A]

SD

3.0

2.5

2.0

1.5

1.0

0.5

0.0
700 800 900 1000 1100 1200 1300

Tj = 25°C

V

[mV]

SD

L6205

DIM.

MIN. TYP . MAX. MIN. TYP . MAX.

mm inch

A 3.6 0.142
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004

b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013

D (1) 15.8 16 0.622 0.630

D1 9.4 9.8 0.370 0.386

E 13.9 14.5 0.547 0.570

e 1.27 0.050

e3 11.43 0.450

E1 (1) 10.9 11.1 0.429 0.437

E2 2.9 0.114
E3 5.8 6.2 0.228 0.244

G 0 0.1 0.000 0.004

H 15.5 15.9 0.610 0.626

h 1.1 0.043

L 0.8 1.1 0.031 0.043
N 8˚ (typ.)
S 8˚ (max.)

T 10 0.394

(1) “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not exceed 0. 15mm (0.006”)

- Critical dimensions: “E”, “G” and “a3”.

OUTLINE AND

MECH AN ICAL DATA

Weight:

1.9gr

JEDEC MO-166

PowerSO20

E2

NN

a2

A

b

h x 45

DETAIL A

e3

H

D

T

110

e

1120

E1

DETAIL B

PSO20MEC

R

lead

a3

Gage Plane

BOTTOM VIEW

E

DETAIL B

0.35

S

D1

L

c

a1

DETAIL A

slug

- C -

SEATING PLANE

GC

(COPLANARITY)

E3

0056635

15/18

L6205

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 22.86 0.900

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130

Z 1.27 0.050

mm inch

OUTLINE AND

MECHANICAL DATA

Powerdip 20

16/18

L6205

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

K 0˚ (m in.)8˚ (m ax.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO20

B

e

D

1120

110

L

h x 45˚

A

K

A1

C

H

E

SO20MEC

17/18

L6205

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18/18

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