®
.
3.5A OUTP UT CURREN T
.
5.1V TO 40V OUTPUT VOLTAGE RAN GE
.
0 TO 90% DUTY CYCLE R A NG E
.
INTERNAL FEED-FORWA RD LINE REG .
.
INTERN AL CURRENT LIM IT ING
.
PRECISE 5.1V ± 2% ON CHIP REFERENCE
.
RESET AND POWER FAIL FUNCTIONS
.
INPUT/OUTPUT SYNC PIN
.
UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON
.
PWM LATCH F OR SING LE PULSE PER PERIOD
.
VERY HIGH EFFICIENCY
.
SWITCHING FREQ UE NC Y UP T O 200KHz
.
THERMAL SHUTDOWN
.
CONTINUOUS MODE OPER A TION
L4974A
3.5A SWITCHING REGULATOR
MULTIPOWER BCD TECHNOLOGY
POWERDIP
ORDERING NUMBE R :
(16 + 2 + 2)
L4974A
DESCRIPTION
The L4974A is a stepd own monolithic power swi tching regulator delivering 3.5A at a voltage variable
from 5.1 to 40V .
Realized with BCD mixed technology, the device
uses a DMOS output transistor to obtain very high
efficiency an d very fas t switchi ng times. F eatures of
BLOCK DIAGRAM
the L4974A include reset and power fail for microprocessors, feed forward line regulation, soft start,
limiting current and thermal protection. The device
is mounted in a Pow erdip 16 + 2 + 2 plastic package
and requires few external components. Efficient
operation at switching frequencies up to 200KHz
allows re duction i n the size and cost o f ex ternal filt er
component.
June 2000
This i s advanced informati on on a new pr oduct now in developm ent or under going eval uation. Det ails are s ubject to ch ange with out notice.
1/22
L4974A
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
11
V
11
V
20
I
20
V
I
, V
V
4
V
3
I
3
, V7, V9, V10Input Vol ta ge at Pin 2, 7, 9, 10 7 V
V
2
I
2
I
7
I
8
P
tot
, T
T
J
stg
Input Voltage 55 V
Input Operating Voltage 50 V
Output DC Vol ta ge
Output Pe ak Vol ta ge at t = 0.1µs f = 200khz
-1
-5
Maximum Output Current Internally Limited
Boostra p Vol ta ge
Boostra p Ope ra ting Vo lta ge
Input Vol ta ge at Pins 4, 12 12 V
8
65
+ 15
V
11
Reset Output Voltage 50 V
Reset Output Sink Current 50 mA
Reset Delay Sink Current 30 mA
Error Amplifier Output Sink Current 1 A
Soft Start Sink Current 30 mA
Total Power Dissipation at T
at T
≤ 90°C
PINS
= 70°C (No copper area on PCB)
amb
5
1.3
Junction and Storage Temperature -40 to 150 °C
V
V
V
V
W
W
PIN CONNECTION (t op v iew)
THERMAL DATA
Symbol Parameter Value Unit
R
th j-pins
R
th j-amb
Thermal Resistance Junction-Pins max
Thermal Resistance Junction-ambient max
12
60
°C/W
°C/W
2/22
L4974A
PIN FUNCTIONS
o
N
1 BOOTSTRAP A C
2 RESET DELAY A C
3 RESET OUT Open Col lec to r Re set /po wer Fai l Sig na l Ou tp ut. Thi s o utp ut i s hi gh whe n t he sup pl y
4 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider
5, 6
GROUND Common Ground Terminal
15, 16
7 FREQUENCY
COMPENSATION
8 SOFT START Soft Star t Time Cons tant. A capac itor i s conne cted b etween thi st ermin al and groun d
9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to
10 SYNC INPUT Multiple L4974A’s are synchronized by connecting pin 10 inputs together or via an
11 SUPPLY VOLTAGE Unregulated Input Voltage.
12, 19 N.C. Not Connected.
13 V
14 V
ref
start
17 OSCILLATOR R
18 OSCILLATOR C
20 OUTPUT Regulator Output.
Name Function
capacitor connected between this terminal and the output allows to drive
boot
properly the internal D-MOS transistor.
capacitor connected between this terminal and ground determines the reset
d
signal delay time.
and the outp ut vol tages are saf e.
to the i nput for power fa il funct ion. It m ust be con nected t o the pin 14 an e xternal 30K
resistor when power fail signal not required.
A series RC network connected between this terminal and ground determines the
regula tio n lo op ga in ch ara cte ri st ics .
to define the soft start time constant.
this terminal for 5.1V operation; It is connected via a divider for higher voltages.
external syncr. pulse.
5.1V V
Device Reference Voltage.
ref
Internal Start-up Circuit to Drive the Power Stage.
. Exte rn al re sis tor con ne cte d to gr oun d d ete rmi ne s t he constant chargin g cu rren t
osc
.
of C
osc
. External capacitor connected to ground determines (with R
osc
frequency.
) the switching
osc
Ω
3/22
L4974A
CIRCUIT OPERATION
The L4974A is a 3.5A monolithic stepdown switching regulat or working i n continuous mode re alized in
the new BCD Technology. This technology allows
the integration of isolated vertical DMO S power tran sistors plu s mix ed CMOS/Bipolar transisto rs .
The device c an deliver 3.5A at an output v oltage adjustable from 5.1V to 40V and contains diagnostic
and control functions that make it particularly suitable for microprocessor based systems.
BLOCK DIAGRAM
The block di agram show s the D MO S power tran -
sistors and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V
± 2%, soft star t, undervoltage lo ckout, osci llator with
feedforward control, pulse by pulse current limit,
thermal shutdown and finally the reset and power
fail circuit. The reset and power fail circuit provides
an output signal for a mic roproc ess or indic ating the
status of the system.
Device turn on is around 1 1V with a typic al 1V hysterysis, this t hr es ho ld porvides a c or re c t v olt ag e f or
the driving stage of the DMOS gate and the hysterysis prev ents ins t abi lit ie s.
An external b ootstrap capac itor charge t o 12V by an
internal voltage refere nc e i s needed to p ro vi de correct gate d ri ve to the power DM OS . T he dr iv ing circuit is able to source and sink peak currents of
around 0.5A to the gate of the DMOS transistor. A
typical switching time of the current in the DMOS
transistor is 50ns. Due to the fast commutation
switching f req uen ci es up t o 200 k Hz ar e pos s ible.
The PWM cont rol lo op consis ts of a sawtooth os cil lator, error am pl if ier , c om parator, latc h a nd the out put stage. An error sig nal is pr oduced by comparin g
the output voltag e with the precis e 5.1V ± 2% on chip
reference. This error signal is then compared with
the sawtooth oscillator in order to generate frixed
frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate
multiple pulsing within a period even in noisy environments.
The gain and stability of the loop can be adjusted by
an external RC netwo rk con nec t ed to the output of
the error amplifier. A voltage feedforward control
has been added to the osc ill at or , th is m ai nt ain s s uperior line regulation over a wide input voltage
range. Closin g the loo p dire ctly g ives an output vol tage of 5.1 V, higher voltages are obt ained by insert ing a voltage div id er.
At turn o n, output overcurr ents are prevented by t he
soft start function (fig. 2). The error amplifier is initially clam ped by an exter nal capacitor, Css, and allowed to ri se linearly under the c harge of an intern al
constant cur re nt so ur ce .
Output overl oad protection is pr ov ided by a current
limit circ uit. The lo ad cur rent is sensed by a in tern al
metal resistor connected to a comparator. Wh en the
load current ex ceeds a pr eset t hreshold , the out put
of the comparato r sets a flip flop wh ich turn s off the
power DM OS. The n ext clock pulse, fr om an in ternal
40kHz os cillator, wil l reset the f lip flop and th e power
DMOS will again conduct. This current protection
method, ens ures a constant cu rrent output when the
system is ove rloaded or short circui ted and limits the
switching f requency, in t his condition , to 40kHz. T he
Reset and Power fail circuit (fig. 4), generates an
output signal when the supply voltage exceeds a
threshold programmed by an external voltage divider. The reset signal, is generated with a delay
time program med by a external c apacitor on the delay pin. When the supply voltage falls below the
threshold or the outpu t voltage goes below 5V, the
reset outpu t goes low immedi ately. The res et output
is an open drai n.
Fig. 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage is
not yet 5V.
Fig. 4B sh ows the c ase whe n the outp ut is 5.1V , but
the supply voltage is not yet higher than the fixed
threshold.
The thermal protection disables circuit operation
when the junction temperature reaches about
150°C and has a hysterysis to prevent unstable
conditions.
4/22
Figure 1 : Feedforward Waveform.
Figure 2 : Soft Start Function.
L4974A
Figure 3 : Lim i ti ng Cu rr en t Fu nc t ion.
5/22
L4974A
Figure 4 : Rese t and P ower Fail Func tions .
A
B
6/22
L4974A
ELECTRICAL CHARACTERISTICS (refer to the test circuit, T
C
= 2.7nF, fSW = 100KHz ty p, unle s s otherwise specif i ed)
9
= 25°C , Vi = 35V, R4 = 30KΩ,
J
DYNAMIC C HA RA CTERISTICS
Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.
V
V
V
∆
V
∆
V
Input Volt. Range (pin 11) Vo = V
i
Output Voltage Vi =15V to 50V
o
Line Regulation VI = 15V to 50V
o
Load Regulation VO = V
o
Dropout Voltage between
d
Pin 11 and 20
I
20L
η
Max Limiting Current Vi = 15V to 50V
Efficiency Io = 3.5A, f = 100KHz
SVR Supply Voltage Ripple
Rejection
I
I
I
I
Io = 2A
I
V
V
V
V
f = 100Hz; V
to 40V
ref
= 3.5A (*)
o
= 2A; Vo = V
o
= 1A; Vo = V
o
= 2A to 3A
o
= 3.5A
o
= V
o
ref
= V
o
ref
= 12V
o
= 2VRMS; Io = 5A
i
ref
ref
Io = 1A to 3.5A
ref
to 40V
= V
o
ref
f Switc hi ng Frequ enc y 90 100 11 0 KHz 5
Vi Voltage Stability of
∆f/∆
= 15V to 45V 2 6 % 5
V
i
Switching
Frequency
f/T
∆
Temperature Stability of
j
Tj = 0 to 125°C 1 % 5
Switchi ng Fre qu enc y
f
max
Maximum Operating
Switchi ng Fre qu enc y
(*) Pulse testing with a low duty cycl e
Vo = V
I
R4 = 15K
ref
= 3.5A C9 = 2.2nF
o
Ω
15 50 V 5
55.15.2V 5
12 30 mV
825mV
410mV
0.25
0.45
0.4
0.7
V
4 4.75 5.5 A
80 85
90
%
%
56 60 dB 5
200 KHz 5
V
SECTION (pin 13)
ref
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V
13
V
∆
V
∆
V
∆
T
∆
Reference Voltage 5 5.1 5.2 V 7
Line Regulation Vi = 15V to 50V 10 25 mV 7
13
Load Regulation I13 = 0 to 1mA 20 40 mV 7
13
Average Temperature
13
Tj = 0°C to 125°C 0.4 mV/°C7
Coefficient Reference
Voltage
Short Circuit Current Limit V13 = 0 70 mA 7
SECTION (pin 15)
V
START
I
13 short
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V
14
V
∆
V
∆
I
14 short
Reference Voltage 11.4 12 12.6 V 7
Line Regulation Vi = 15 to 50V 0.6 1.4 V 7
14
Load Regulation I
14
Short Circuit Current Limit V
= 0 to 1mA 50 200 mV 7
14
= 0V 80 mA 7
15
7/22
L4974A
ELECTRICAL CHARACTERISTICS (c ontinued)
DC CHARAC T E RIS T ICS
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V
11on
V
11 Hyst
I
11Q
I
11OQ
I
20L
SOFT START (pin 8)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
I
8
V
ERROR AMPLIFIER
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V
7H
V
7L
I
7H
-I
7L
I
9
G
SVR Supply Voltage Rejection 15 < V
V
OS
RAMP GENERATOR (pin 18)
Turn-on Threshold 10 11 12 V 7A
Turn-off Hysteresys 1 V 7A
Quiesce nt Cur re nt V8 = 0; S1 = D 13 19 mA 7A
Operating Supply Current V8 = 0; S1 = B; S2 = B 16 23 mA 7A
Out Leak Current Vi = 55V; S3 = A; V8 = 0 2 mA 7A
Soft Start Source Current V8 = 3V; V9 = 0V 80 115 150
Output Saturation Voltage I8 = 20mA; V11 = 10V
8
= 200µA; V11 = 10V
I
8
High Level Out Voltage I7 = -100µA; S1 = C
= 4.7V
V
9
Low Level Out Voltage I7 = 100µA; S1 = C
= 5.3V;
V
9
6V7C
1
0.7
1.2 V 7C
Source Output Current V7 = 1V; V7 = 4.7V 100 150
Sink Output Current V7 = 6V; V9 = 5.3V 100 150
Input Bias Current S1 = B; RS = 10K
DC Open Loop Gain S1 = A; RS = 10
V
Input Offset Voltage RS = 50
Ω
Ω
< 50V 60 80 dB 7C
i
S1 = A 2 10 mV 7C
Ω
60 dB 7C
0.4 3
A7B
µ
V
V
A7C
µ
A7C
µ
A7C
µ
7B
7B
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
V
18
V
18
I
18
I
18
Ramp Valley S1 = B; S2 = B 1.2 1.5 V 7A
Ramp Peak S1 = B Vi = 15V
S2 = B V
= 45V
i
2.5
5.5
Min. Ramp Current S1 = A; I17 = 100µA 270 30 0
V
V
A7A
µ
Max. Ramp Current S1 = A; I17 = 1mA 2.4 2.7 mA 7A
SYNC FUNCTION (pin 10)
Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.
8/22
V
10
Low Input Voltage Vi = 15V to 50V; V8 = 0;
S1 = B; S2 = B; S4 = B
V
10
High Input voltage V8 = 0;
S1 = B; S2 = B; S4 = B
+I
10L
Sync Inp ut Curr ent with Low
Input Voltage
+I
10H
Input Current with High
V10 = V18 = 0.9V; S4 = B;
S1 = B; S2 = B
V10 = 2.5V 1.5 mA 7A
Input Voltage
V
10
t
W
Output Amplitude 4 5 V –
Output Pul se Wid th V
= 2.5V 0.3 0.5 0.8
thr
–0.3 0.9 V 7A
2.5 5.5 V 7A
0.4 mA 7A
s–
µ
7A
7A
L4974A
ELECTRICAL CHARACTERISTICS (continue d)
RESET AND POWER FAIL FUNCTIONS
Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.
V
9R
V
9F
V
2H
V
2L
I
2SO
I
2SI
V
3S
I
3
V
4R
V
4H
I
4
Rising Thereshold Voltage
(pin 9)
Falling Thereshold Voltage
(pin 9)
Vi = 15 to 50V
= 5.3V
V
4
Vi = 15 to 50V
= 5.3V
V
4
Delay High Threshold Volt. Vi = 15 to 50V
= 5.3V V9 = V
V
4
Delay Low Threshold Volt. Vi = 15 to 50V
= 4.7V V9 = V
V
4
13
13
V
ref
-130
4.77 Vref
4.95 5.1 5.25 V 7D
1 1.1 1.2 V 7D
Delay Source Current V4 = 5.3V; V2 = 3V 30 60 80
Delay Source Sink Current V4 = 4.7V; V2 = 3V 10 mA 7D
Output Saturation Voltage I3 = 15mA; S1 = B V4 = 4.7V 0.4 V 7D
Output Leak Current V3 = 50V; S1 = A 100
Rising Threshold Voltage V9 = V
13
4.955 5.1 5.25 V 7D
Hysteresis 0.4 0.5 0.6 V 7D
Input Bias Cur re nt 1 3
V
ref
-100
-200
V
ref
-80
V
ref
-160
V
mV
V
mV
A7D
µ
A7D
µ
A7D
µ
7D
7D
Figure 5 : Test and Evaluation B oar d Circuit.
TYPICAL P E RF ORMANCE S (using evaluation boar d) :
n = 83% (V
V
o RIPPLE
Line regulat ion = 12mV (V
Load regulat ion = 8mV (I
= 35V ; Vo = VREF ; Io = 3.5A ; fsw = 100KHz)
i
= 30mV (at 1A)
= 15 to 50V)
i
= 1 to 3.5A)
o
for componen t values Refer to the fig. 5 ( P ar t lis t).
9/22
L4974A
Figure 6a : Component Layout of fig .5 (1 : 1 s c ale) . E va lua ti on B oa rd A v ai lable
PART LIST
R1 = 30K
R
R
R
R
R
R
R
R
* C
** C
* 2 capacitors in parall el to increase input RMS current ca pability.
* * 3 capacitors in parallel to reduce total output ESR.
Ω
= 10K
Ω
2
= 15K
Ω
3
= 30K
Ω
4
= 22
Ω
5
= 4.7K
6
7
8
9
Ω
= see table A
= OPTION
= 4.7K
Ω
= C2 = 1000µF 63V EYF (ROE)
1
= C4 = C5 = C6 = 2,2µF 50V
C
3
= 390pF Film
C
7
= 22nF MKT 1837 (ERO)
C
8
= 2.7nF KP 1830 (ERO)
C
9
= 0.33µF Film
C
10
= 1nF
C
11
= C13 = C14 = 100µF 40V EKR (ROE)
12
= 1µF Film
C
15
D1 = SB 560 (OR EQUIVALENT)
L1 = 150µH
core 58310 MAGNETICS
45 TURNS 0.91mm (A WG 19)
COGEMA 949181
Table A
V
12V
15V
18V
24V
0
R
4.7k
4.7k
4.7k
4.7k
9
Ω
Ω
Ω
Ω
R
6.2kW
9.1k
12
18
Table B
SUGGESTED BOOSTRAP CAPACITORS
Operating Frequency Boostrap Cap.c10
f = 20KHz
f = 50KHz
f = 100KHz
f = 200KHz
f = 500KHz
680nF
≥
470nF
≥
330nF
≥
220nF
≥
100nF
≥
7
Ω
Ω
Ω
10/22
Figure 6b: P.C. Board and Component Layout of the Circuit of Fig. 5. (1:1 scale)
L4974A
Figure 7 : DC Tes t Cir c uits .
11/22
L4974A
Figure 7A.
Figure 7B.
Figure 7C.
12/22
Figure 7D.
L4974A
Figure 8 : Quiescent Drain Cur r ent v s. S upp ly
Voltage (0% duty cy c le - s ee fig. 7A ) .
Figure 9 : Quiescent D rai n Current vs. Jun ctio n
Temperature (0% duty cycle).
13/22
L4974A
Figure 10 : Quies c ent Drain Current v s . Dut y Cy -
cle.
Figure 12 : Refer enc e V ol ta ge ( pin 13) vs . Ju nc tion Temperatur e (s ee fi g. 7).
Figure 11 : Reference Vo lt age (pi n 13) v s. V i
(see fig. 7).
Figure 13 : Reference V olt age (p in 14) v s. V i
(see fig. 7).
Figure 14 : R efer enc e V oltage (pin 14) vs . Ju nc tion Temperatur e (s ee fi g. 7).
14/22
Figure 15 : Reference Vo lt age 5. 1V (pi n 13) S up ply Voltage Ripple Rejection vs. Fre-
SVR
(dB)
L4974A
Figure 16 : Swit ch ing F req uen cy v s . Inp ut Vo lt age
(see fig. 5).
Figure 18 : Swit ch ing F req uen cy v s . R4
(see fig.5).
Figure 17 : Switching Frequency vs. Junction
Temperature (see fig. 5).
Figure 19 : Maximum Dut y Cy c le v s . Frequency.
Figure 20 : Supply Voltage Ripple Reject ion v s .
Frequency (see fig. 5).
Figure 21 : Efficiency vs. Output Voltage.
15/22
L4974A
Figure 22 : Line Tr ans i ent Res p ons e ( se e f ig. 5) . Figure 23 : Load Transient Re s pons e (s ee fig. 5).
Figure 24 : Dropout Volt ag e bet we en P in 11 and
Pin 20 vs. Current at Pin 20.
Figure 26 : Power Dis si pation (device on ly ) vs .
Input Voltage.
Figure 25 : .Dr op out V oltage between Pi n 11 an d
Pin 20 vs. Junction Temperature.
Figure 27 : P ow er Dis s ipation (device o nly ) vs .
Input Voltage.
16/22
L4974A
Figure 28 : Power Dis s ipation (device only ) vs .
Output Voltage.
Figure 30 : Power Dis s ipation (device only ) vs .
Output Current.
Figure 29 : Power Dissipation (devic e only) vs.
Output Voltage.
Figure 31 : Power Dis si pation (device onl y ) vs .
Output Current.
Figure 32 : Efficiency vs. Output Current. Figure 33 : Test PCB Thermal Characteristic.
17/22
L4974A
Figure 34 : Junction to Ambient Thermal Resistance
vs . Area on Board He atsink (DIP 16+2+2)
Figure 36: Open Loop Frequency and Phase of Er-
ror Amplifier (see fig. 7 C).
Figure 35: Maximum Allowable Power Dissipa-
tion vs. Ambient Temperature (Powerdip)
18/22
Figure 37 : 3.5A – 5.1V Low Cost Applica t ion C ir cu it .
L4974A
Figure 38 : A 5.1V/ 12 V Mul t iple Su pply. Note the Sy nc hr oniz a ti on be tw een th e L49 74A and L4970A.
19/22
L4974A
Figure 39 : L4974A’s Sync. Example.
Figure 40: 1A/24V Multiple Supply. Note t he synchronization between the L4974A and L4962
20/22
L4974A
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.85 1.40 0.033 0.055
b 0.50 0.020
b1 0.38 0.50 0.015 0.020
D 24.80 0.976
E 8.80 0.346
e 2.54 0.100
e3 22.86 0.900
F 7.10 0.280
I 5.10 0.201
L 3.30 0.130
Z 1.27 0.050
mm inch
OUTLINE AND
MECHANICAL DATA
Powerdip 20
21/22
L4974A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of us e of such inform ation nor for any infringement of patent s or other right s of third parties whic h may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicr oelectronic s.
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22/22
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