STMicroelectronics L4974A User Manual

®

.

3.5A OUTP UT CURREN T

.

5.1V TO 40V OUTPUT VOLTAGE RAN GE

.

0 TO 90% DUTY CYCLE R A NG E

.

INTERNAL FEED-FORWA RD LINE REG .

.

INTERN AL CURRENT LIM IT ING

.

PRECISE 5.1V ± 2% ON CHIP REFERENCE

.

RESET AND POWER FAIL FUNCTIONS

.

INPUT/OUTPUT SYNC PIN

.

UNDER VOLTAGE LOCK OUT WITH HYS­TERETIC TURN-ON

.

PWM LATCH F OR SING LE PULSE PER PE­RIOD

.

VERY HIGH EFFICIENCY

.

SWITCHING FREQ UE NC Y UP T O 200KHz

.

THERMAL SHUTDOWN

.

CONTINUOUS MODE OPER A TION

L4974A

3.5A SWITCHING REGULATOR

MULTIPOWER BCD TECHNOLOGY

POWERDIP

ORDERING NUMBE R :

(16 + 2 + 2)

L4974A

DESCRIPTION

The L4974A is a stepd own monolithic power swi tch­ing regulator delivering 3.5A at a voltage variable
from 5.1 to 40V .

Realized with BCD mixed technology, the device
uses a DMOS output transistor to obtain very high
efficiency an d very fas t switchi ng times. F eatures of

BLOCK DIAGRAM

the L4974A include reset and power fail for micro­processors, feed forward line regulation, soft start,
limiting current and thermal protection. The device
is mounted in a Pow erdip 16 + 2 + 2 plastic package
and requires few external components. Efficient
operation at switching frequencies up to 200KHz
allows re duction i n the size and cost o f ex ternal filt er
component.

June 2000

This i s advanced informati on on a new pr oduct now in developm ent or under going eval uation. Det ails are s ubject to ch ange with out notice.

1/22

L4974A

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

11

V

11

V

20

I

20

V

I

, V

V

4

V

3

I

3

, V7, V9, V10Input Vol ta ge at Pin 2, 7, 9, 10 7 V

V

2

I

2

I

7

I

8

P

tot

, T

T

J

stg

Input Voltage 55 V
Input Operating Voltage 50 V
Output DC Vol ta ge

Output Pe ak Vol ta ge at t = 0.1µs f = 200khz

-1

-5
Maximum Output Current Internally Limited
Boostra p Vol ta ge

Boostra p Ope ra ting Vo lta ge
Input Vol ta ge at Pins 4, 12 12 V

8

65

+ 15

V

11

Reset Output Voltage 50 V
Reset Output Sink Current 50 mA

Reset Delay Sink Current 30 mA
Error Amplifier Output Sink Current 1 A
Soft Start Sink Current 30 mA
Total Power Dissipation at T

at T

≤ 90°C

PINS

= 70°C (No copper area on PCB)

amb

5

1.3

Junction and Storage Temperature -40 to 150 °C

V
V

V
V

W
W

PIN CONNECTION (t op v iew)

THERMAL DATA

Symbol Parameter Value Unit

R

th j-pins

R

th j-amb

Thermal Resistance Junction-Pins max
Thermal Resistance Junction-ambient max

12
60

°C/W
°C/W

2/22

L4974A

PIN FUNCTIONS

o

N

1 BOOTSTRAP A C

2 RESET DELAY A C

3 RESET OUT Open Col lec to r Re set /po wer Fai l Sig na l Ou tp ut. Thi s o utp ut i s hi gh whe n t he sup pl y

4 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider

5, 6

GROUND Common Ground Terminal

15, 16

7 FREQUENCY

COMPENSATION

8 SOFT START Soft Star t Time Cons tant. A capac itor i s conne cted b etween thi st ermin al and groun d

9 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to

10 SYNC INPUT Multiple L4974A’s are synchronized by connecting pin 10 inputs together or via an

11 SUPPLY VOLTAGE Unregulated Input Voltage.

12, 19 N.C. Not Connected.

13 V
14 V

ref
start

17 OSCILLATOR R

18 OSCILLATOR C

20 OUTPUT Regulator Output.

Name Function

capacitor connected between this terminal and the output allows to drive

boot

properly the internal D-MOS transistor.

capacitor connected between this terminal and ground determines the reset

d

signal delay time.

and the outp ut vol tages are saf e.

to the i nput for power fa il funct ion. It m ust be con nected t o the pin 14 an e xternal 30K
resistor when power fail signal not required.

A series RC network connected between this terminal and ground determines the
regula tio n lo op ga in ch ara cte ri st ics .

to define the soft start time constant.

this terminal for 5.1V operation; It is connected via a divider for higher voltages.

external syncr. pulse.

5.1V V

Device Reference Voltage.

ref

Internal Start-up Circuit to Drive the Power Stage.

. Exte rn al re sis tor con ne cte d to gr oun d d ete rmi ne s t he constant chargin g cu rren t

osc

.

of C

osc

. External capacitor connected to ground determines (with R

osc

frequency.

) the switching

osc

Ω

3/22

L4974A

CIRCUIT OPERATION

The L4974A is a 3.5A monolithic stepdown switch­ing regulat or working i n continuous mode re alized in
the new BCD Technology. This technology allows
the integration of isolated vertical DMO S power tran ­sistors plu s mix ed CMOS/Bipolar transisto rs .

The device c an deliver 3.5A at an output v oltage ad­justable from 5.1V to 40V and contains diagnostic
and control functions that make it particularly suit­able for microprocessor based systems.

BLOCK DIAGRAM
The block di agram show s the D MO S power tran -

sistors and the PWM control loop. Integrated func­tions include a reference voltage trimmed to 5.1V
± 2%, soft star t, undervoltage lo ckout, osci llator with
feedforward control, pulse by pulse current limit,
thermal shutdown and finally the reset and power
fail circuit. The reset and power fail circuit provides
an output signal for a mic roproc ess or indic ating the
status of the system.

Device turn on is around 1 1V with a typic al 1V hys­terysis, this t hr es ho ld porvides a c or re c t v olt ag e f or
the driving stage of the DMOS gate and the hyste­rysis prev ents ins t abi lit ie s.

An external b ootstrap capac itor charge t o 12V by an
internal voltage refere nc e i s needed to p ro vi de cor­rect gate d ri ve to the power DM OS . T he dr iv ing cir­cuit is able to source and sink peak currents of
around 0.5A to the gate of the DMOS transistor. A
typical switching time of the current in the DMOS
transistor is 50ns. Due to the fast commutation
switching f req uen ci es up t o 200 k Hz ar e pos s ible.

The PWM cont rol lo op consis ts of a sawtooth os cil ­lator, error am pl if ier , c om parator, latc h a nd the out ­put stage. An error sig nal is pr oduced by comparin g
the output voltag e with the precis e 5.1V ± 2% on chip
reference. This error signal is then compared with
the sawtooth oscillator in order to generate frixed
frequency pulse width modulated drive for the out­put stage. A PWM latch is included to eliminate
multiple pulsing within a period even in noisy envi­ronments.

The gain and stability of the loop can be adjusted by

an external RC netwo rk con nec t ed to the output of
the error amplifier. A voltage feedforward control
has been added to the osc ill at or , th is m ai nt ain s s u­perior line regulation over a wide input voltage
range. Closin g the loo p dire ctly g ives an output vol ­tage of 5.1 V, higher voltages are obt ained by insert ­ing a voltage div id er.

At turn o n, output overcurr ents are prevented by t he
soft start function (fig. 2). The error amplifier is in­itially clam ped by an exter nal capacitor, Css, and al­lowed to ri se linearly under the c harge of an intern al
constant cur re nt so ur ce .

Output overl oad protection is pr ov ided by a current
limit circ uit. The lo ad cur rent is sensed by a in tern al
metal resistor connected to a comparator. Wh en the
load current ex ceeds a pr eset t hreshold , the out put
of the comparato r sets a flip flop wh ich turn s off the
power DM OS. The n ext clock pulse, fr om an in ternal
40kHz os cillator, wil l reset the f lip flop and th e power
DMOS will again conduct. This current protection
method, ens ures a constant cu rrent output when the
system is ove rloaded or short circui ted and limits the
switching f requency, in t his condition , to 40kHz. T he
Reset and Power fail circuit (fig. 4), generates an
output signal when the supply voltage exceeds a
threshold programmed by an external voltage di­vider. The reset signal, is generated with a delay
time program med by a external c apacitor on the de­lay pin. When the supply voltage falls below the
threshold or the outpu t voltage goes below 5V, the
reset outpu t goes low immedi ately. The res et output
is an open drai n.

Fig. 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage is
not yet 5V.

Fig. 4B sh ows the c ase whe n the outp ut is 5.1V , but
the supply voltage is not yet higher than the fixed
threshold.

The thermal protection disables circuit operation
when the junction temperature reaches about
150°C and has a hysterysis to prevent unstable
conditions.

4/22

Figure 1 : Feedforward Waveform.

Figure 2 : Soft Start Function.

L4974A

Figure 3 : Lim i ti ng Cu rr en t Fu nc t ion.

5/22

L4974A

Figure 4 : Rese t and P ower Fail Func tions .
A

B

6/22

L4974A

ELECTRICAL CHARACTERISTICS (refer to the test circuit, T

C

= 2.7nF, fSW = 100KHz ty p, unle s s otherwise specif i ed)

9

= 25°C , Vi = 35V, R4 = 30KΩ,

J

DYNAMIC C HA RA CTERISTICS

Symbol Parameter Test Conditions Min. Typ. Max. Unit Fig.

V

V

V

∆

V

∆

V

Input Volt. Range (pin 11) Vo = V

i

Output Voltage Vi =15V to 50V

o

Line Regulation VI = 15V to 50V

o

Load Regulation VO = V

o

Dropout Voltage between

d

Pin 11 and 20

I

20L

η

Max Limiting Current Vi = 15V to 50V

Efficiency Io = 3.5A, f = 100KHz

SVR Supply Voltage Ripple

Rejection

I

I

I

I
Io = 2A

I

V

V
V

V
f = 100Hz; V

to 40V

ref

= 3.5A (*)

o

= 2A; Vo = V

o

= 1A; Vo = V

o

= 2A to 3A

o

= 3.5A

o

= V

o

ref

= V

o

ref

= 12V

o

= 2VRMS; Io = 5A

i

ref

ref

Io = 1A to 3.5A

ref

to 40V

= V

o

ref

f Switc hi ng Frequ enc y 90 100 11 0 KHz 5

Vi Voltage Stability of

∆f/∆

= 15V to 45V 2 6 % 5

V

i

Switching
Frequency

f/T

∆

Temperature Stability of

j

Tj = 0 to 125°C 1 % 5

Switchi ng Fre qu enc y

f

max

Maximum Operating
Switchi ng Fre qu enc y

(*) Pulse testing with a low duty cycl e

Vo = V
I

R4 = 15K

ref

= 3.5A C9 = 2.2nF

o

Ω

15 50 V 5

55.15.2V 5

12 30 mV

825mV
410mV

0.25

0.45

0.4

0.7

V

4 4.75 5.5 A

80 85

90

%
%

56 60 dB 5

200 KHz 5

V

SECTION (pin 13)

ref

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V

13

V

∆

V

∆

V

∆

T

∆

Reference Voltage 5 5.1 5.2 V 7
Line Regulation Vi = 15V to 50V 10 25 mV 7

13

Load Regulation I13 = 0 to 1mA 20 40 mV 7

13

Average Temperature

13

Tj = 0°C to 125°C 0.4 mV/°C7
Coefficient Reference
Voltage

Short Circuit Current Limit V13 = 0 70 mA 7

SECTION (pin 15)

V

START

I

13 short

Symbol Parameter Test Condition Min. Typ. Max. Unit Fig.

V

14

V

∆

V

∆

I

14 short

Reference Voltage 11.4 12 12.6 V 7
Line Regulation Vi = 15 to 50V 0.6 1.4 V 7

14

Load Regulation I

14

Short Circuit Current Limit V

= 0 to 1mA 50 200 mV 7

14

= 0V 80 mA 7

15

7/22