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VNQ5160K-E
Datasheet (ST)
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Datasheet VNQ5160K-E Datasheet (ST)

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Features
VNQ5160K-E
Quad channel high side driver for automotive applications
Max transient supply voltage V
Operating voltage range V
Max on-state resistance (per ch.) R
Current limitation (typ) I
Off-state supply current I
1. Typical value with all loads connected
■ General features
– Inrush current active management by
European directive
■ Diagnostic functions
– Open drain status output – On-state open-load detection – Off-state open-load detection – Thermal shutdown indication
■ Protection
– Undervoltage shutdown – Overvoltage clamp – Output stuck to V – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of V – Thermal shut down – Reverse battery protection (see Application
schematic on page 18

Table 1. Device summary

Package
detection
CC
CC
CC
ON
LIMH
S
41V
4.5 to 36 V
160 mΩ
5.4 A
(1)
2 μA
PowerSSO-24
– Electrostatic discharge protection
Applications
■ All types of resistive, inductive and capacitive
loads
Description
The VNQ5160K-E is a monolithic device made using STMicroelectronics VIPower™ M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V device against low energy spikes (see ISO7637 transient compatibility table).
The device detects open-load condition in both on and off states, when STAT_DIS is left open or driven low. Output shorted to V the off-state. When STAT_DIS is driven high, the STATUS pin is in a high impedance condition.
Output current limitation protects the device in overload condition. In the case of long duration overload, the device limits the dissipated power to a safe level up to thermal shutdown intervention.
CC
Thermal shutdown with automatic restart allows the device to recover normal operation as soon as a fault condition disappears.
Order codes
Tub e Tap e a nd reel
pin voltage clamp protects the
CC
CC
is detected in
PowerSSO-24 VNQ5160K-E VNQ5160KTR-E
July 2009 Doc ID 13349 Rev 6 1/30
www.st.com
1
Contents VNQ5160K-E
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18
3.1.1 Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . 18
3.1.2 Solution 2: a diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . 19
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 22
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30 Doc ID 13349 Rev 6
VNQ5160K-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Status pin (V
Table 9. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 14. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SD
Doc ID 13349 Rev 6 3/30
List of figures VNQ5160K-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. On-state resistance vs T Figure 16. On-state resistance vs V
Figure 17. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. I
LIMH
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
case
Figure 23. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. High-level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 26. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 22
Figure 31. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 23
Figure 33. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 24
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-24
Figure 35. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 36. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 37. Tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
(1)
. . . . . . . . . . . . . . . . . 24
4/30 Doc ID 13349 Rev 6
VNQ5160K-E Block diagram and pin configuration

1 Block diagram and pin configuration

Figure 1. Block diagram

V
CC
V
GND
INPUT1
STATUS1
STAT_DIS
INPUT2
STATUS2
CC
clamp
Overtemp 1
Logic
Undervoltage
Clamp 1
Driver 1
Current limiter 1
Openload on 1
V
DS,
INPUT3
STATUS3
INPUT4
Openload off 1
PWR
LIM
1
STATUS4

Table 2. Pin functions

Name Function
V
CC
Battery connection
OUTPUTn Power output
GND
INPUTn
Ground connection. Must be reverse battery protected by an external diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
LIM
Control & protection Identical to channel 1
Control & protection Identical to channel 1
Control & protection Identical to channel 1
OUTPUT1
V
CC
OUTPUT2
V
CC
OUTPUT3
V
CC
OUTPUT4
STATUSn Open drain digital diagnostic pin
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin
Doc ID 13349 Rev 6 5/30
Block diagram and pin configuration VNQ5160K-E

Figure 2. Configuration diagram (top view)

V
CC
GND
INPUT1
STATUS1
INPUT2
STATUS2
INPUT3
STATUS3
INPUT4
STATUS4
STAT_DIS
V
CC

Table 3. Suggested connections for unused and not connected pins

1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4
TAB = V
CC
Connection / Pin Status N.C. Output Input STAT_DIS
Floating X X X X X
To ground N.R.
1. Not recommended
(1)
XN.R.
Through 10 kΩ
resistor
Through 10 kΩ
resistor
6/30 Doc ID 13349 Rev 6
VNQ5160K-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I
Fn
S
V
CC
V
CC
V
I
SD
V
Note: VFn = V
OUTn
- V
SD
CCn
I
INn
V
INn
during reverse battery condition

2.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit
V
- V
- I
I
OUT
- I
I
STAT
I
STAT_DIS
E
V
V
DC supply voltage 41 V
CC
Reverse DC supply voltage 0.3 V
CC
DC reverse ground pin current 200 mA
GND
DC output current Internally limited A
Reverse DC output current 6 A
OUT
DC input current +10 / -1 mA
I
IN
DC status current +10 / -1 mA
DC status disable current +10 / -1 mA
Maximum switching energy (single pulse)
MAX
(L=12mH; RL=0Ω; V
Electrostatic discharge (Human Body Model: R=1.5KΩ; C=100pF)
– Input – Status
ESD
–STAT_DIS – Output –V
CC
Charge device model (CDM-AEC-Q100-011) 750 V
ESD
=13.5V; T
bat
INPUTn
jstart
OUTPUTnSTAT_DIS
STATUSn
GND
I
GND
=150ºC; I
OUT
= I
I
OUTn
I
limL
STATn
V
STATn
(Typ.) )
V
OUTn
33 mJ
4000 4000 4000 5000 5000
V V V V V
Doc ID 13349 Rev 6 7/30
Electrical specifications VNQ5160K-E
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
T
Junction operating temperature -40 to 150 °C
j
T
Storage temperature - 55 to 150 °C
stg

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max. value Unit
R
thj-case
R
thj-amb
Thermal resistance junction-case (with one channel on)
Thermal resistance junction-ambient See Figure 32. °C/W

2.3 Electrical characteristics

8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
USDhyst
R
V
clamp
I
L(off1)
I
L(off2)
Operating supply voltage 4.5 13 36 V
CC
Undervoltage shutdown 3.5 4.5 V
USD
Undervoltage shutdown hysteresis
I
OUT
I
OUT
I
OUT
On-state resistance
ON
(1)
Clamp voltage IS=20 mA 41 46 52 V
Off-state; VCC=13V; VIN=V T
I
Supply current
S
Off-state output current
Off-state output current
Output - VCC diode
V
F
voltage
(1)
j
On-state; V I
OUT
VIN=V
(1)
VIN=V
(1)
VIN=0V; V
-I
OUT
8°C/W
0.5 V
=1A; Tj=25°C =1A; Tj=150°C =1A; VCC=5V; Tj=25°C
=25°C
=5V; VCC=13V;
IN
=0A
=0V; VCC=13V; Tj=25°C
OUT
=0V; VCC=13V; Tj=125°C
OUT
=4V -75 0 μA
OUT
OUT
=0V;
000.01 35μA
160 320 210
(2)
2
5
8
=0.6A; Tj=150°C 0.7 V
mΩ mΩ mΩ
(2)
14μAmA
μA
1. For each channel.
2. PowerMOS leakage included.
8/30 Doc ID 13349 Rev 6
VNQ5160K-E Electrical specifications
Table 7. Switching (VCC=13V; Tj= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
dV
/dt
OUT
/dt
dV
OUT
W
ON
W
OFF

Table 8. Status pin (VSD=0)

Turn-on delay time RL=13Ω (see Figure 6.)15μs
Turn-off delay time RL=13Ω (see Figure 6.)15μs
Turn-on voltage
(on)
slope
Turn-off voltage
(off)
slope
Switching energy losses during t
Switching energy losses during
t
=13Ω
R
L
R
=13Ω
L
RL=13Ω (see Figure 6.)0.05mJ
won
RL=13Ω (see Figure 6.)0.03mJ
woff
See
Figure 6.
See
Figure 6.
Symbol Parameter Test conditions Min Typ Max Unit
V
STAT
I
LSTAT
C
STAT
V
SCL
Status low output voltage
Status leakage current
Status pin input capacitance
Status clamp voltage
I
= 1.6 mA, VSD=0V 0.5 V
STAT
Normal operation or V V
= 5V
STAT
SD
=5V,
Normal operation or VSD=5V,
= 5V
V
STAT
I
STAT
I
STAT
= 1mA = -1mA
5.5
-0.7
10 μA
100 pF
7V
V/μs
V/μs
V

Table 9. Protection

(1)
Symbol Parameter Test conditions Min. Typ. Max. Unit
=13V
I
limH
I
T
T
T
HYST
t
SDL
DC Short circuit current
Short circuit current
limL
during thermal cycling
Shutdown
TSD
temperature
Reset temperature TRS + 1 TRS + 5 °C
T
R
Thermal reset of
RS
STATUS
Thermal hysteresis
TSD-TR
)
(T
Status delay in overload conditions
V
CC
5V<VCC<36V
=13V
V
CC
TR<Tj<T
T
TSD
(See Figure 4.) 20 μs
j>TTSD
3.8 5.4 7.5
7.5
2A
150 175 200 °C
135 °C
7°C
A A
Doc ID 13349 Rev 6 9/30
Electrical specifications VNQ5160K-E
Table 9. Protection
(1)
(continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
DEMAG
V
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles

Table 10. Open-load detection

Turn-off output voltage clamp
Output voltage drop
ON
limitation
=1A; VIN=0; L=20mH VCC-41 VCC-46 VCC-52 V
I
OUT
I
=0.03A (see Figure 5.)
OUT
= -40°C...+150°C
T
j
25 mV
Symbol Parameter Test conditions Min Typ Max Unit
See
Figure
18.
40 mA
200 μs
I
OL
t
DOL(on)
Open-load on-state detection threshold
Open-load on-state detection delay
= 5V ,8V<VCC<18V 10
V
IN
= 0A, VCC=13V
I
OUT
(See Figure 4.)
Delay between INPUT
t
POL
falling edge and STATUS rising edge in
= 0A (See Figure 4.) 200 500 1000 μs
I
OUT
Open-load condition
Open-load OFF-state
V
voltage detection
OL
VIN = 0V, 8V<VCC<16V 2
threshold
See
Figure
19.
4V
Output short circuit to
t
DSTKON
Vcc detection delay at
(See Figure 4.)180t
POL
turn-off
μs

Table 11. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
I(hyst)
V
V
I
SDL
V
Input low level 0.9 V
IL
Low level input current VIN = 0.9V 1 μA
I
IL
Input high level 2.1 V
IH
I
High level input current VIN = 2.1V 10 μA
IH
Input hysteresis voltage 0.25 V
Input clamp voltage
ICL
STAT_DIS low level
SDL
voltage
Low level STAT_DIS current
STAT_DIS high level
SDH
voltage
IIN = 1mA IIN = -1mA
V
10/30 Doc ID 13349 Rev 6
5.5
-0.7
7V
0.9 V
=0.9V 1 μA
SD
2.1 V
V
VNQ5160K-E Electrical specifications
Table 11. Logic input (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SDH
V
SD(hyst)
V
SDCL
High level STAT_DIS current
STAT_DIS hysteresis voltage
STAT_DIS clamp voltage

Figure 4. Status timings

OPEN LOAD STATUS TIMING (without external pull-up)
I
< I
OUT
I
OUT
> I
OL
V
OL
V
V
V
V
IN
STAT
IN
t
DOL(on)
OUTPUT STUCK TO Vcc
=2.1V 10 μA
V
SD
0.25 V
ISD=1mA ISD=-1mA
< V
OUT
t
POL
> V
OUT
OPEN LOAD STATUS TIMING (with external pull-up)
V
V
IN
STAT
t
DOL(on)
OL
OVER TEMP STATUS TIMING
V
OL
IN
I
OUT
5.5
< I
Tj > T
-0.7
OL
TSD
7V
V
V
> V
OUT
OL
V
STAT
t
DOL(on)
t
DSTKON
V
STAT
t
SDL
t
SDL

Figure 5. Output voltage drop limitation

Vcc-V
out
Tj=150oC
V
on
V
on/Ron(T)
=25oC
T
j
=-40oC
T
j
I
out
Doc ID 13349 Rev 6 11/30
Electrical specifications VNQ5160K-E

Table 12. Truth table

Conditions INPUTn OUTPUTn STATUSn (VSD=0V)
(1)
Normal operation
Current limitation
Overtemperature
Undervoltage
Output voltage > V
Output current < I
OL
OL
L
H
L
H
L
H
L
H
L
H
L
H
1. If the VSD is high, the STATUS pin is in a high impedance.
2. The STATUS pin is low with a delay equal to t
3. The STATUS pin becomes high with a delay equal to t
after INPUT falling edge.
DSTKON
POL

Figure 6. Switching characteristics

V
OUT
t
Won
80%
L
H
L
X
L L
L L
H H
L
H
after INPUT falling edge.
t
Woff
90%
H H
H H
H
L
X X
(2)
L
H
(3)
H
L
dV
dV
/dt
OUT
(on)
t
r
INPUT
t
d(on)
10%
t
d(off)
t
f
OUT
/dt
(off)
t
t
12/30 Doc ID 13349 Rev 6
VNQ5160K-E Electrical specifications

Table 13. Electrical transient requirements (part 1/3)

ISO 7637-2:
2004(E)
Test pu l s e
Test levels
III IV
(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and Impedance
1 -75 V -100 V
2a +37 V +50 V
5000
pulses
5000
pulses
0.5 s 5 s 2 ms, 10 Ω
0.2 s 5 s 50 μs, 2 Ω
3a -100 V -150 V 1h 90 ms 100 ms 0.1 μs, 50 Ω
3b +75 V +100 V 1h 90 ms 100 ms 0.1 μs, 50 Ω
4 -6 V -7 V 1 pulse 100 ms, 0.01
(1)
5b
+65 V +87 V 1 pulse 400 ms, 2 Ω
1. Valid in case of external load dump clamp: 40V maximum referred to ground.

Table 14. Electrical transient requirements (part 2/3)

ISO 7637-2:
Test level results
(1)
2004(E)
Test pulse
III IV
1C C
2a C C
3a C C
3b C C
4C C
(2)
5b
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Ω

Table 15. Electrical transient requirements (part 3/3)

Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 13349 Rev 6 13/30
Electrical specifications VNQ5160K-E

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current
Iloff1 (uA)
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
-50 -25 0 25 50 75 100 125 150 175
Off state Vcc=13V
Vin=Vout=0V
Tc ( °C )
Iih (uA)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Vin=2.1V
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)

Figure 9. Input clamp voltage Figure 10. Input low level voltage

Vicl (V)
8
7.75
7.5
7.25
7
Iin=1mA
Vil (V)
4
3.5
3
2.5
2
6.75
6.5
6.25
6
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)

Figure 11. Input high level voltage Figure 12. Input hysteresis voltage

Vih (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
Vihyst (V)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
14/30 Doc ID 13349 Rev 6
VNQ5160K-E Electrical specifications

Figure 13. Status low output voltage Figure 14. Status leakage current

Vstat (V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Istat=1.6mA
0
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
Figure 15. On-state resistance vs T
Ron (mOhm)
250
225
200
175
150
125
100
75
50
25
0
Iout=1A
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
case
Ilstat (uA)
0.06
0.055
Vstat=5V
0.05
0.045
0.04
0.035
0.03
0.025
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C)
Figure 16. On-state resistance vs V
Ron (mOhm)
250
225
200
175
150
125
100
75
50
25
0
0 5 10 15 20 25 30 35 40
Vcc (V)
Tc=150°C
Tc=125°C
Tc=25°C
Tc=-40°C
CC

Figure 17. Status clamp voltage Figure 18. Open-load on-state detection

threshold
Vscl (V)
9
8.5
7.5
6.5
5.5
4.5
Istat=1mA
8
7
6
5
4
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
Doc ID 13349 Rev 6 15/30
Iol (mA)
100
90
80
70
60
50
40
30
20
10
0
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tc ( ° C)
Electrical specifications VNQ5160K-E
Figure 19. Open-load off-state voltage

Figure 20. Undervoltage shutdown

detection threshold
Vol (V)
5
4.5
4
3.5
3
2.5
2
1.5
1
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
Vusd (V)
14
12
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175

Figure 21. Turn-on voltage slope Figure 22. I

dVout/dt(on) (V/ms)
1000
900
800
700
600
500
400
300
200
100
Vcc=13V
Ri=6.5Ohm
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Ilimh (A)
10
9
8
7
6
5
4
3
2
1
0
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
LIMH
vs T
Tc ( °C )
case
Tc ( °C )

Figure 23. Turn-off voltage slope Figure 24. High-level STAT_DIS voltage

dVout/dt(off) (V/ms)
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
16/30 Doc ID 13349 Rev 6
Vcc=13V
Ri=13Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Vsdh (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
VNQ5160K-E Electrical specifications

Figure 25. STAT_DIS clamp voltage Figure 26. Low level STAT_DIS voltage

Vsdcl (V)
14
12
Isd=1mA
10
8
6
4
2
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Vsdl (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc ( °C )
Doc ID 13349 Rev 6 17/30
Application information VNQ5160K-E

3 Application information

Figure 27. Application schematic

+5V
μ
R
R
C
R
prot
prot
prot
+5V
STAT_DIS
INPUT
STATUS
V
CC
OUTPUT
GND
R
GND
GND
D
GND
V
Note: Channels 2, 3 and 4 have the same internal circuit as channel 1.

3.1 GND protection network against reverse battery

D
ld
3.1.1 Solution 1: resistor in the ground line (R
This solution can be used with any type of load.
The following is an indication on how to dimension the R
1. R
2. R
where -I maximum rating section of the device datasheet.
Power dissipation in R
P
= (-VCC)2/R
D
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the R
GND
values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R
≤ 600mV / (I
GND
≥ (−VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
GND
).
)
(when VCC<0: during reverse battery situations) is:
GND
will produce a shift (I
S(on)max
* R
GND
GND
only).
GND
resistor.
GND
S(on)max
becomes the sum of the
) in the input thresholds and the status output
.
18/30 Doc ID 13349 Rev 6
VNQ5160K-E Application information
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests that Solution 2 is used(see below).
3.1.2 Solution 2: a diode (D
A resistor (R
=1kΩ) should be inserted in parallel with D
GND
) in the ground line.
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( threshold and in the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO T/R 7637/1 table.

3.3 Microcontroller I/Os protection

If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests the insertion of resistors (R lines to prevent the μC I/Os pins from latching up.
The values of these resistors are a compromise between the leakage current of μC and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of the μC I/Os.
if the device drives an
GND
~600mV) in the input
prot
) in the
-V
CCpeak/Ilatchup
≤ R
prot
≤ (V
OHμC-VIH-VGND
Calculation example:
For V
5kΩ ≤ R
Recommended R
CCpeak
prot
= - 100V and I
≤ 65kΩ.
value is 10kΩ.
prot
latchup
≥ 20mA; V

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between the OUTPUT pin and a positive supply voltage (V microprocessor.
The external resistor has to be selected according to the following requirements:
Doc ID 13349 Rev 6 19/30
) / I
IHmax
OHμC
≥ 4.5V
) like the +5V line used to supply the
PU
Application information VNQ5160K-E
1. No false open-load indication when load is connected: in this case we have to avoid
V
to be higher than V
OUT
V
=(VPU/(RL+RPU))RL<V
OUT
2. No misdetection when the load is disconnected: in this case the V
than V
R
<(V
PU
Because I
s(OFF)
up resistor R
; this results in the following condition:
OLmax
PU–VOLmax
)/I
L(off2)
may significantly increase if V
should be connected to a supply that is switched OFF when the module is in
PU
; this results in the following condition:
Olmin
Olmin.
.
is pulled high (up to several mA), the pull-
out
has to be higher
OUT
standby.
The values of V
OLmin
, V
OLmax
and I
are available in the Electrical characteristics
L(off2)
section.

Figure 28. Open-load detection in off-state

V
CC
INPUT
STATUS
DRIVER
+
LOGIC
+
-
VOL
GROUND
V batt. VPU
I
L(off2)
OUT
R
R
PU
RL
20/30 Doc ID 13349 Rev 6
VNQ5160K-E Application information

Figure 29. Waveforms

NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
V
V
OUT>VOL
I
OUT<IOL
t
POL
USDhyst
undefined
V
CC
INPUT STAT_DIS
LOAD CURRENT
STATUS
INPUT
STAT_DIS
LOAD VOLTAGE
STATUS
INPUT
STAT_DIS
LOAD VOLTAGE
LOAD CURRENT
STATUS
V
USD
OPEN LOAD with external pull-up
V
OL
OPEN LOAD without external pull-up
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
LOAD VOLTAGE
I
OUT>IOL
V
OUT>VOL
V
OL
STATUS
t
DSTKON
OVERLOAD OPERATION
T
TSD
T
j
T
R
T
RS
INPUT
STAT_DIS
LOAD CURRENT
I
LIMH
I
LIML
STATUS
current
limitation
power limitation
SHORTED LOAD NORMAL LOAD
thermal cycling
Doc ID 13349 Rev 6 21/30
Application information VNQ5160K-E
3.5 Maximum demagnetization energy (V

Figure 30. Maximum turn-off current versus inductance (for each channel)

10
A
B
C
1
I (A)
0,1
0,1 1 10 100L (mH)
=13.5V)
CC
VIN, I
A: T
B: T
C: T
L
= 150°C single pulse
jstart
= 100°C repetitive pulse
jstart
= 125°C repetitive pulse
jstart
Note: Values are generated with R
In case of repetitive pulses, T must not exceed the temperature specified above for curves A and B.
Demagnetization Demagnetization Demagnetization
=0Ω
L
(at beginning of each demagnetization) of every pulse
jstart
t
22/30 Doc ID 13349 Rev 6
VNQ5160K-E Package and PC board thermal data

4 Package and PC board thermal data

4.1 PowerSSO-24 thermal data

Figure 31. PowerSSO-24 PC board

Note: Layout condition of R
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70mm (front and back side), copper areas: from minimum pad lay-out to 8cm
Figure 32.
RTHj_amb(°C/W)
R
thj-amb
60
55
50
45
40
35
30
0246810
and Zth measurements (PCB: double layer, thermal vias, FR4
th
2
).
vs PCB copper area in open box free air condition (one channel ON)
PCB Cu heatsink area (cm^2)
Doc ID 13349 Rev 6 23/30
Package and PC board thermal data VNQ5160K-E
Figure 33. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel on)
ZTH (°C/W)
1000
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-24
Footprint
2 cm
(1)
8 cm
2
2
1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered
24/30 Doc ID 13349 Rev 6
VNQ5160K-E Package and PC board thermal data
Equation 1: pulse calculation formula:
Z
THδ
where δ = t

Table 16. Thermal parameters

R
TH
P
δ Z
/T
THtp
1 δ–()+⋅=
Area/island (cm2)Footprint28
R1 = R7 = R9 = R11 (°C/W) 1.2
R2 = R8 = R10 = R12 (°C/W) 6
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1 = C7 = C9 = C11 (W.s/°C) 0.0008
C2 = C8 = C10 = C12 (W.s/°C) 0.0016
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
Doc ID 13349 Rev 6 25/30
Package and packing information VNQ5160K-E

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.

5.2 PowerSSO-24™ mechanical data

Figure 35. PowerSSO-24™ package dimensions

.
26/30 Doc ID 13349 Rev 6
VNQ5160K-E Package and packing information

Table 17. PowerSSO-24™ mechanical data

Millimeters
Symbol
Min Typ Max
A 2.45
A2 2.15 2.35
a1 0 0.1
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G 0.1
H 10.1 10.5
h 0.4
k0° 8°
L0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N 10°
X4.1 4.7
Y6.5 7.1
Doc ID 13349 Rev 6 27/30
Package and packing information VNQ5160K-E

5.3 Packing information

Figure 36. PowerSSO-24 tube shipment (no suffix)

Base Q.ty 49
C
B
Bulk Q.ty 1225
Tube length (± 0.5) 532
A 3.5
B 13.8
A
C (± 0.1) 0.6

Figure 37. Tape and reel shipment (suffix “TR”)

Ta b l e 1 8 :
Reel dimensions
Table 19:
Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 24.4 N (min) 100 T (max) 30.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986
Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.05) 1.55 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 11.5 Compartment Depth K (max) 2.85 Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Start
Top
cover
tape
500mm min
Empty components pockets sealed with cover tape.
No componentsNo components Components
500mm min
User direction of feed
28/30 Doc ID 13349 Rev 6
VNQ5160K-E Revision history

6 Revision history

Table 20. Document revision history

Date Revision Changes
8-Jan-2004 1 Initial release.
20-Jan-2006 2 Major general update
Reformatted and restructured. Contents, List of tables and List of figures added.
15-Mar-2007 3
01-Jun-2007 4
22-Jun-2009 5
Section 3.5: Maximum demagnetization energy (VCC = 13.5V)
added.
®
Section 5.1: ECOPACK
packages information added.
New disclaimer added.
Table 4: Absolute maximum ratings: E
MAX entries updated.
Table 13: Electrical transient requirements (part 1/3) :Test level
values III and IV for test pulse 5b and notes updated
Figure 34: Thermal fitting model of a double channel HSD in PowerSSO-24
(1)
note added
Table 17: PowerSSO-24™ mechanical data:
– Deleted A (min) value – Changed A (max) value from 2.47 to 2.45 – Changed A2 (max) value from 2.40 to 2.35 – Changed a1 (max) value from 0.075 to 0.1 Added F and k rows
Updated Figure 35: PowerSSO-24™ package dimensions.
23-Jul-2009 6
Updated Table 17: PowerSSO-24™ mechanical data: – Deleted G1 row – Added O, Q, S, T and U rows
Doc ID 13349 Rev 6 29/30
VNQ5160K-E
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30/30 Doc ID 13349 Rev 6
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