ST VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 User Manual

Features

3

TYPE R

DS(on)

VNB14NV04
VND14NV04
VND14NV04-1

35 mΩ 12 A 40 V

VNS14NV04

■ Linear current limitation

■ Thermal shutdown

■ Short circuit protection

■ Integrated clamp

■ Low current drawn from input pin

■ Diagnostic feedback through input pin

■ ESD protection

■ Direct access to the gate of the Power

MOSFET (analog driving)

■ Compatible with standard Power MOSFET

I

lim

V

clamp

VNB14NV04, VND14NV04

VND14NV04-1, VNS14NV04

"OMNIFET II"

fully autoprotected Power MOSFET

TO-252 (DPAK)

Description

The VNB14NV04, VND14NV04, VND14NV04-1 and

VNS14NV04

STMicroelectronics VIPower™ M0 technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications. Built-in
thermal shutdown, linear current limitation and
overvoltage clamp protect the chip in harsh
environments.

are monolithic devices made using

3

1

TO-251 (IPAK)

SO-8 D

2

PAK

2

1

3

1

Fault feedback can be detected by monitoring the
voltage at the input pin.

Table 1. Device summary

Package Tube Tube (lead free) Tape and reel Tape and reel (lead free)

2

PAK VNB14NV04 VNB14NV04-E

D

TO-252 (DPAK) VND14NV04 VND14NV04-E

TO-251 (IPAK) VND14NV04-1 VND14NV04-1-E -

SO-8 VNS14NV04 - -

April 2010 Doc ID 7393 Rev 8 1/31

VNB14NV0413TR VNB14NV04TR-E

VND14NV0413TR VND14NV04TR-E

-

-

www.st.com

1

Contents VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 D

2

PAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 D

5.4 TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.5 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31 Doc ID 7393 Rev 8

VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. DPAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. D

Table 7. TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. D

Table 9. TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2

PAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2

PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 7393 Rev 8 3/31

List of figures VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 9. Static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11. Static drain-source on resistance vs. input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12. Static drain-source on resistance vs. input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14. Static drain-source on resistance vs. id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 15. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 16. Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 17. Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 18. Input voltage vs. input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 19. Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 20. Turn-off drain source voltage slope (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 21. Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 22. Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 23. Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 24. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 25. Normalized on resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 26. Normalized input threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 27. Current limit vs. junction temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 28. Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 29. DPAK maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 30. DPAK demagnetization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 31. D
Figure 32. D
Figure 33. DPAK PC board
Figure 34. DPAK R

Figure 35. DPAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 36. Thermal fitting model of an OMNIFET II in DPAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 37. SO-8 PC board
Figure 38. SO-8 R
Figure 39. D
Figure 40. D
Figure 41. D
Figure 42. Thermal fitting model of an OMNIFET II in D

Figure 43. TO-251 (IPAK) package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 44. D

Figure 45. TO-252 (DPAK) package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 46. SO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

PAK maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . 17

2

PAK demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

thj-amb

thj-amb

2

PAK PC board

2

PAK R

2

2

thj-amb

PAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 22

PAK package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . 18

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . 20

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 21

2

PAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4/31 Doc ID 7393 Rev 8

VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Block diagram

1 Block diagram

Figure 1. Block diagram

Doc ID 7393 Rev 8 5/31

Electrical specification VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04

2 Electrical specification

Figure 2. Current and voltage conventions

2.1 Absolute maximum rating

Table 2. Absolute maximum rating

Symbol Parameter

V

V

I

R

IN MIN

I

I

V

ESD1

V

ESD2

P

E

MAX

T

T

T

Drain-source voltage (VIN=0 V) Internally clamped V

DS

Input voltage Internally clamped V

IN

Input current +/-20 mA

IN

Minimum input series impedance 10 Ω

Drain current Internally limited A

D

Reverse DC output current -15 A

R

Electrostatic discharge (R=1.5 KΩ, C=100 pF) 4000 V

Electrostatic discharge on output pin only
(R=330 Ω, C=150 pF)

Total dissipation at Tc=25 °C 4.6 74 74 74 W

tot

Maximum switching energy (L=0.4 mH; R
V

=13.5 V; T

bat

Operating junction temperature Internally limited °C

j

c

stg

Case operating temperature Internally limited °C

Storage temperature -55 to 150 °C

=150 °C; IL=18 A)

jstart

=0 Ω;

L

Value

SO-8 DPAK IPAK D

16500 V

93 93 mJ

2

PAK

Unit

6/31 Doc ID 7393 Rev 8

VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Electrical specification

2.2 Thermal data

Table 3. Thermal data

Value

Symbol Parameter

SO-8 DPAK IPAK D

Rthj-case Thermal resistance junction-case max 1.7 1.7 1.7 °C/W

Rthj-lead Thermal resistance junction-lead max 27 °C/W

Rthj-amb Thermal resistance junction-ambient max 90

1. When mounted on a standard single-sided FR4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected to all DRAIN
pins. Horizontal mounting and no artificial air flow.

(1)

65

(1)

102 52

2

PAK

(1)

Unit

°C/W

2.3 Electrical characteristics

-40 < Tj < 150 °C unless otherwise specified.

Table 4. Electrical characteristics

Symbol Parameter Test Conditions Min Typ Max Unit

Off

V

CLAMP

V

CLTH

V

INTH

I

ISS

V

INCL

Drain-source clamp voltage V

Drain-source clamp threshold
voltage

Input threshold voltage VDS=VIN; ID=1 mA 0.5 2.5 V

Supply current from input pin V

Input-source clamp voltage

=0 V; ID=7 A 40 45 55 V

IN

=0 V; ID=2 mA 36 V

V

IN

=0 V; VIN=5 V 100 150 µA

DS

IIN=1 mA
IIN=-1 mA

6

-1.0

6.8 8

-0.3

V

I

DSS

Zero input voltage drain current
(V

=0 V)

IN

VDS=13 V; VIN=0 V; Tj=25 °C
V

DS

On

V

R

DS(on)

Static drain-source on resistance

in

V

in

Dynamic (Tj=25°C, unless otherwise specified)

(1)

g

fs

C

Forward transconductance VDD = 13 V ID = 7 A 18 S

Output capacitance VDS = 13 V f = 1 MHz VIN = 0 V 400 pF

oss

Switching

t

d(on)

t

d(off)

Turn-on delay time

V

Rise time 350 1000 ns

t

r

Turn-off delay time 450 1350 ns

t

Fall time 150 500 ns

f

DD

V

gen

(see Figure 3)

Doc ID 7393 Rev 8 7/31

=25 V; VIN=0 V

= 5 V ID = 7 A Tj = 25 °C
= 5 V ID = 7 A

= 15 V ID = 7 A

= 5 V R

gen

= R

IN MIN

=10 Ω

30
75

35
70

µA

mΩ

80 250 ns

Electrical specification VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04

Table 4. Electrical characteristics (continued)

Symbol Parameter Test Conditions Min Typ Max Unit

t

d(on)

t

d(off)

(di/dt)

Turn-on delay time

t

Rise time 9.7 30.0 µs

r

Turn-off delay time 25.0 µs

Fall time 10.2 30.0 µs

t

f

Turn-on current slope

on

Q

Total input charge

i

Source drain diode

(1)

V

I

SD

Q

RRM

Forward on voltage ISD = 7 A Vin = 0 V 0.8 V

Reverse recovery time

t

rr

Reverse recovery charge 0.8 µC

rr

Reverse recovery current 5 A

Protection

I

t

dlim

T

T

Drain current limit V

lim

Step response current limit V

Over temperature shutdown 150 175 200 °C

jsh

Over temperature reset 135 °C

jrs

I

Fault sink current V

gf

Eas Single pulse avalanche energy

1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

1.5 4.5 µs

V

= 15 V Id = 7 A

DD

V

gen

= 5 V R

= 2.2 KΩ

gen

(see Figure 3)

VDD = 15 V ID = 7 A
V

gen

= 5 V R

gen

= R

IN MIN

=10 Ω

VDD = 12 V ID = 7 A Vin = 5 V;
I

= 2.13 mA (see Figure 7)

gen

= 7 A; di/dt = 40 A/µs

I

SD

= 30 V L = 200 µH

V

DD

16 A/µs

36.8 nC

300 ns

(see test circuit, Figure 4)

= 5 V; V

IN

= 5 V; VDS = 13 V 45 µs

IN

= 5 V; VDS = 13 V; Tj = T

IN

starting T

= 5 V; R

V

IN

L = 24 mH (see Figure 5 and

= 13 V 12 18 24 A

DS

10 15 20 mA

jsh

= 25 °C; VDD = 24 V

j

gen

= R

IN MIN

= 10 Ω;

400 mJ

Figure 6)

8/31 Doc ID 7393 Rev 8

VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Protection features

3 Protection features

During normal operation, the input pin is electrically connected to the gate of the internal
power MOSFET through a low impedance path.

The device then behaves like a standard power MOSFET and can be used as a switch from
DC up to 50 KHz. The only difference from the user’s standpoint is that a small DC current
I

(typ. 100 µA) flows into the input pin in order to supply the internal circuitry.

ISS

The device integrates:

● Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche

characteristics of the Power MOSFET stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly important when driving inductive
loads.

● Linear current limiter circuit: limits the drain current I

voltages. When the current limiter is active, the device operates in the linear region, so
power dissipation may exceed the capability of the heatsink. Both case and junction
temperatures increase, and if this phase lasts long enough, junction temperature may
reach the over temperature threshold T

● Over temperature and short circuit protection: these are based on sensing the chip

jsh

.

temperature and are not dependent on the input voltage. The location of the sensing
element on the chip in the power stage area ensures fast, accurate detection of the
junction temperature. Over temperature cutout occurs in the range 150 to 190 °C, a
typical value being 170 °C. The device is automatically restarted when the chip
temperature falls of about 15 °C below shutdown temperature.

● Status feedback: in the case of an over temperature fault condition (T

device tries to sink a diagnostic current Igf through the input pin in order to indicate fault
condition. If driven from a low impedance source, this current may be used in order to
warn the control circuit of a device shutdown. If the drive impedance is high enough so
that the input pin driver is not able to supply the current I
This will not however affect the device operation: no requirement is put on the current
capability of the input pin driver except to be able to supply the normal operation drive
current I

ISS

.

Additional features of this device are ESD protection according to the Human Body model
and the ability to be driven from a TTL Logic circuit.

to I

D

whatever the input pin

lim

> T

j

, the input pin will fall to 0 V.

gf

jsh

), the

Doc ID 7393 Rev 8 9/31

Protection features VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04

Figure 3. Switching time test circuit for resistive load

Figure 4. Test circuit for diode recovery times

10/31 Doc ID 7393 Rev 8