ST VIPer53 - E User Manual

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General features

Type

European

(195 - 265Vac)

DIP-8 50W 30W

PowerSO-10

TM

65W 40W

US / Wide range

(85 - 265 Vac)

Features

■ Switching frequency up to 300kHz

■ Current limitation

■ Current mode control with adjustable limitation

■ Soft start and shut-down control

■ Automatic burst mode in standby condition

(“Blue Angel“ compliant )

■ Undervoltage lockout with Hysteresis

■ HIgh voltage star-tup current source

■ Overtemperature protection

■ Overload and short-circuit control

Block diagram

VIPer53 - E

OFF-line primary switch

DIP-8PowerSO-10

Description

The VIPer53-E combines an enhanced current
mode PWM controller with a high voltage
MDMesh Power Mosfet in the same package.
Typical applications cover offline power supplies
with a secondary power capability ranging up to
30W in wide range input voltage, or 50W in single
European voltage range and DIP-8 package, with
the following benefits:

■ Overload and short circuit controlled by

feedback monitoring and delayed device reset.

■ Efficient standby mode by enhanced pulse

skipping.

■ Primary regulation or secondary loop failure

protection through high gain error amplifier.

OSC DRAIN

ON/OFF

OSCILLATOR

PWM

VDD

8.4/

11.5V

15V

18V

UVLO

COMPARATO R

ERROR

AMPLIF IER

OVERVOLTAGE

COMPARATO R

0.5V

4.35V

OVERTEMP.

DETECTOR

STANDBY

COMPARAT OR

OVERLOAD

COMPARAT OR

LATCH

S

R1

FF

R2

R3 R4 R5

Q

BLANKING TIM E

SELECTION

150/400ns

BLANKING

4V

4.5V

PWM

COMPARATOR

8V

125k

TOVL COMP SOURCE

1V

0.5V

H

COMP

CURRENT

AMPLIF IER

November 2006 Rev 1 1/36

www.st.com

36

Contents VIPer53 - E

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Primary regulation configuration example . . . . . . . . . . . . . . . . . . . . . . 15

6 Secondary feedback configuration example . . . . . . . . . . . . . . . . . . . . 17

7 Current mode topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9 High voltage Start-up current source . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 Short-circuit and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24

11 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

12 Special recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13 Software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2/36

VIPer53 - E Electrical data

1 Electrical data

1.1 Maximum rating

Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

Table 1. Absolute maximum rating

Symbol Parameter Value Unit

V

I

V

V

OSC

I

COMP

I

TOVL

Continuous drain source voltage (TJ= 25 ... 125°C)

DS

Continuous drain current Internally limited A

D

Supply voltage 0 ... 19 V

DD

OSC input voltage range

COMP and TOVL input current range

Electrostatic discharge:

V

ESD

Machine model (R = 0Ω; C = 200pF)
Charged device model

T

T

T

STG

1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ

should be inserted in series with the TOVL pin.\

Junction operating temperature Internally limited °C

J

Case operating temperature -40 to 150 °C

C

Storage temperature -55 to 150 °C

1.2 Thermal data

Table 2. Thermal data

Symbol Parameter

(1)

(1)

PowerSO-10

-0.3 ... 620 V

0 ... V

DD

-2 ... 2 mA

200

1.5

(1)

DIP-8

(2)

V

V

kV

Unit

R

R

1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the DRAIN pin.

2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the device tab.

Thermal Resistance Junction-case Max 2 20 °C/W

thJC

Thermal Resistance Ambient-case Max 60 80 °C/W

thJA

3/36

Electrical characteristics VIPer53 - E

2 Electrical characteristics

TJ = 25°C, V

= 13V, unless otherwise specified

DD

Table 3. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

BV

I

DSS

R

DS(on)

C

C

1. On clamped inductive load

2. This parameter can be used to compute the energy dissipated at turn on E
to source voltage V

Drain-source voltage

DSS

Off state drain
current

Static drain-source
On state resistance

t

Fall time

fv

t

Rise time

rv

Drain capacitance

oss

Effective output

Eon

capacitance

and the following formula:

DSon

= 1mA; V

I

D

V

= 500V; V

DS

TJ = 125°C

ID = 1A; V

= 25°C

T

J

T

= 100°C

J

ID = 0.2A; V

ID = 1A; V

= 25V

V

DS

200V < V

E

ton

COMP

COMP

= 0V

COMP

= 4.5V; V

= 0V;

TOVL

= 0V

620 V

150 µA

0.9 1

1.7ΩΩ

IN

= 300V

IN

= 300V

(1)

(1)

100 ns

50 ns

170 pF

300

(2)

V

2

DSon

⎛⎞

----------------

⎝⎠

300

according to the initial drain

ton

1.5

< 400V

DSon

1

-- -

C

⋅⋅⋅=

Eon

2

60 pF

Table 4. Oscillator section

Symbol Parameter Test conditions Min. Typ. Max. Unit

R

F

OSC1

F

OSC2

V

OSChi

V

OSClo

Oscillator frequency
initial accuracy

Oscillator frequency
total variation

Oscillator peak
voltage

Oscillator valley
voltage

4/36

= 8kΩ; CT = 2.2nF

T

Figure 12 on page 12

= 8kΩ; CT = 2.2nF

R

T

Figure 16 on page 14

= V

V

DD

DDon

T

= 0 ... 100°C

J

... V

DDovp

95 100 105 kHz

;

93 100 107 kHz

9V

4V

VIPer53 - E Electrical characteristics

Table 5. Supply section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

DSstart

I

DDch1

I

DDch2

I

DDchoff

I

DD0

I

DD1

V

DDoff

V

DDonVDD

V

DDhystVDD

V

DDovp

Drain voltage starting
threshold

Startup charging current

Startup charging current

Startup charging current
in thermal shutdown

Operating supply current
not switching

Operating supply current
switching

V

undervoltage

DD

shutdown threshold

startup threshold

threshold hysteresis

V

Overvoltage

DD

shutdown threshold

Table 6. Error amplifier section

V

= 5V; I

DD

V

= 0 ... 5V; V

DD

Figure 5 on page 10

= 10V; V

V

DD

V

= 5V; V

DD

> TSD - T

T

J

= 0kHz; V

F

sw

= 100kHz

F

sw

= 0mA

DD

= 100V

DS

= 100VFigure 5.

DS

= 100VFigure 7.

DS

HYST

= 0V

COMP

34 50 V

-12 mA

-2 mA

0mA

811mA

9mA

Figure 5 on page 10 7.5 8.4 9.3 V

Figure 5. 10.2 11.5 12.8 V

Figure 5. 2.6 3.1 V

Figure 5. 17 18 19 V

Symbol Parameter Test conditions Min. Typ. Max. Unit

= 0mA

I

V

DDregVDD

∆V

DDreg

G

BW

AV

OL

G

m

V

COMPlo

V

COMPhi

I

COMPlo

I

COMPhi

1. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should
always be present on the COMP pin.

regulation point

VDD regulation point
total variation

Unity gain bandwidth

Voltage gain I

DC transconductance V

Output low level I

Output high level I

Output sinking current

Output sourcing current

COMP

Figure 11. on page 11

I

= 0mA; TJ = 0 ... 100°C 2 %

COMP

From Input = V
V

COMP

I

= 0mA Figure 14 and 15

COMP

= 0mA Figure 14 and 15 40 45 dB

COMP

= 2.5V Figure 11. 11.41.8mS

COMP

= -0.4mA; V

COMP

= 0.4mA; VDD=14V

COMP

= 2.5V; V

V

COMP

to Output =

DD

= 16V 0.2 V

DD

(1)

= 16V

DD

Figure 11. on page 11

= 2.5V; VDD= 14V

V

COMP

Figure 11.

14.5 15 15.5 V

700 kHz

4.5 V

-0.6 mA

0.6 mA

5/36

Electrical characteristics VIPer53 - E

Table 7. PWM comparator section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

= 1 ... 4 V Figure 10.

H

COMP

V

COMPosVCOMP

I

Dlim

I

Dmax

V

COMPbl

t

t

t

ONmin1

t

ONmin2

V

COMPoff

∆V

Peak drain current
limitation

Drain current
capability

Current sense delay to

t

d

Turn-Off

V

COMP

change threshold

Blanking time V

b1

Blanking time V

b2

Minimum On time V

Minimum On time V

V

COMP

Threshold

/ ∆I

COMP

Offset

blanking time

Shutdown

DPEAK

COMP

/dt = 0 1.7 2 2.3 V/A

dI

D

dI

/dt = 0 Figure 10. on page 11 0.5 V

D

I

= 0mA; V

COMP

Figure 10.

/dt = 0

dI

D

= V

V

COMP

/dt = 0 1.6 1.9 2.3 A

dI

D

= 1A 250 ns

I

D

COMPovl

TOVL

; V

= 0V

= 0V

TOVL

1.7 2 2.3 A

Figure 6 on page 10 1V

COMP

COMP

COMP

COMP

< V

> V

< V

> V

COMPBL

COMPBL

COMPBL

COMPBL

Figure 6. 300 400 500 ns

Figure 6. 100 150 200 ns

450 600 750 ns

250 350 450 ns

Figure 9 on page 11 0.5 V

Table 8. Overload protection section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

COMPovl

V

V

1. V

DIFFovl

OVLth

t

OVL

COMPovl

V

overload

COMP

threshold

V

COMPhi

to V

COMPovl

voltage difference

V

overload

TOVL

threshold

Overload delay

is always lower than V

I

TOVL

Figure 4 on page 9

I

TOVL

= 0mA

= V

V

DD

Figure 4.

Figure 4. 4V

C

OVL

COMPhi

(1)

= 0mA

... V

DDoff

(1)

DDreg

= 100nF Figure 4.

4.35 V

;

50 150 250 mV

8ms

Table 9. Over temperature Protection Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

T

T

HYST

Thermal shutdown

SD

temperature

Thermal shutdown
hysteresis

Figure 7 on page 10 140 160 °C

Figure 7 on page 10 40 °C

6/36

VIPer53 - E Pin connections and function

V

S

3 Pin connections and function

Figure 1. Pin connection (top view)

OSC

SOURCE

SOURCE

1

2

3

8

7

6

54

TOVLCOMP

VDD

NC

DRAIN

DIP-8 PowerSO-10

Figure 2. Current and voltage conventions

I

DD

VDD

I

OSC

OSC

15V

DD

I

V

OSC

TOVL

V

TOVL

I

COMP

SOURCECOMPTOVL

DRAIN

I

D

V

D

V

COMP

7/36

Pin connections and function VIPer53 - E

Table 10. Pin function

Pin Name Pin function

Power supply of the control circuits. Also provides the charging current of the external
capacitor during start-up. The functions of this pin are managed by four threshold
voltages:

V

DD

SOURCE Power MOSFET source and circuit ground reference.

DRAIN

COMP

TOVL

- VDDon: Voltage value at which the device starts switching (Typically 11.5 V).

- VDDoff: Voltage value at which the device stops switching (Typically 8.4 V).

- VDDreg: Regulation voltage point when working in primary feedback
(Trimmed to 15 V).

- VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).

Power MOSFET drain. Also used by the internal high voltage current source during the
start-up phase to charge the external V

capacitor.

DD

Input of the current mode structure, and output of the internal error amplifier. Allows
the setting of thedynamic characteristic of the converter through an external passive
network. The useful voltage range extends from 0.5V to 4.5V. The Power MOSFET is
always off below 0.5V, and the overload protection is triggered if the voltage exceeds

4.35V. This action is delayed by the timing capacitor connected tothe TOVL pin.

Allows the connection of an external capacitor for delaying the overload protection,
which is triggered by a voltage on the COMP pin higher than 4.35V.

OSC Allows the setting of the switching frequency through an external Rt-Ct network.

8/36

VIPer53 - E Operation pictures

V

4 Operation pictures

Figure 3. Rise and fall time

I

D

C<<C

OSS

CLD

t

V

DS

90%

t

fv

10%

Figure 4. Overloaded event

V

DD

V

DDon

V

DDoff

V

COMP

t

rv

Normal

operation

VDD

OSC

15V

DRAIN

300

SOURCECOMPTOVL

t

Abnormal
operation

V

DIFFovl

V

TOVL

V

OVLth

t

OVL

V

DS

Switching

Not

switching

9/36

Operation pictures VIPer53 - E

Figure 5. Start-up V

I

DD

I

I

DDch2

I

DDch1

DD0

V

DDhyst

V

DDoff

current Figure 6. Blanking time

DD

t

b

t

b1

V

V

DDon

VDS = 100 V

F

= 0 kHz

SW

DD

t

b2

V

COMPbl

Figure 7. Thermal shutdown Figure 8. Overvoltage event

V

V

DDovp

DD

TSD-T

T

T

HYST

j

SD

V

COMPhi

V

V

DD

V

DDon

COMP

Automatic

startup

V

COMP

V

DS

Abnormal
operation

Switching

Not

switching

10/36

VIPer53 - E Operation pictures

Figure 9. Shutdown action Figure 10. Comp pin gain and offset

V

OSC

V

OSChi

V

OSClo

t

I

Dpeak

V

COMP

V

COMPoff

I

D

Figure 11. Output characteristics

I

COMP

I

COMPhi

Slope = Gm

V

0

DDreg

I

Dlim

I

Dmax

Slope = 1 / H

COMP

t

V

COMP

V

COMPos

V

COMPovl

V

COMPhi

t

V

DD

I

COMPlo

11/36

Operation pictures VIPer53 - E

Figure 12. Oscillator schematic

Vcc

Rt

OSC

320 Ω

Ct

VDD

PWM

section

SOURCE

The switching frequency settings shown on the graphic here below is valid within the
following boundaries:

Rt > 2kΩ

F

= 300kHz

SW

Figure 13. Oscillator settings

Frequency (kHz)

300

100

12/36

2.2nF

4.7nF

10nF

22nF

10

110100

R

T

(KΩ)

1nF

VIPer53 - E Operation pictures

Figure 14. Error amplifier test cpfiguration

Vin

VDD

OSC

15V

2.5 V

DRAIN

SOURCECOMPTOVL

Vout

R

This configuration is for test purpose only. In order to insure a correct stability of the error
amplifier, a capacitor of 10nF (minimum value: 8nF) should be always connected between
COMP pin and ground. See figures Figure 18, 19 and 22.

Figure 15. Error amplifier transfer function

Gain (dB)

60

40

20

0

-20

-40

-60

Open

Ω

R = 10 k

Ω

R = 2.2 k

R = 470 Ω

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

13/36

Operation pictures VIPer53 - E

Figure 16. Typical frequency variation vs. junction temperature

Normalised Frequency

1.04

1.02

1

0.98

0.96

-20 0 20 40 60 80 100 120

Temperature (°C)

Figure 17. Typical current limitation vs. junction temperature

Normalised IDlim

1.04

1.02

1

0.98

0.96

-20 0 20 40 60 80 100 120

Temperature (°C)

14/36

VIPer53 - E Primary regulation configuration example

5 Primary regulation configuration example

Figure 18. Off line power supply with auxiliary supply feedback

F1

AC IN

C1

T1

R1

U1

VIPer73

R3

OSC

C4

C5

VDD

15V

D1

C2

R4

DRAIN

SOURCECOMPTOVL

R6

1k

C6

C11

10nF

R5

C7

R2

C3

T2

D2

C10

L1

C9

C8

DC OUT

D3

D4

The schematic on Figure 18 delivers a fixed output voltage by using the internal error
amplifier of the device in a primary feedback configuration. The primary auxiliary winding
provides a voltage to the V

pin, and is automatically regulated at 15V, due to the internal

DD

error amplifier connected to this pin. The secondary voltage has to be adjusted through the
turn ratio of the transformer between auxiliary and secondary.

The error amplifier of the VIPer53 is a transconductance type: its output is a current
proportional to the difference of voltage between the V

pin and the internally trimmed 15V

DD

reference (i.e., the error voltage). As the transconductance value is set at a relatively low
value to control the overall loop gain and ensure stability, this current has to be integrated by
a capacitor (C7 in Figure 18). When the steady state operation is reached, this capacitor
blocks any DC current from the COMP pin and imposes a “nil” error voltage. Therefore, the
V

voltage is accurately regulated to 15V.

DD

This results in a good load regulation, which depends only on transformer coupling and
output diodes impedance. The current mode structure takes care of all incoming voltage
changes, thus providing at the same time an excellent line regulation.

15/36

Primary regulation configuration example VIPer53 - E

The switching frequency can be set to any value through the choice of R3 and C5. This
allows to optimize the efficiency of the converter by adopting the best compromise between
switching losses, EMI (Lower with low switching frequencies) and transformer size (Smaller
with high switching frequencies). For an output power of a few watts, typical switching
frequencies between 20kHz and 40kHz because of the small size of the transformer. For
higher power, 70kHz to 130kHz are generally chosen.

The R5 compensation resistor value sets the dynamic behavior of the converter. It can be
adjusted to provide the best compromise between stability and recovery time with fast load
changes.

16/36

VIPer53 - E Secondary feedback configuration example

6 Secondary feedback configuration example

Figure 19. Off line power supply with optocoupler feedback

F1

AC IN

C1

R1

C4

T1

U1

VIPe r73

R3

OSC

15V

C5

VDD

D1

C2

R4

DRAIN

SOURCECOMPTOVL

C11

R9

1k

C6

10nF

R5

C7

R2

C3

T2

D2

C10

L1

C8

R8

C12

C9

R7

R6

DC OUT

D3

D4

U2

U3

When a more accurate output voltage is needed, the way is to monitor it directly secondary
side, and drive the PWM controller through an optocoupler as shown on Figure 17.

The optocoupler is connected in parallel with the compensation network on the COMP pin.
The design of the auxiliary winding that the VDD voltage is always lower than the internal
15V reference. The internal error amplifier will therefore be saturated in the high state, and
because of its transconductance nature, will deliver a constant biasing current of 0.6mA to
the optotransistor. This current does not depend on the compensation voltage, and so it
does not depend on the output load either. Consequently, the gain of the optocoupler
ensures consequently a constant biasing of the TL431 device (U3) which is in charge of
secondary regulation. If the optocoupler gain is sufficiently low, no additional components
are required to ensure a minimum current biasing of U3. Also, the low biasing current value
avoid any ageing of the optocoupler.

The constant current biasing can be used to simplify the secondary circuit: Instead of a
TL431, a simple zener and resistance network in series with the optocoupler diode can
insure a good secondary regulation. As the current flowing in this branch remains constant
for the same reason as above, typical load regulation of 1% can be achieved from zero to full
output current with this simple configuration.

17/36

Secondary feedback configuration example VIPer53 - E

Since the dynamic characteristics of the converter are set on the secondary side through
components associated to U3, the compensation network has only a role of gain
stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed
value of 1kΩ, offering the possibility of using C7 as a soft start capacitor: When starting up
the converter, the VIPer53 device delivers a constant current of 0.6 mA on the COMP pin,
creating a constant voltage of 0.6V in R5 and a rising slope across C7. This voltage shape,
together with the operating range of 0.5V to 4.5V provides a soft start-up of the converter.
The rising speed of the output voltage can be set through the value of C7. The C4 and C6
values must be adjusted accordingly in order to ensure a correct start-up.

18/36

VIPer53 - E Current mode topology

7 Current mode topology

The VIPer53-E implements the conventional current mode control method for regulating the
output voltage. This kind of feedback includes two nested regulation loops:

The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored
with a SenseFET technique and converted into a voltage. When V
power switch is turned off. This structure is completely integrated as shown on the Block
Diagram on page 1, with the current amplifier, the PWM comparator, the blanking time
function and the PWM latch. The following formula gives the peak current in the Power
MOSFET according to the compensation voltage:

Equation 1

S reaches V

COMP

, the

I

Dpeak

V

------------------------------------------------- -=

–

COMPVCOMPos

H

COMP

The outer loop defines the level at which the inner loop regulates peak current in the power
switch. For this purpose, V

is driven by the feedback network (TL431 through an

COMP

optocoupler in secondary feedback configuration, see Figure 19 on page 17) and is sets
accordingly the peak drain current for each switching cycle.

As the inner loop regulates the peak primary current in the primary side of the transformer,
all input voltage changes are compensated for before impacting the output voltage. This
results in an improved line regulation, instantaneous correction to line changes, and better
stability for the voltage regulation loop.

Current mode topology also provides a good converter start-up control. The compensation
voltage can be controlled to increase slowly during the start-up phase, so the peak primary
current will follow this soft voltage slope to provide a smooth output voltage rise, without any
overshoot. The simpler voltage mode structure which only controls the duty cycle, leads
generally to high current at start-up with the risk of transformer saturation.

An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in the case of current spikes caused by primary side
transformer capacitance or secondary side rectifier reverse recovery time when working in
continuous mode.

19/36

Standby mode VIPer53 - E

8 Standby mode

The device offers a special feature to address the low load condition. The corresponding
function described hereafter consists of reducing the switching frequency by going into burst
mode, with the following benefits:

– It reduces the switching losses, thus providing low consumption on the mains lines.

The device is compliant with “Blue Angel” and other similar standards, requiring less
than 0.5 W of input power when in standby.

– It allows the regulation of the output voltage, even if the load corresponds to a duty

cycle that the device is not able to generate because of the internal blanking time, and
associated minimum turn on.

For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM
latch and the Power MOSFET in the Off state as long as V
Block Diagram on page 1). If the output load requires a duty cycle below the one defined by
the minimum turn on of the device, the V

0.5V threshold (V

COMPoff

). The Power MOSFET can be completely Off for some cycles, and

resumes normal operation as soon as V

net decreases its voltage until it reaches this

COMP

is higher than 0.5V. The output voltage is

COMP

regulated in burst mode. The corresponding ripple is not higher than the nominal one at full
load.

remains below 0.5V (See

COMP

In addition, the minimum turn on time which defines the frontier between normal operation
and burst mode changes according to V

value. Below 1.0V (V

COMP

COMPbl

), the blanking
time increases to 400ns, whereas for higher voltages, it is 150ns Figure 6 on page 10 The
minimum turn on times resulting from these values are respectively 600 ns and 350 ns,
when taking into account internal propagation time. This brutal change induces an
hysteresis between normal operation and burst mode as shown on Figure 20 on page 21.

When the output power decreases, the system reaches point 2 where V
V

COMPbl

. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding

COMP

equals

the effective turn-on time that should be needed at this output power level. Therefore the
regulation loop will quickly drive V

COMP

to V

COMPoff

(Point 3) in order to pass into burst
mode and to control the output voltage. The corresponding hysteresis can be seen on the
switching frequency which passes from F

which is the normal switching frequency set

SWnom

by the components connected to the OSC pin and to FSWstby. Note: This frequency is
actually an equivalent number of switching pulses per second, rather than a fixed switching
frequency since the device is working in burst mode.

As long as the power remains below P
V

COMPsd

and the converter works in burst mode. Its “density” increases (i.e. the number of

missing cycles decreases) as the power approaches P

the output of the regulation loop remains stuck at

RST

and finally resumes normal

RST

operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be
seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power level.

The power points value P

RST

and P

are defined by the following formulas:

STBY

Equation 2

1

RST

-- -

• tb1td+()•

F

SWnom

2

P

20/36

2

V2• IN

1

------ -

•=

Lp

VIPer53 - E Standby mode

Equation 3

1

P

STBY

-- -

F

• Ip2V

SWnom

2

()• Lp•=

COMPbl

COMPbl

2

) is the peak Power MOSFET current corresponding to a compensation
(1V).

Where Ip(V
voltage of V

COMPbl

Note: The power point PSTBY where the converter is going into burst mode does not depend on

the input voltage.

The standby frequency F

SWstby

is given by:

Equation 4

P

STBY

P

SWstby

-----------------

P

RST

•=

F

SWnom

The ratio between the nominal and standby switching frequencies can be as high as 4,
depending on the Lp value and input voltage.

Figure 20. Standby mode implementation

ton

600ns
Minimum
turn on

350ns

3

V

COMPsd

V

COMPoff

2

V

COMPbl

1

V

COMP

P

P

P

RST

STBY

IN

F

SWstby

1

3

2

F

SW

F

SWnom

21/36

High voltage Start-up current source VIPer53 - E

9 High voltage Start-up current source

An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits in standby
mode with reduced consumption, and also supplies the external capacitor connected to the
V

pin. As soon as the voltage on this pin reaches the high voltage threshold V

DD

UVLO logic, the device turns into active mode and starts switching. The start-up current
generator is switched off, and the converter should normally provide the needed current on
the V

pin through the auxiliary winding of the transformer, as shown on Figure 19 on

DD

page 17.

DDon

of the

The external capacitor C

on the VDD pin must be sized according to the time needed by

VDD

the converter to start-up, when the device starts switching. This time tss depends on many
parameters, including transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin and possible secondary feedback
circuit.

The following formula can be used for defining the minimum capacitor needed:

Equation 5

I

tss⋅

DD1

C

Figure 21 on page 23 shows a typical start-up event. V

current I
down to I
rise. Device starts switching for V
energy to V

The charging current change at V

at about 9 mA. When about V

DDch1

which is about 0.6mA. This lower current leads to a slope change on the VDD

DDch2

capacitor after the start-up time tss.

DD

equal to V

DD

DDoff

---------------------------

>

VDD

V

DDhyst

starts from 0V with a charging

DD

is reached, the charging current is reduced

DDoff

, and the auxiliary winding delivers some

DDon

allows a fast complete start-up time t

SDU

, and
maintains a low restart duty cycle. This is especially useful for short circuits and overloads
conditions, as described in the following section.

22/36

VIPer53 - E High voltage Start-up current source

Figure 21. Start-up waveforms

I

DD

I

DD1

t

I

DDch2

I

DDch1

V

V

V

V

DD

DDreg

DDst

DDsd

tSS

tSU

t

23/36

Short-circuit and overload protection VIPer53 - E

10 Short-circuit and overload protection

A V

COMPovl

V

COMP

When reaching typically V

threshold of about 4.35V has been implemented on the COMP pin. When

goes above this level, the capacitor connected on the TOVL pin begins to charge.

(4V), the internal MOSFET driver is disabled and the device

OVLth

stops switching. This state is latched because of to the regulation loop which maintains the
COMP pin voltage above the V

COMPovl

more energy from the auxiliary winding, its voltage drops down until it reaches V
the device is reset, recharging the V
drops below the V

COMPovl

threshold for any reason during the VDD drop, the device

threshold. Since the VDD pin does not receive any

capacitor for a new restart cycle. Note: If VCOMP

DD

DDoff

and

resumes switching immediately.

The device enters an endless restart sequence if the overload or short circuit condition is
maintained. The restart duty cycle D

is defined as the time ratio for which the device tries

RST

to restart, thus delivering its full power capability to the output. In order to keep the whole
converter in a safe state during this event, D

must be kept as low as possible, without

RST

compromising the real start-up of the converter. A typical value of about 10% is generally
sufficient. For this purpose, both V

and TOVL capacitors can be used to satisfy the

DD

following conditions:

Equation 6

C

12.5 106–tss⋅⋅>

OVL

Equation 7

⋅

4

1

C

VDD

810

⋅⋅ ⋅>

⎛⎞

-------------- 1–

⎝⎠

D

RST

Refer to the previous start-up section for the definition of tss, and C

C

OVLIDDch2

-------------------------------------- -

V

DDhyst

must also be

VDD

checked against the limit given in this section. The maximum value of the two calculus will
be adopted.

All this behavior can be observed on Figure 8 on page 10. In Figure 10 on page 11 the value
of the drain current Id for V
is the drain current to take into account for design purposes. Since I

COMP

= V

COMPovl

is shown. The corresponding parameter I

represents the

Dmax

Dmax

maximum value for which the overload protection is not triggered, it defines the power
capability of the power supply.

24/36

VIPer53 - E Transconductance error amplifier

11 Transconductance error amplifier

The VIPer53-E includes a transconductance error amplifier. Transconductance Gm is the
change in output current I

Equation 8

versus change in input voltage VDD. Thus:

COMP

∂I

------------------- -=

∂V

COMP

DD

Gm

The output impedance Z

at the output of this amplifier (COMP pin) can be defined as:

COMP

Equation 9

∂V

COMP

Z

COMP

--------------------- -

∂I

COMP

This last equation shows that the open loop gain A

∂V

1

--------- -

Gm

COMP

--------------------- -

⋅==

∂V

DD

can be related to Gm and Z

VOL

COMP

:

Equation 10

A

VOL

Gm Z

⋅=

COMP

where Gm value for VIPer53 is typically 1.4mA/V.

Gm is well defined by specification, but Z

and therefore A

COMP,

are subject to large

VOL,

tolerances. An impedance Z must be connected between the COMP pin and ground in order
to accurately define the transfer function F of the error amplifier, the following equation, very
similar to the one above:

Equation 11

Fs() Gm Z s()⋅=

The error amplifier frequency response is shown in .0 for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier
shows an internal Z

of about 140KΩ. More complex impedances can be connected on

COMP

the COMP pin to achieve different compensation methods. A capacitor provides an
integrator function, thus eliminating the DC static error, and a resistance in series leads to a
flat gain at higher frequency, introducing a zero level and ensuring a correct phase margin.
This configuration illustrated in Figure 22, for the schematic and Figure 23 on page 28 for
the error amplifier transfer function for a typical set of values of C

COMP

and R

COMP

.

Note that a 10nF capacitor (8nF, minimum value) should always be connected to the COMP
pin to ensure a correct stability of the internal error amplifier.

The complete converter open loop transfer function can be built from both power cell and
error amplifier transfer functions. A theoretical example can be seen in Figure 24 for a
discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no

25/36

Transconductance error amplifier VIPer53 - E

optocoupler, the internal error amplifier is fully used for regulation). A typical schematic
corresponding to this situation can be seen on Figure 18.

The transfer function of the power cell is represented as G(s) in Figure 24 Iexhibits a pole
which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, R

and RL2. A zero at higher frequency values then appears, due to the output

L1

capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control.

The error amplifier has a fixed behavior, similar to the one shown in Figure 23. Its bandwidth
is to avoid injection of high frequency noise in the current mode section. A zero due to the
R

COMP-CCOMP

network is set at the same value as the maximum load RL2 pole.

The total transfer function is shown as F(s). G(s) at the bottom of Figure 24. For maximum
load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and
the result is a perfect first order decreasing until it reaches the zero of the output capacitor
ESR. The error amplifier cut-off then definitely any further spurious noise or resonance from
disturbing the regulation loop.

The point where the complete transfer function has a unity gain is known as the regulation
bandwidth and has:

– The higher it is, the faster the reaction will be to an eventual load change, and the

smaller the output voltage change will be.

– The phase shift in the complete system at this point has to be less than 135° to

ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.

In Figure 24, the unity gain is reached in a first order slope, so the stability is ensured.

The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected: As the transfer function above the zero due the capacitor
ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take
place), the bandwidth should always be lower than the minimum of F

As the highest bandwidth is obtained with the highest output power (Plain line with R

and ESR zero.

C

L2

load
in Figure 24), the above criteria will be checked for this condition and allows to define the
value of R

, as the error amplifier gain depends only on this value for this frequency

COMP

range. The following formula can be derived:

Equation 12

⋅⋅

P

R

COMP

2

V

P

With: and:

OUT2

--------------=

OUT

R

L2

OUT2

-----------------

P

MAX

F

BW2RL2COUT

------------------------------------------------------

⋅=

Gm

P

MAX

1

-- -

⋅⋅ ⋅=

2

LPI

2
LIM

F

SW

26/36

VIPer53 - E Transconductance error amplifier

The lowest load gives another condition for stability: The frequency F

must not encounter

BW1

the second order slope generated by the load pole and the integrator part of the error
amplifier. This condition can be met by adjusting the C

COMP

value:

Equation 13

RL1C

⋅

OUT

⋅⋅

With:

P

OUT1

V

---------------=

2

OUT

R

C

L1

------------------------------ ------------------------

COMP

6.3 G m R

The above formula gives a minimum value for C

2

COMP

P

OUT1

-------------------⋅>

P

MAX

. It can be then increased to provide a

COMP

natural soft start function as this capacitor is charged by the error amplifier current capacity
I

COMPhi

at start-up.

Figure 22. Typical compensation network

VDD

DRAIN

OSC

15V

SOURCECOMPTOVL

Rcomp

10nF

Ccomp

27/36

Transconductance error amplifier VIPer53 - E

Figure 23. Typical transfer functions

Gain (dB)

60

50

40

30

20

10

0

-10
1 10 100 1k 10k 100k 1M

Phase (°)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100
1 10 100 1k 10k 100k 1M

Frequency (Hz)

Frequency (Hz)

Rcomp=4.7k
Ccomp=470nF

Rcomp=4.7k
Ccomp=470nF

28/36

VIPer53 - E Transconductance error amplifier

Figure 24. Complete converter transfer function

G(S)

1

-----------------------------------------------

π RL1C

⋅⋅

OUT

1

-----------------------------------------------

π RL2C

⋅⋅

OUT

F

1

1

-----------------------------------------------------------

2 π ESR C

⋅⋅ ⋅

OUT

F(S)

1

F(S).G(S)

1

1

----------------------------------------------------------------------------

2 π R

⋅⋅ ⋅

COMPCCOMP

BW1

F

FBW2

F

C

F

F

29/36

Special recommendations VIPer53 - E

12 Special recommendations

As steted in the error amplifier section, a capacitor of 10nF capacitor (minimum value: 8nF)
should always be connected to the COMP pin to ensure correct stability of the internal error
amplifier Figure 18, 19 and 22.

In order to improve the ruggedness of the device versus eventual drain overvoltages, a
resistance of 1kΩ should be inserted in series with the TOVL pin, as shown on Figure 18,

Figure 19 on page 17.

Note that, this resistance does not impact the overload delay, as its value is negligible prior
to the internal pull-up resistance (about 125kΩ).

13 Software implementation

All the above considerations and some others are included included in ST design software
which provides all of the needed components around the VIPer device for specified output
configurations, and is available on www.st.com.

30/36

VIPer53 - E Package mechanical data

14 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

31/36

Package mechanical data VIPer53 - E

Table 11. DIP8 mechanical data

Dimensions

Databook (mm)

Ref.

Nom. Min Max

A 5.33

A1 0.38

A2 2.92 3.30 4.95

b 0.36 0.46 0.56

b2 1.14 1.52 1.78

c 0.20 0.25 0.36

D 9.02 9.27 10.16

E 7.62 7.87 8.26

E1 6.10 6.35 7.11

e2.54

eA 7.62

eB 10.92

L 2.92 3.30 3.81

Package Weight Gr. 470

Figure 25. Package dimensions

32/36

VIPer53 - E Package mechanical data

Table 12. PowerSO-10 mechanical data

Dimensions

Ref.

Nom. Min Max

A 3.35 3.65

A1 0.00 0.10

B 0.40 0.60

c 0.35 0.55

D 9.40 9.60

D1 7.40 7.60

E 9.30 9.50

E1 7.20 7.40

E2 7.20 7.60

E3 6.10 6.35

E4 5.90 6.10

e 1.27

F 1.25 1.35

H 13.80 14.40

h 0.50

L 1.20 1.80

q 1.70
α 0° 8°

Databook (mm)

Figure 26. Package dimensions

33/36

Order codes VIPer53 - E

15 Order codes

Table 13. Order codes

Part Number Package Shipment

VIPer53DIP-E DIP-8 Tube

VIPer53SP-E PowerSO-10 Tube

VIPer53SPTR - E PowerSO-10 Tape and reel

34/36

VIPer53 - E Revision history

16 Revision history

Table 14. Revision history

Date Revision Changes

13-Nov-2006 1 Initial release.

35/36

VIPer53 - E

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36/36