Datasheet VIPer50-E Datasheet (ST)

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F

C

0

0

2

9

1

General Features

VIPer50-E

SMPS PRIMARY I.C.

Type

V

DSS

I

n

R

DS(on)

VIPer50-E 620V 1.5A 5 Ω

■ ADJUSTABLE SWITCHING FREQUENCY UP

TO 200 kHz

■ CURRENT MODE CONTROL

■ SOFT START AND SHUTDOWN CONTROL

■ AUTOMATIC BURST MODE OPERATION IN

STAND-BY CONDI T ION ABLE TO MEET
“BLUE ANGEL” NORM (<1w TOTAL POWER
CONSUMPTION)

■ INTERNALLY TRIMMED ZENER

REFERENCE

■ UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■ INTEGRATED START-UP SUPPLY

■ OVER-TEMPERATURE PROTECTION

■ LOW STAND-BY CURRENT

■ ADJUSTABLE CURRENT LIMITATION

Block Diagr am

PENTAWATT HV

PENTAWATT HV (022Y)

Description

VIPer50-E, made using VIPower M0 Technology,
combines on the same si licon chip a state-of-the­art PWM circuit together with a n optimized, high
voltage, Vertical Power MOSFET (620V/ 1.5A).

Typical applications cover offline power supplies
with a secondary power capability of 25W in wide
range condition and 50W in single ran ge or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the ability to operate in stand-by mode
without extra components.

_

2 V/A

CURRENT

AMPLIFIER

DRAIN

SOURCE

OSC

ON/OFF

SECURITY

LATCH

FF

R/S

S

OVERTEMP.

DETECTOR

1.7 µs
DELAY

0.5 V

ERROR

AMPLIFIER

UVLO

LOGIC

+
_

4.5 V

DD

V

_

13 V

+

Q

OSCILLATOR

PWM

LATCH

S

R1

FF

R2 R3

COMP

Q

250 ns

BLANKING

0.5V
+

+
_

Rev 1

September 2005 1/29

www.st.com

29

VIPer50-E

Contents

1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Drain Pin (Integrated Power MOSFET Drain): . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Source Pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 V

3.4 Compensation Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.5 OSC Pin (Oscillat or Freque nc y ): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin (Power Supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DD

4 Typical Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Current Mode Topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.2 Stand-by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.3 High Voltage Start-up Current Suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Transconducta nce Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 External Clock Synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Primary Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Operation Pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/29

VIPer50-E

6 Electrical Over Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Electrical Over Stress Ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3/29

1 Electrical Data VIPer50-E

1 Electrical Data

1.1 Maximum Rating

Table 1. Absolute Maximum Rating

Symbol Parameter Value Unit

V

I

V

V

OSC

V

COMP

I

COMP

V

ESD

I

D(AR)

P

TOT

T

T

STG

DS

D

DD

Continuous Drain-Source Voltage (TJ = 25 to 125°C) –0.3 to 620 V
Maximum Current Internally limited A
Supply Voltage 0 to 15 V
Voltage Range Input 0 to V

DD

Voltage Range Input 0 to 5 V
Maximum Continuous Current ±2 mA
Electrostati c Discharge (R = 1.5kΩ; C = 100pF) 4000 V
Avalanche Drai n-Source Current, Repetitive or Not Repetitive

= 100°C; Pulse width limited by TJ max; δ < 1%)

(T

C

1.5 A

Power Dissipati on at TC= 25ºC 60 W
Junction Operat ing Temperature Internally limited °C

J

Storage Temperature -65 to 150 °C

V

4/29

VIPer50-E 1 Electrical Data

1.2 Electrical Characteristics

TJ = 25°C; VDD = 13V, unless otherwise spec ified

Table 2. Power Section

Symbol Parameter Test Conditions Min Typ Max Unit

BV

I

DSS

R

DS(on)

t
t

C

oss

(1) On Inductive Load, Clamped.

Drain-Source Voltage ID = 1mA; V

DS

Off-State Drain
Current

St atic Drain-Source
On Resistance

Fall Ti me ID = 0.2A; V

f

Rise Time ID = 1A; V

r

Output Capacitance V

= 0V 620 V

COMP

V
V

ID = 1A
I

= 0V; Tj = 125°C

COMP
DS

= 620V

1mA

2.3 5.0

= 1A; TJ= 100°C

D

=300V (1)Figure 7 100 ns

IN

= 300V (1)Figure 7 50 ns

IN

= 25V 120 pF

DS

9

Table 3. Supply Section

Symbol Parameter Test Conditions Min Typ Max Unit

I

DDch

I

DD0

I

DD1

I

DD2

V

DDoff

V

DDon

V

DDhyst

Start-Up Charging Current V

Operating Supply Current V

Operating Supply Current V
Operating Supply Current V
Undervoltage Shutdown (see Figure 6) 7.5 8 9 V
Undervoltage Reset (see Figure 6) 11 12 V
Hys teres is Start-up (see Figure 6) 2.4 3 V

= 5V; VDS = 35V

DD

(see Figure 6)(see Fig ure 11)

= 12V; F

DD

SW

= 0kHz

(see Figure 6)

= 12V; F

DD

= 12V; F

DD

= 100kHz 14 mA

sw

= 200kHz 16 mA

sw

-2 mA

12 16 mA

Ω

Table 4. Oscillator Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

F

V

OSCIH

V

OSCIL

SW

Oscillator Frequency Total
Variation

RT=8.2KΩ; CT=2.4nF
V

=9 to 15V;

DD

with R

± 1%; CT± 5%

T

(see Figure 10)(see Figure 14)

Oscillator Peak Voltage 7.1 V
Oscillator Valley Voltage 3.7 V

90 100 110 KHz

5/29

1 Electrical Data VIPer50-E

Table 5. Error Amplifier Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

V

DDREG

∆V

DDreg

G

BW

VDD Regulation Point I

=0mA (see Figure 5) 12.6 13 13.4 V

COMP

Tota l Variatio n TJ = 0 to 100°C 2 %
Unity Gain Bandwidth From Input =VDD to

Output = V

COMP

150 KHz

COMP pin is open

(see Figure 15)

A

VOL

Open Loop Voltage Gain COMP pin is open

45 52 dB

(see Figure 15)

G

m

V

COMPLO

V

COMPHI

I

COMPLO

I

COMPHI

DC Transconductance V
Output Low Level I
Output High Level I
Output Low Curre nt Capability V
Output High Current

=2.5V(see Figure 5) 1.1 1.5 1.9 mA/V

COMP

=-400µA; VDD=14V 0.2 V

COMP

=400µA; VDD=12V 4.5 V

COMP

=2.5V; VDD=14V -600 µA

COMP

V

=2.5V; VDD=12V 600 µA

COMP

Capability

Table 6. PWM Comparator Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

H

V

COMPoffVCOMP

I

Dpeak

t

∆V

ID

COMP

/ ∆I

DPEAK

Offset I
Peak Current Limitat ion V
Current Sense Delay to Turn-

d

Off

V

= 1 to 3 V 1.4 2 2.6 V/A

COMP

= 10mA 0.5 V

DPEAK

= 12V; COMP pin open 1.5 2 2.7 A

DD

ID = 0.5A 250 ns

t

t

on(min)

Blanking Ti m e 250 360 ns

b

Minimum On Time 350 1200 ns

Table 7. Shutdown and Overtemperature Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

V

COMPth

t

DISsu

T

tsd

T

hyst

6/29

Restart Threshold (see Figure 8) 0.5 V
Disable Set Up Time (see Figure 8) 1.7 5 µs
Thermal Shutdown

(see Figure 8) 140 170 °C

Temperature
Thermal Shutdown Hyst eresis (see Figure 8) 40 °C

VIPer50-E 2 Thermal Data

2 Thermal Data

Table 8. Thermal data

Symbol Parameter PENTAWATT HV Unit

R

thJC

R

thJA

Thermal Resistance Junction-case Max 1.9 °C/W
Thermal Resi stance Ambient-case Max 60 °C/W

7/29

3 Pin Descript ion VIPer50-E

3 Pin Description

3.1 Drain Pin (Integrated Power MOSFET Drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an
integrated high voltage current source which is switched off during normal operation. The
device is able to handle an unclamped current during its normal operation, assuring self
protection against voltage surges, PCB stray inductance, and allowing a snubberless operation
for low output power.

3.2 Source Pin:

Power MOSFET source pin. Primary side circuit common ground connection.

3.3 VDD Pin (Powe r Supply):

This pin provides two functions :

● It corresponds to the low volt age supply of t he control part of the circuit. If V

8V, the start-up current source is activated and the output power MOSFET is switched off
until the V

reduced, the V
ground. After that, the current source is shut down, and the device tries to start up by

switching again.

● This pin is also connected to the error amplifier, in order to allow primary as well as

secondary regulation configurations. In case of primary regulation, an internal 13V
trimmed reference voltage is used to maintain V

voltage between 8.5V and 12.5V will be put on V
stuck the output of the transconductance amplifier to the high state. The COMP pin

behaves as a constant current source, and can easily be connected to the output of an
optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the
error amplifier through the V

will be somewhat higher than the nominal one, but still under control.

voltage reaches 11V. During this phase, the internal current consumption is

DD

pin is sourcing a current of about 2mA and the COMP pin is shorted to

DD

at 13V. For secondary regulation, a

DD

pin by transformer design, in order to

DD

voltage, which cannot overpass 13V. The output voltage

DD

goes below

DD

3.4 Compensation Pin

This pin provides two functions :

● It is the output of the error transconductance amplifier, and allows for the connection of a

compensation network to provide the desired transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the needed value with usual components value. As
stated above, secondary regulation configurations are also implemented through the
COMP pin.

● When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a

zero duty cycle for the power MOSFET. This feature can be used to switch off the
converter, and is automatically activated by the regulation loop (no matter what the
configuration is) to provide a burst mode operation in case of negligible output power or
open load condition.

8/29

VIPer50-E 3 Pin Description

FC00020

3.5 OSC Pin (Oscillator Frequency):

An Rt-Ct network must be connected on that to define the switching frequency. Note that
despite the connection of R
from 8V to 15V. It provides also a synchronisation ca pabilit y, when connected to an external
frequency source.

Figure 1. Connection Diagrams (T o p View)

to VDD, no significant frequency change occurs for VDD varying

t

PENTAWATT HV

Figure 2. Current and Voltage Convention

DD

I

VDD

IOSC

OSC

13V

OSC

V

­+

I

VCOMP

COMP SOURCE

COMP

PENTAWATT HV (022Y)

DRAINVDD

D

I

DS

V

9/29

4 T ypical Circuit VIPer50-E

4 Typical Circuit

Figure 3. Offline Power Supply With Auxiliary Supply Feedback

F1

BR1

TR1

D2

D1

C2

R1

C7

L2

+Vcc

C9

AC IN

TR2

C1

R9

D3

C4

C3

R7

R2

DRAINVDD

13V

­+

C11

VIPer50

COMP SOURCE

C6

OSC

C5

R3

Figure 4. Offline Power Supply With Optocoupler Feedback

F1

BR1

TR1

D1

C2

C4

R1

D3

C3

R7

AC IN

TR2

C1

R9

GND

C10

FC00301

D2

C10

L2

+Vcc

C9C7

GND

R2

13V

­+

C11

COMP SOURCE

C6

R3

OSC

C5

10/29

DRAINVDD

U1

VIPer100

R6

ISO1

R4

U2

C8

R5

FC00091

VIPer50-E 5 Operation Description

5 Operation Description

5.1 Current Mode Topology:

The current mode control method, like the one integrated in the VIPer50-E, uses two control
loops - an inner current control loop and an outer loop for voltage control. When the Power
MOSFET output transistor is on, the inductor current (primary side of the transformer) is
monitored with a SenseFET technique and converted into a voltage V
current. When V

reaches V

S

(the amplified output voltage error) the power switch is

COMP

switched off. Thus, the outer voltage control loop defines the level at which the inner loop
regulates peak current through the power switch and the primary winding of the transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.

Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
powe r supply on V

is no longer correct. For specific applications the maximum peak current

DD

internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.

proportional to this

S

5.2 Stand-by Mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power P

Where:

L

is the primary inductance of the transformer. FSW is the normal switching frequency.

P

I

STBY

P

STBY

is the minimum controllable current, corresponding to the minimum on time that the

device is able to provide in normal operation. This current can be computed as :

I

STBY

t

+ td is the sum of the blanking time and of the propagation time of the internal current sense

b

and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage.

1

-- -L
2

tbtd+()V

-----------------------------=

given by :

STBY

I2STBYFSW=

P

IN

L

p

11/29

5 Operation Description VIPer50-E

As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase
above the 13V regulation level, forcing the output voltage of the transconductance amplifier to
low state (V

COMP

< V

COMPth

). This situation leads to the shutdown mode where the power
switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as
V

gets back to the regulation level and the V

DD

COMPth

threshold is reached, the device
operates again. The above cycle repeats indefinitely, providing a burst mode of which the
effective duty cycle is much lower than the minimum one when in normal operation. The
equivalent switching frequency is also lower than the normal one, leading to a reduced
consumption on the input main supply lines. This mode of operation allows the VIPer50-E to
meet the new German "Blue Angel" Norm with less than 1W total power consumption for the
system when working in stand-by mode. The output voltage remains regulated around the
normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this
ripple is low, because of the output capacitors and low output current drawn in such
conditions.The normal operation resumes automat ically when the power gets back to higher
levels than P

STBY

.

5.3 High Voltage Start-up Current Suorce

An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits which are
placed into a standby mode with reduced consumption and also provided to the external
capacitor connected to the V
threshold V

of the UVLO logic, the device becomes active mode and starts switching. The

DDon

start-up current generator is switched off, and the converter should normally provide the
needed current on the V

(see Figure 11).

pin. As soon as the volt age on t his pi n reaches the high voltage

DD

pin through the auxiliary winding of the transformer, as shown on

DD

In case there are abnormal conditions where the auxiliary winding is unable to provide the low
voltage supply current to the V
external capacitor discharges to the low threshold voltage V

pin (i.e. short circuit on the output of the converter), the

DD

of the UVLO logic, and the

DDoff

device goes back to the inactive state where the internal circuits are in standby mode and the
start-up current source is activated. The converter enters a endless start-up cycle, with a start­up duty cycle defined by the ratio of charging current towards discharging when the VIPer100­E tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle
while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.

This low value start-up duty cycle prevents the application of stress to the output rectifiers as
well as the transformer when a short circuit occurs.

The external capacitor C
converter to start up, when the device starts switching. This time t

on the VDD pin must be sized according to the time needed by the

VDD

depends on many

SS

parameters, among which transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin. The following formula can be used for
defining the minimum capacitor needed:

I

where:

I

DD

C

VDD

is the consumption current on the VDD pin when switching. Refer to specified I

DDtSS

-------------------->
V

DDhyst

and IDD2

DD1

values.

is the start up time of the converter when the device begins to switch. Worst case is

t

SS

generally at full load.

12/29

VIPer50-E 5 Operation Description

V

is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).

DDhyst

The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be als o us e d a s the compens ation network . In this case , the regulation lo op bandw idth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high
performance compensation netw ork together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.

If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the V

voltage is oscillating between V

DD

This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.

5.4 Transconductance Error Amplifier

The VIPer50-E includes a transconductance error amplifier. Trans conduc tance Gm is the
change in output current (I

∂l

m

COMP

-------------------=
∂V

COMP

DD

V

∂

COMP

-------------------- -

I

∂

COMP

COMP

-------­G

G

The output impedance Z

Z

) versus change in input voltage (VDD). Thus:

COMP

at the output of this amplifier (COMP pin) can be defined as:

V

1

∂

COMP

------------------------ -×==
∂V

m

DD

DDon

and V

DDoff

.

This last equation shows that the open loop gain A

= Gm x Z

A

VOL

COMP

can be related to Gm and Z

VOL

COMP

:

where Gm value for VIPer50-E is 1.5 mA/V typically.

is defined by specification, but Z

G

m

and therefore A

COMP

are subject to large tolerances.

VOL

An impedance Z can be connected between the CO MP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):

F

= Gm x Z(S)

(S)

The error amplifier frequency response is reported in Figure 10. for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier shows
an internal Z

of about 330KΩ. More complex impedance can be connected on the COMP

COMP

pin to achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at hi gher
frequency, insuring a correct phase margin. Thi s configur ation is illustrated in Figure 20

As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to
avoid any high frequency interference.

Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.

13/29

5 Operation Description VIPer50-E

5.5 External Clock Synchronization:

The OSC pin provides a synchronisation capability when connected to an external frequency
source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.
If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is
sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through
the optotransistor.

5.6 Primary Peak Current Limitation

The primary I

current and, consequently, the output power can be limited using the

DPEAK

simple circuit shown in Figure 22 . The circuit based on Q1, R
the COMP pin in order to limit the primary peak current of the device to a value:

I

DPEAK

V

COMP

--------------------------------=

0.5–

H

ID

where:

V

COMP

The suggested value for R

0.6

1R2

-------------------×=
R

2

is in the range of 220KΩ.

1+R2

+

R

5.7 Over-Temperature Protection

Over-temperature protection is based on chip temperature sensing. The minimum junction
temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is
170ºC. The device is automatically restarted when the junction temperature decreases to the
restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)

and R2 clamps the voltage on

1

14/29

VIPer50-E 5 Operation Description

I

DD

I

D

V

V

0

(

140

(

5.8 Operation Pictures

Figure 5. VDD Regulation Point Figure 6. Undervoltage Lockout

I

COM P

I

COMPHI

0

COMPLO

Figure 7. Tr an sition Time Figure 8. Shutdown Action

Slope =

G m i n mA/V

V

DDreg

FC00150

V

I

DD

DD0

I

DDch

VOSC

DDhyst

V

V

DDoff

VDS= 35 V

Fsw = 0

DDon

V

FC00170

V

D

ID

10% Ipeak

DS

90% V D

D

10% V

tf

t

t

tr

FC00160

VCOMP

COMPth

ID

tDISsu

ENABLE

DISABLE

t

t

t

ENABLE

FC0006

Figure 9. Breakdown Voltage vs. Temperature Figure 10. Typical Frequency Variation

1.15

BVDSS

Normalized)

1.05

0.95

1.1

1

0 20406080100120

Temperature (°C)

FC00180

1

%)

0

-1

-2

-3

-4

-5
0 20 40 60 80 100 120

Temperature (°C)

FC00190

15/29

5 Operation Descri ption VIPer50-E

V

0

Figure 11. Behaviour of the high voltage current source at start-up

VDD

VDDon

DDoff

t

Auxiliary primary

Figure 12. Start-Up W aveforms

winding

2 mA

15 mA

VDD

C

VDD

15 mA1 mA

Ref.

UNDERVOLTAGE
LOCK OUT LOGIC

3 mA

VIPer50

Start up duty cycle ~ 12%

DRAIN

SOURCE

FC0032

16/29

VIPer50-E 5 Operation Descri ption

0

00000000

0

0

0

0000
0

0

0

0

0

0
0

0

000
000

00
00

000
000

0

0

000
000

000

000
000

0

0

0

0

0

000
000

00

000
000

0

000
000

00
00

000

00
00
00
00
00
00

00000
00000
00000
00000
00000
00000

0
0
0
0
0
0

00000
00000
00000
00000
00000
00000

0
0
0

00000
00000
00000
00000

00
00
00
00
00

00000
00000
00000
00000
00000
00000

0
0
0
0
0
0

000000
000000
000000
000000
000000
000000

000000000

0
0

SC 101 91

T

T

t

t

t

t

Figure 13. Over-temperature Protection

J

T

ts c

tsd-Th yst

V

dd

V

dd on

V

dd off

I

d

V

comp

17/29

5 Operation Descri ption VIPer50-E

C

C

w

Figure 14. Oscillator

Rt

VDD

OSC

F

CLK

t

Ω

SW

2.3

-----------1

⋅=

R

tCt

550

⎛⎞

--------------------–

⎝⎠

R

150–

t

~360

FC00050

t

Forbidden area

For Rt > 1.2kΩ and Ct ≤ 40KHz

22nF

Ct(nF) =

15nF

880

Fsw(kHz)

1,000

500

300
200

100

Frequency (kHz)

Forbidden area

40kHz

Oscillator frequency vs Rt and Ct

FC00030FC00030

Ct = 1.5 nF

Ct = 2.7 nF

Ct = 4.7 nF

Ct = 10 nF

50

30

1 2 3 5 10 20 30 50

Rt (kΩ)

Fs

18/29

VIPer50-E 5 Operation Descri ption

0

0

Figure 15. Error Amplifier frequency Response

FC00200

60

RCOMP = +
RCOMP = 270k

40

RCOMP = 82k

RCOMP = 27k
RCOMP = 12k

20

Voltage Gain (dB)

0

∞

(20)

0.001 0.01 0.1 1 10 100 1,00

Frequency (kHz)

Figure 16. Error Amplifier Phase Response

200

RCOMP = +
RCOMP = 270k

RCOMP = 82k

RCOMP = 27k
RCOMP = 12k

Phase (°)

150

100

50

0

(50)

0.001 0.01 0.1 1 10 100 1,00

Frequenc y ( k Hz )

FC00210

∞

19/29

5 Operation Descri ption VIPer50-E

Y

Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down

D2

VIPer50

OSC

C3

+

­+

13V

C4

DRAINVDD

COMP SOURCE

R1

C1

D1

D3

R3

AUXILIAR
WINDING

R2

C2

+

Shutdow n

Q2

R4

R1

OSC

13V

R2R3

Q1

D1

FC00331

Figure 19. Typical Compensation Network Figure 20. Slo pe Compensation

VIPer50

DRAINVDD

OSC

13V

-

+

C2

COMP SOURCE

R1

C1

R1R2

OSC

Q1

13V

­+

C2

VIPer5 0

COMP SOURCE

C3

VIPer50

-

+

DRAINVDD

DRAINVDD

COMP SOURCE

FC00340

C1 R3

FC00351

FC00361

Figure 21. Ex te rnal Clock Sin chronisati on Figure 22. Current Limitation Ci rc u it Example

VIPer50

DRAINVDD

13V

-

+

COMP SOURCE

R1

Q1

R2

FC003 80

10 kΩ

OSC

13V

VIPer50

­+

OSC

DRAINVDD

COMP SOURCE

FC00370

20/29

VIPer50-E 6 Electrical Over S tr ess

B

g

6 Electrical Over Stress

6.1 Electrical Over Stress Ruggedness

The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or
lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages
most of the time. However in some cases, the voltage surges coupled through the transformer
auxiliary winding can exceed the V
may trigger the V
discharge current of the V

internal protection circuitry which could be damaged by the strong

DD

bulk capacitor. The simple RC filter shown in Figure 23 can be

DD

implemented to improve the application immunity to such surges.

Figure 23. Input Vol tage Surges Protecti on

pin absolute maximum rating voltage value. Such events

DD

C1

ulk capacitor

C2

22nF

OSC

VIPerXX0

13V

R2
39R

VDD

D1

Auxilliary windin

R1

(Optional)

DRAIN

-

+

COMP

SOURCE

21/29

7 Layout VIPer50-E

d

d

7 Layout

7.1 Layout Considerations

Some simple rules insure a correct running of switching power supplies. They may be
classified into two categories:

– Minimizing power loops: The switched power current must be carefully analysed and

the corresponding paths must be as small an inner loop area as possible. This avoids
radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic inductances, especially on secondary side.

– Using different tracks for low level and power signals: Interference due to mixing of

signal and power may result in instabilities and/or anomalous behaviour of the device
in case of violent power surge (Input overvoltages, output short circuits...).

In case of VIPer, these rules apply as shown on (see Figure 24).

– Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized.
– C6 must be as close as possible to T1.
– Signal components C2, ISO1, C3, and C4 are using a dedicated track connected

directly to the power source of the device.

Figure 24. Recommended Layout

R1

C1

From input
iodes bridge

C2

OSC

U1
VIPerXX0

13V

ISO1

­+

COMP SOURCE

C3

T1

D2

DRAINVDD

C5

R2

C4

D1

To s econdary

C7

filtering and loa

C6

FC00500

22/29

VIPer50-E 8 Package Mechanical Data

8 Package M echanical Da ta

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com.

23/29

8 Package Mechani cal D at a VIPer50-E

Pentawatt HV Mechanical Data

mm. inch

Dim

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.11

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409

L 15.60 17.30 6.14 0.681

L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 4.50 5.60 0.177 0.220

R0.50 0.02

V4 90

°

Diam 3.65 3.85 0.144 0.152

24/29

P023H3

VIPer50-E 8 Package Mechanical Data

Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data

mm. inch

Dim

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409

L 16.42 17.42 0.646 0.686

L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 5.00 5.70 0.197 0.224

R 0.50 0.02 0.020

V4 90

° 90°

Diam 3.65 3.85 0.144 0.154

L

E

M1

M

R

Resin between

leads

G2

V4

G1

L1

A

D

L6

C

L7

H2

H3

H1

F

DIA

L3

L5

25/29

8 Package Mechani cal D at a VIPer50-E

Figure 25. Pentawatt HV Tube Shipment ( no suffix )

Base Q.ty 50
Bulk Q.ty 1000

T ube length ( ± 0.5 ) 532

A 18
B 33.1

C ( ± 0. 1) 1

All dim e nsions ar e i n mm.

26/29

VIPer50-E 9 Order Codes

9 Order Codes

PENT AWATT HV PENTAWATT HV (022Y)

VIPer50-E VIPer50-22-E

27/29

10 Revision history VIPer50-E

10 Revision history

Date Revision Changes

26-Sep-2005 1 Initial release.

28/29

VIPer50-E 10 Revision history

I

s

o

d

b

ct

t

ot

a

nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence

f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grante
y implic ation or otherwise u nder any pat ent or pat ent rights of STMicro el ectronics . Specificati ons menti oned in this publicati on are subje

o change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are n

uthoriz ed for use as critical compo nents in life support devices or systems without express written approval of STMicroel ectronics.

The ST logo is a registered t rademark of ST M i croelectroni cs.

All other nam es are the pro perty of their respectiv e owners

© 2005 STMi croelectro ni cs - All rights reserved

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29/29