ST VIPer20A-E User Manual

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General features

I

Typ e

VIPer20A-E

VIPer20ASP-E

VIPer20ADIP-E

V

DSS

700V
700V
700V

0.5A

0.5A

0.5A

R

n

DS(on)

18
18Ω
18Ω

VIPer20A-E

SMPS primary I.C.

Ω

PENTAWATT HV

DIP-8

■ Adjustable switching frequency up to 200 kHz

■ Current mode control

■ Soft start and shutdown control

■ Automatic burst mode operation in stand-by

condition able to meet “blue angel” norm (<1w
total power consumption)

■ Internally trimmed zener reference

■ Undervoltage lock-out with hysteresis

■ Integrated start-up supply

■ Over-temperature protection

■ Low stand-by current

■ Adjustable current limitation

Block diagram

10

1

PENTAWATT HV (022Y)

POWERSO-10

TM

Description

All the devices are made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized, high voltage, Vertical Power MOSFET
(700V/ 0.5A).

Typical applications cover offline power supplies
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the ability to operate in stand-by mode
without extra components.

OSC

DRAIN

ON/OFF

SECURITY

LATCH

ERROR

AMPLIFIER

UVLO
LOGIC

0.5 V

R/SSQ

OVERTEMP.

DETECTOR

delay

1.7

µ

+

_

4.5 V

VDD

_

13 V

+

OSCILLATOR

PWM

LATCH

S
FFFF

R1

Q

R2 R3

0.5V
_

+

+

6 V/A

_

CURRENT

AMPLIFIER

FC00491

SOURCE

COMP

250 ns

Blanking

s

June 2006 Rev 2 1/34

www.st.com

34

Contents VIPer20A-E

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Drain pin (Integrated Power MOSFET drain): . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Source pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 VDD pin (power supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Compensation pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.5 OSC pin (oscillator frequency): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Current mode topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.3 High voltage start-up current suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 External clock synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Primary peak current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7 Over-temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/34

VIPer20A-E Contents

6 Electrical over stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Electrical over stress ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3/34

Electrical data VIPer20A-E

1 Electrical data

1.1 Maximum rating

Table 1. Absolute maximum rating

Symbol Parameter Value Unit

V

I

V

V

OSC

V

COMP

I

COMP

V

ESD

I

D(AR)

P

TOT

T

T

STG

DS

D

DD

Continuous Drain-Source Voltage (TJ = 25 to 125°C)

–0.3 to 700 V

Maximum Current Internally limited A

Supply Voltage 0 to 15 V

Voltage Range Input

0 to V

DD

V

Voltage Range Input 0 to 5 V

Maximum Continuous Current ±2mA

Electrostatic Discharge (R = 1.5kΩ; C = 100pF) 4000 V

Avalanche Drain-Source Current, Repetitive or Not Repetitive

= 100°C; Pulse width limited by TJ max; δ < 1%)

(T

C

Power Dissipation at TC= 25ºC

Junction Operating Temperature Internally limited ° C

J

0.4 A

57 W

Storage Temperature -65 to 150 °C

4/34

VIPer20A-E Electrical data

1.2 Electrical characteristics

TJ = 25°C; VDD = 13V, unless otherwise specified

Table 2. Power section

Symbol Parameter Test conditions Min Typ Max Unit

BV

I

DSS

R

DS(on)

t

t

C

oss

(1) On Inductive Load, Clamped.

Drain-Source Voltage

DS

Off-State Drain
Current

Static Drain-Source
On Resistance

Fall Time

f

Rise Time

r

Output Capacitance

I

= 1mA; V

D

V

V

= 0V; Tj = 125°C

COMP

= 700V

DS

ID = 0.4A

= 0.4A; TJ= 100°C

I

D

= 0.2A; V

I

D

ID = 0.4A; V

= 25V 90 pF

V

DS

= 0V 700 V

COMP

15.5 18

=300V

IN

= 300V

IN

(1)

Figure 7

(1)

Figure 7

100 ns

50 ns

1.0 mA

32

Table 3. Supply section

Symbol Parameter Test conditions Min Typ Max Unit

I

DDch

I

DD0

I

DD1

I

DD2

V

DDoff

V

DDon

V

DDhyst

Start-Up Charging Current V

Operating Supply Current V

Operating Supply Current V

Operating Supply Current V

Undervoltage Shutdown

Undervoltage Reset

Hysteresis Start-up

= 5V; VDS = 35V

DD

Figure 6, Figure 11

= 12V; F

DD

SW

= 0kHz

Figure 6

= 12V; F

DD

= 12V; F

DD

= 100kHz

sw

= 200kHz

sw

-2 mA

12 16 mA

13 mA

14 mA

Figure 6 7.5 8 9 V

Figure 6 11 12 V

Figure 6 2.4 3 V

Ω
Ω

Table 4. Oscillator section

Symbol Parameter Test conditions Min Typ Max Unit

=8.2KΩ; CT=2.4nF

R

T

=9 to 15V;

F

V

OSCIH

V

OSCIL

SW

Oscillator Frequency Total
Variat ion

Oscillator Peak Voltage 7.1 V

Oscillator Valley Voltage 3.7 V

V

DD

± 1%; CT± 5%

with R

T

(see Figure )(see Figure 14)

90 100 110 KHz

5/34

Electrical data VIPer20A-E

Table 5. Error amplifier section

Symbol Parameter Test conditions Min Typ Max Unit

V

DDREGVDD

∆V

DDreg

G

BW

Regulation Point I

Total Variation

Unity Gain Bandwidth

=0mA (see Figure 5)

COMP

= 0 to 100°C

T

J

From Input =V

Output = V

DD

COMP

to

COMP pin is open

12.6 13 13.4 V

2%

150 KHz

Figure 15

A

VOL

G

V

COMPLO

V

COMPHI

I

COMPLO

I

COMPHI

Open Loop Voltage Gain

DC Transconductance

m

Output Low Level

Output High Level

Output Low Current Capability

Output High Current
Capability

COMP pin is open

Figure 15

=2.5V(see Figure 5)

V

COMP

=-400µA; VDD=14V

I

COMP

=400µA; VDD=12V

I

COMP

V

=2.5V; VDD=14V

COMP

V

=2.5V; VDD=12V

COMP

45 52 dB

1.1 1.5 1.9 mA/V

0.2 V

4.5 V

-600 µA

600 µA

Table 6. PWM comparator section

Symbol Parameter Test conditions Min Typ Max Unit

H

V

COMPoffVCOMP

I

Dpeak

t

∆V

ID

COMP

/ ∆I

DPEAK

Offset I

Peak Current Limitation

Current Sense Delay to Turn-

d

Off

V

= 1 to 3 V

COMP

= 10mA

DPEAK

= 12V; COMP pin open

V

DD

ID = 1A

4.267.8V/A

0.5 V

0.50.670.9 A

250 ns

t

t

on(min)

Blanking Time 250 360 ns

b

Minimum On Time 350 1200 ns

Table 7. Shutdown and overtemperature section

Symbol Parameter Test conditions Min Typ Max Unit

V

COMPth

t

DISsu

T

tsd

T

hyst

6/34

Restart Threshold (see Figure 8) 0.5 V

Disable Set Up Time (see Figure 8) 1.7 5 µs

Thermal Shutdown
Temperature

(see Figure 8) 140 170 190 °C

Thermal Shutdown Hysteresis (see Figure 8) 40 °C

VIPer20A-E Thermal data

2 Thermal data

Table 8. Thermal data

Symbol Parameter PENTAWATT

PowerSO-10™

(1)

DIP-8 Unit

R

R

R

1. When mounted using the minimum recommended pad size on FR-4 board.

2. On multylayer PCB.

Thermal Resistance Junction-pin Max 20 °C/W

thJA

Thermal Resistance Junction-case Max 2.0 2.0 °C/W

thJC

Thermal Resistance Ambient-case Max 70 60

thJC

35

(2)

°C/W

7/34

Pin description VIPer20A-E

3 Pin description

3.1 Drain pin (Integrated Power MOSFET drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an
integrated high voltage current source which is switched off during normal operation. The
device is able to handle an unclamped current during its normal operation, assuring self
protection against voltage surges, PCB stray inductance, and allowing a snubberless operation
for low output power.

3.2 Source pin:

Power MOSFET source pin. Primary side circuit common ground connection.

3.3 VDD pin (power supply):

This pin provides two functions :

● It corresponds to the low voltage supply of the control part of the circuit. If V

8V, the start-up current source is activated and the output power MOSFET is switched off
until the V

reduced, the V
ground. After that, the current source is shut down, and the device tries to start up by

switching again.

● This pin is also connected to the error amplifier, in order to allow primary as well as

secondary regulation configurations. In case of primary regulation, an internal 13V
trimmed reference voltage is used to maintain V

voltage between 8.5V and 12.5V will be put on V
stuck the output of the transconductance amplifier to the high state. The COMP pin

behaves as a constant current source, and can easily be connected to the output of an
optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the
error amplifier through the V

will be somewhat higher than the nominal one, but still under control.

voltage reaches 11V. During this phase, the internal current consumption is

DD

pin is sourcing a current of about 2mA and the COMP pin is shorted to

DD

at 13V. For secondary regulation, a

DD

pin by transformer design, in order to

DD

voltage, which cannot overpass 13V. The output voltage

DD

goes below

DD

3.4 Compensation pin

This pin provides two functions :

● It is the output of the error transconductance amplifier, and allows for the connection of a

compensation network to provide the desired transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the needed value with usual components value. As
stated above, secondary regulation configurations are also implemented through the
COMP pin.

● When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a

zero duty cycle for the power MOSFET. This feature can be used to switch off the
converter, and is automatically activated by the regulation loop (no matter what the
configuration is) to provide a burst mode operation in case of negligible output power or
open load condition.

8/34

VIPer20A-E Pin description

3.5 OSC pin (oscillator frequency):

An Rt-Ct network must be connected on that to define the switching frequency. Note that
despite the connection of R
from 8V to 15V. It provides also a synchronisation capability, when connected to an external
frequency source.

Figure 1. Connection diagrams (top view)

to VDD, no significant frequency change occurs for VDD varying

t

PENTAWATT HV

PENTAWATT HV (022Y)

Figure 2. Current and voltage convention

IDD ID

IOSC

OSC

13V

VDD

VOSC

-

+

VCOMP

COMP SOURCE

ICOMP

DIP-8

DRAINVDD

VDS

FC00020

PowerSO-10

TM

9/34

Typical circuit VIPer20A-E

4 Typical circuit

Figure 3. Offline power supply with auxiliary supply feedback

F1

BR1

TR1

D2

D1

C2

R1

C7

L2

+Vcc

C9

AC IN

TR2

C1

R9

D3

C4

C3

R7

R2

DRAINVDD

13V

-

+

C11

COMP SOURCE

C6

OSC

C5

R3

Figure 4. Offline power supply with optocoupler feedback

AC IN

F1

TR2

C1

R9

BR1

D1

C2

C4

R1

D3

C3

R7

VIPer20

TR1

GND

C10

FC00401

D2

C7

C10

L2

C9

+Vcc

GND

R2

13V

-

+

COMP SOURCE

C11

OSC

C5

10/34

DRAINVDD

VIPer20

C6

R3

R6

ISO1

R4

U2

C8

R5

FC00411

VIPer20A-E Operation description

5 Operation description

5.1 Current mode topology:

The current mode control method, like the one integrated in the devices, uses two control loops

- an inner current control loop and an outer loop for voltage control. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored with a
SenseFET technique and converted into a voltage V
reaches V

(the amplified output voltage error) the power switch is switched off. Thus, the

COMP

outer voltage control loop defines the level at which the inner loop regulates peak current
through the power switch and the primary winding of the transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.

Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
power supply on V

is no longer correct. For specific applications the maximum peak current

DD

internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.

proportional to this current. When VS

S

5.2 Stand-by mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power P

1

Where:

is the primary inductance of the transformer. FSW is the normal switching frequency.

L

P

I

STBY

P

STBY

is the minimum controllable current, corresponding to the minimum on time that the

device is able to provide in normal operation. This current can be computed as :

I

STBY

t

+ td is the sum of the blanking time and of the propagation time of the internal current sense

b

and comparator, and represents roughly the minimum on time of the device. Note: that P
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage.

-- -

L

2

tbtd+()V

-----------------------------=

given by :

STBY

I2STBYFSW=

P

IN

L

p

STBY

11/34