ST VIPER15 User Manual

Features
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800 V avalanche rugged power section
Quasi-resonant (QR) control for valley
Standby power < 50 mW at 265 Vac
Limiting current with adjustable set point
Adjustable and accurate overvoltage
protection
On-board soft-start
Safe auto-restart after a fault condition
Hysteretic thermal shutdown
Applications
Adapters for PDA, camcorders, shavers,
cellular phones, cordless phones, videogames
Auxiliary power supply for LCD/PDP TV,
monitors, audio systems, computer, industrial systems, LED driver, No el-cap LED driver, utility power meter
SMPS for set-top boxes, DVD players and
recorders, white goods
VIPER15
Off-line high voltage converters
SO16 narrow
-
Description
The device is an off-line converter with an 800 V rugged power section, a PWM control, double levels of overcurrent protection, overvoltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. Burst mode operation and device very low consumption helps to meet the standby energy saving regulations. The quasi­resonant feature reduces EMI filter cost. Brown­out and brown-in function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. The high voltage start-up circuit is embedded in the device.

Figure 1. Typical topology

DIP-7

Table 1. Device summary

VIPER15HDTR / VIPER15LDTR Tape and reel
August 2010 Doc ID 15455 Rev 5 1/40
Order codes Package Packaging
VIPER15LN / VIPER15HN DIP-7 Tube
VIPER15HD / VIPER15LD
SO16 narrow
Tube
www.st.com
40
Contents VIPER15
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Power-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 Power-down description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5 Auto-restart description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6 Quasi-resonant operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 Frequency foldback function and valley skipping mode . . . . . . . . . . . . . . 22
7.8 Double blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.9 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.10 Current limit set point and feed-forward option . . . . . . . . . . . . . . . . . . . . . 24
7.11 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.12 Summary on ZCD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.13 Feedback and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.14 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 32
7.15 Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.16 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 34
2/40 Doc ID 15455 Rev 5
VIPER15 Contents
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Doc ID 15455 Rev 5 3/40
Block diagram VIPER15

1 Block diagram

Figure 2. Block diagram

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2 Typical power

Table 2. Typical power

Part number
VIPER15 9 W 10 W 5 W 6 W
1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.
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230 V
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4/40 Doc ID 15455 Rev 5
VIPER15 Pin settings

3 Pin settings

Figure 3. Connection diagram (top view)

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Note: The copper area for heat dissipation has to be designed under the DRAIN pins.

Table 3. Pin description

Pin n.
Name Function
DIP-7 SO16
1 1...2 GND This pin represents the device ground and the source of the power section.
-4N.A.
25VDD
Not available for user. It can be connected to GND (pins 1-2) or left not connected.
Supply voltage of the control section. This pin also provides the charging current of the external capacitor during power-up.
This is a multifunction pin.
1. Input for the zero current detection circuit for transformer demagnetization sensing. (i.e. R
LIM
, RFF, R
OVP
and D
, Figure 32)
OVP
2. User defined drain current limit set-point and voltage feed forward.The resistor, R I
36ZCD
ZCD
3. The resistor R
and then it limits the static maximum drain current.
, connected between ZCD pin and GND causes the current
LIM
, between ZCD pin and the auxiliary winding, performs
FF
the feed-forward operation and then the drain current limitation changes according to the converter input voltage.
4. Output overvoltage protection. A voltage exceeding V
threshold,
OVP
(see Table 8 on page 8), shuts the IC down reducing the device consumption. This function is strobed and digitally filtered for high noise immunity.
Control input for duty cycle control. Internal current generator provides bias
47FB
current for loop regulation. A voltage below the threshold V the burst-mode operation. A level close to the threshold V
FBbm
means that
FBlin
activates
we are approaching the cycle-by-cycle overcurrent set point.
Brownout protection input with hysteresis. A voltage below the threshold
shuts down (not latch) the device and lowers the power consumption.
V
58BR
BRth
Device operation restarts as the voltage exceeds the threshold V
. It can be connected to ground when not used.
V
BRhyst
BRth
+
High voltage drain pin. The built-in high voltage switched start-up bias
7,8 13...16 DRAIN
current is drawn from this pin too. Pins connected to the metal frame to facilitate heat dissipation.
Doc ID 15455 Rev 5 5/40
Electrical data VIPER15

4 Electrical data

4.1 Maximum ratings

Table 4. Absolute maximum ratings

Symbol
V
DRAIN
E
AV
I
AR
I
DRAIN
V
ZCD
V
FB
V
BR
V
DD
I
DD
P
TOT
T
J
T
STG
Pin
(DIP7)
Parameter
Val ue
Min. Max.
7, 8 Drain-to-source (ground) voltage 800 V
Repetitive avalanche energy
7, 8
(limited by T
Repetitive avalanche current
7, 8
(limited by T
= 150 °C)
J
= 150 °C)
J
2mJ
1A
7, 8 Pulse drain current (limited by TJ = 150 °C) 2.5 A
3 Control input pin voltage (with I
= 1 mA) -0.3 Self limited V
ZCD
4 Feedback voltage -0.3 5.5 V
5 Brown-out input pin voltage (with IBR = 0.5 mA) -0.3 Self limited V
2 Supply voltage (IDD = 25 mA) -0.3 Self limited V
2 Input current 25 mA
Power dissipation at TA < 40 °C (DIP-7) 1 W
Power dissipation at T
< 60 °C (SO16N) 1 W
A
Operating junction temperature range -40 150 °C
Storage temperature -55 150 °C
Unit

4.2 Thermal data

Table 5. Thermal data

Symbol Parameter
R
R
R
1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 μm thick)
6/40 Doc ID 15455 Rev 5
Thermal resistance junction pin
thJP
(Dissipated power = 1 W)
Thermal resistance junction ambient
thJA
(Dissipated power = 1 W)
Thermal resistance junction ambient
thJA
(Dissipated power = 1 W)
(1)
Max. value
SO16N
Max. value
DIP7
35 40 °C/W
90 110 °C/W
80 90 °C/W
Unit
VIPER15 Electrical data

4.3 Electrical characteristics

(TJ = -25 to 125 °C, VDD = 14 V

Table 6. Power section

Symbol Parameter Test condition Min. Typ. Max. Unit
V
BVDSS
I
OFF
R
DS(on)
C
OSS

Table 7. Supply section

Symbol Parameter Test condition Min. Typ. Max. Unit
Break-down voltage
OFF state drain current
Drain-source on state resistance
Effective (energy related) output capacitance
(a)
; unless otherwise specified)
I
= 1 mA, VFB = GND
DRAIN
TJ = 25 °C
V
V
I
= max rating,
DRAIN
= GND
FB
= 0.2 A, VFB = 3 V,
DRAIN
VBR = GND, TJ = 25 °C
I
= 0.2 A, VFB = 3 V ,
DRAIN
VBR = GND, TJ = 125 °C
= 0 to 640 V 10 pF
V
DRAIN
800 V
60 μA
20 24 Ω
40 48 Ω
Volt ag e
V
DRAIN
Drain-source start voltage 60 80 100 V
_START
= 120 V,
V
DRAIN
VBR = GND, VFB = GND,
-2 -3 -4 mA
VDD = 4 V
I
DDch
V
DD
V
DDclamp
V
DDon
V
DDoff
V
DD(RESTART)
Start-up charging current
V
= 120 V,
DRAIN
VBR = GND, VFB = GND,
= 4 V after fault.
V
DD
-0.4 -0.6 -0.8 mA
Operating voltage range After turn-on 8.5 23.5 V
VDD clamp voltage IDD = 20 mA 23.5 V
VDD start-up threshold
VDD under voltage shutdown threshold
VDD restart voltage threshold
V
V
V
V
= 120 V,
DRAIN
= GND, VFB = GND
BR
= 120 V,
DRAIN
= GND, VFB = GND
BR
13 14 15 V
7.588.5V
44.55 V
Current
I
DD0
I
DD1
I
DD_FAULT
I
DD_OFF
Operating supply current, not switching
Operating supply current, switching
Operating supply current, with protection tripping
Operating supply current with V
DD
< V
DDoff
VFB = GND, FSW = 0 k H z , VBR = GND, VDD = 10 V
V
= 120 V, 2.5 mA
DRAIN
0.9 mA
400 μA
VDD = 7 V 270 μA
a. Adjust VDD above V
start-up threshold before settings to 14 V.
DDon
Doc ID 15455 Rev 5 7/40
Electrical data VIPER15

Table 8. Controller section

Symbol Parameter Test condition Min. Typ. Max. Unit
Feedback pin
V
FBolp
V
FBlin
V
FBbm
V
FBbmhys
I
FB
R
FB(DYN)
H
FB
Overload shutdown threshold 4.5 4.8 5.2 V
Linear dynamics upper limit 3.2 3.3 3.4 V
Burst mode threshold Voltage falling 0.4 0.45 0.5 V
Burst mode hysteresis Voltage rising 50 mV
Feedback sourced current
Dynamic resistance V
ΔVFB / ΔI
ZCD pin
V
ZCDCLh
V
ZCDAth
V
ZCDTth
I
ZCD
T
BLANK
Upper clamp voltage I
Arming voltage threshold Positive-going edge 0.8 V
Triggering voltage threshold Negative-going edge 0.6 V
Internal pull-up -2 µA
Turn-on inhibit time after MOSFET’s turn-off
Current limitation
I
Dlim
Max drain current limitation
V
= 0.3 V -150 -200 -280 uA
FB
3.3 V < V
FB
D
ZCD
V
ZCD
V
ZCD
< 4.8 V -3 uA
FB
< 3.3 V 14 19 kΩ
26V/A
= 1 mA 5 5.5 6 V
< 1 V 6.3 µs
>1 V 2.5 µs
VFB = 4 V, I
= -10 µA
ZCD
0.38 0.4 0.42 A
TJ = 25 °C
t
SS
t
SU
T
ON_MIN
Soft start time
Start up time
Minimum turn ON time 220 400 480 ns
td Propagation delay 100 ns
t
LEB
I
D_BM
Overcurrent protection (2
I
DMAX
Overvoltage protection
V
OVP
T
STROBE
Leading edge blanking 300 ns
Peak drain current during burst mode
nd
OCP)
Second overcurrent threshold 0.6 A
Overvoltage protection threshold
Overvoltage protection strobe time
8/40 Doc ID 15455 Rev 5
VIPER15L 3.5 ms
VIPER15H 4.2 ms
VIPER15L 7.5 15 ms
VIPER15H 9.5 18 ms
V
= 0.6 V 90 mA
FB
3.8 4.2 4.6 V
2.2 μs
VIPER15 Electrical data
Table 8. Controller section (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Oscillator section
F
OSClim
F
STARTER
F
OSCmin
Internal frequency limit VIPER15H 200 225 250 kHz
Starter frequency
Brown-out protection
Internal frequency limit VIPER15L 122 136 150 kHz
V
BRth
V
BRhyst
I
BRhyst
V
BRclamp
V
DIS
Brown-out threshold Voltage falling 0.41 0.45 0.49 V
Voltage hysteresis above V
BRth
Current hysteresis 7 12 μA
Clamp voltage IBR = 250 µA 3 V
Brown-out disable voltage 50 150 mV
Thermal shutdown
T
SD
Thermal shutdown temperature
=1 V,
V
FB
V
ZCD<VZCDT th
t<tSU
VFB=1 V, V
ZCD<VZCDT th
t>tSU
VFB = 1 V, V
ZCD>VZCDA_th
1/4
F
OSClim
1/8
F
OSClim
1/64
F
OSClim
kHz
kHz
kHz
Violate rising 50 mV
150 160 °C
T
HYST
Thermal shutdown hysteresis 30 °C
Doc ID 15455 Rev 5 9/40
Electrical data VIPER15

Figure 4. Minimum turn-on time test circuit

V
DRAIN
GND
14 V
3.5 V
VDD
ZCD
FB
DRAIN
DRAIN
50 Ω
BR
30 V
90 %
10 %
I
Dlim
I
DRAIN
T
ONmin
Time
Time

Figure 5. Brown-out threshold test circuits

V
BRth+VBRhyst
V
BRth
V
I
BRhyst
DIS
I
DRAIN
BR
I
BR
Time
Time
14 V
GND
VDD
ZCD
FB
DRAIN
DRAIN
I
BRhyst
BR
10 kΩ
V
30 V
2 V
Note: Adjust V

Figure 6. OVP threshold test circuits

GND
DRAIN
VDD
DRAIN
14 V
above V
DD
start-up threshold before settings to 14 V
DDon
2 V
ZCD
FB
BR
10 kΩ
30 V
Time
V
ZCD
V
OVP
V
DRAIN
Time
Time
10/40 Doc ID 15455 Rev 5
VIPER15 Typical electrical characteristics

5 Typical electrical characteristics

Figure 7. Current limit vs TJ Figure 8. Drain start voltage vs T
J
Figure 9. HFB vs T
Figure 11. Brown-out hysteresis vs T
J
J
Figure 10. Brown-out threshold vs T
J
Figure 12. Brown-out hysteresis current
vs T
J
Doc ID 15455 Rev 5 11/40
Typical electrical characteristics VIPER15
Figure 13. Operating supply current
(no switching) vs T
J
Figure 14. Operating supply current
(switching) vs T
J
Figure 15. V
V
(mV )
ZCD
500
450
400
350
300
0.0 50.0 100.0 150.0 200.0 250.0
ZCD
vs I
I
ZCD
ZCD
(μA)
Figure 17. Power MOSFET on-resistance
vs T
J
Figure 16. Current limit vs I
ZCD
Figure 18. Power MOSFET break down
voltage vs T
J
12/40 Doc ID 15455 Rev 5
VIPER15 Typical electrical characteristics

Figure 19. Thermal shutdown

V
DD
V
DDon
V
DDoff
V
DD(RESTART)
T
SD
I
DRAIN
T
J
T
SD
- T
HYST
Normal operation
Shut down after over temper ature
Normal operation
time
time
time
Doc ID 15455 Rev 5 13/40
Typical circuits VIPER15

6 Typical circuits

Figure 20. Min-features QR flyback application

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14/40 Doc ID 15455 Rev 5
VIPER15 Operation description

7 Operation description

VIPER15 is a high-performance low-voltage PWM controller IC with an 800 V, avalanche rugged power section.
The controller includes the current-mode PWM logic and the ZCD (zero current detect) circuit for QR operation, the start-up circuitry with soft-start feature, an oscillator for frequency foldback function, the current limit circuit with adjustable set point, the second overcurrent circuit, the burst mode management circuit, the brown-out circuit, the UVLO circuit, the auto-restart circuit and the thermal shutdown circuit.
The current limit set-point is set by the ZCD pin. The burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment
All the fault protections are built in auto-restart mode with very low repetition rate to prevent IC's over heating.

7.1 Power section and gate driver

The power section is implemented with an avalanche ruggedness N-channel MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The power section has a BV of 20 Ω at 25 °C.
of 800 V min. and a typical R
DSS
DS(on)
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn­off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the Power section cannot be turned on accidentally.

7.2 High voltage startup generator

The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than V
page 7. When the HV current generator is ON, the I
delivered to the capacitor on the V the I phase.
current is reduced to 0.6 mA, in order to have a slow duty cycle during the restart
DDch
DRAIN_START
pin. In case of Auto-restart mode after a fault event,
DD
threshold, reported on Table 7 on current (see Table 7 on page 7) is
DDch
Doc ID 15455 Rev 5 15/40
Operation description VIPER15

7.3 Power-up description

If the input voltage rises up till the device start level, VDRAIN_START, the VDD voltage begins to grow due to the I start-up circuit. If the V power MOSFET starts switching and the HV current generator is turned OFF, see Figure 23
on page 17.
current (see Table 7 on page 7) coming from the internal high voltage
DDch
voltage reaches the V
DD
threshold (See Table 7 on page 7) the
DDon
The IC is powered by the energy stored in the capacitor on the VDD pin, C
, until when
VDD
the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation.
C
capacitor must be sized enough to avoid fast discharge and keep the needed voltage
VDD
value higher than V
threshold. In fact, a too low capacitance value could terminate the
DDoff
switching operation before the controller receives any energy from the auxiliary winding.
The following formula can be used for the V
capacitor calculation:
DD
Equation 1
tI
SSauxDDch
VV
DDoffDDon
The t
C
=
VDD
is the time needed for the steady state of the auxiliary voltage. This time is
SSaux
estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.).
During normal operation, the power MOSFET is switched ON immediately after transformer demagnetization, detected by the VIPER15, through the voltage V pin. At power up the initial output voltage is zero and then the voltage V
sensed on the ZCD
ZCD
is not high
ZCD
enough to correctly arm the internal ZCD circuit. In this case, the power MOSFET is turned ON with a fixed frequency determined by the internal oscillator. This fixed switching frequency is F
STARTER
to arm the ZCD circuit (i.e. its positive value exceeds V
(see Table 8 on page 8). As soon as the voltage on ZCD pin is able
), the turn-on of the power
ZCDAth
MOSFET is driven by this circuit and is no more related to the internal oscillator (except for the frequency fold-back function).
The start-up phase is managed by a dedicated internal logic and is activated every time the device exits from UVLO because the V timing (t
, see Table 8 on page 8) defines the end of the start-up phase.
SU
During the first part of the start-up phase soft start takes place: the drain peak current is increased cycle-by-cycle from zero as far as the maximum value, I
Figure 25 on page 18). The duration of soft-start is t
During soft-start and until the output voltage reaches its regulated value, the feedback loop is open. To prevent an improper activation of the OLP function (see the Section 7.13 on
page 28) during soft-start and until the start-up phase is over (t = t
is clamped at V
(see Figure 24 on page 18).
FBlin.
In this way, the feedback voltage can exceed V
16/40 Doc ID 15455 Rev 5
threshold, V
(see Figure 25 on page 18), which would activate the OLP function, only at
FBolp
the end of the start-up phase (t > t
SU
voltage exceeds the threshold V
DD
, (tSS < tSU, see Table 8 on page 8),
SS
and ramp up as far as the overload
FBlin
Dlim
SU
, (see Figure 24 or
), the feedback voltage
. An internal
DDon
) if the output voltage is still below the regulated value.
VIPER15 Operation description
As soon as the output voltage reaches the regulated value, the regulation loop takes over and the drain current is regulated below its limit, I at a value lower than the threshold V
FBlin
, by the feedback voltage, which settles
Dlim

Figure 22. IDD current during start-up and burst mode

V
DD
V
DDon
V
DDoff
V
FB
V
FBolp
V
FBlin
V
FBbm
V
DRAIN
I
DD
I
DD1
I
DD0
I
(-3 mA)
DDch
START- UP
NORMAL MODE
BURST MODE
NORMAL M ODE

Figure 23. Timing diagram: normal power-up and power-down sequences

V
V
DRAIN_START
IN
VIN< V
DRAIN_START
HV startup is no m ore activated
t
t
t
t
V
FBbmhys
V
DD
V
DDon
V
DDoff
V
DD(RESTART)
V
DRAIN
I
DD
I
(3mA)
DDch
Power-on
Normal operation
regulation is lost here
Power-off
time
time
time
time
Doc ID 15455 Rev 5 17/40
Operation description VIPER15

Figure 24. Timing diagram: Start-up phase and soft start (case 1)

t
(start up phase)
I
DRAIN
V
V
I
Dlim
V
FBolp
FBlin
FB
SU
tSS(soft start)
t
V
OUT
Regulated value

Figure 25. Timing diagram: Start-up phase and soft start (case 2)

t
(start up phase)
I
DRAIN
V
V
I
Dlim
V
FBolp
FBlin
FB
SU
t
SS
(soft start)
T
OLP-delay
t
t
t
V
OUT
Regulated value
18/40 Doc ID 15455 Rev 5
t
t
VIPER15 Operation description

7.4 Power-down description

At converter power-down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. The V the V interrupted and consequently the V if the V
threshold the power MOSFET is switched OFF, the energy transfers to the IC is
DDoff
is lower than the threshold V
IN
voltages decreases, see Figure 23 on page 17. Later,
DD
DRAIN_START
voltage drops and when it falls below
DD
, the start-up sequence is inhibited and the power-down completed. This feature is useful to prevent converter’s restart attempts and ensures monotonic output voltage decay during the system power-down.

7.5 Auto-restart description

If after a converter power-down, the VIN is higher than V
DRAIN_START,
sequence is not inhibited and will be activated only when the V V
DD(RESTART)
current generator restarts the V below V
threshold (reported on Table 7 on page 7). This means that the HV start-up
capacitor charging only when the V
DD
DD(RESTART)
. The scenario above described is for instance a power-down because
of a fault condition. After a fault condition, the charging current, I
the power-up
voltage drops down the
DD
voltage drops
DD
, is reduced to 0.6 mA
DDch
instead of 3 mA of the normal power-up converter phase. This feature together with the low V
DD(RESTART)
threshold (reported on Table 7 on page 7) ensures that, after a fault, the restart attempts of the IC has a very long repetition rate and the converter works safely with extremely low power throughput. The
Figure 26 shows the IC behavioral after a short-circuit
event.

Figure 26. Timing diagram: behavior after short-circuit

DD
FB
FBlin
DS
Short circuit occurs here
0.3 x T
REPETITION
T
REPETITION
time
time
V
DD(RESTART)
V
V
DDon
V
DDoff
V
V
FBolp
V
V
I
DD
I
(0.6mA)
DDch
time
time
Doc ID 15455 Rev 5 19/40
Operation description VIPER15

7.6 Quasi-resonant operation

The control core of the VIPER15 is a current-mode PWM controller with a the zero current detection circuit designed for Quasi-Resonant (QR) operation, a technique that provides the benefits of minimum turn-on losses, low EMI emission and safe behavior in case of short­circuit. At heavy load the converter operates in quasi-resonant mode: operation lies in synchronizing MOSFET's turn-on to the transformer’s demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. The system works close to the boundary between discontinuous (DCM) and continuous conduction (CCM) of the transformer and the switching frequency will be different for different line/load conditions. See the hyperbolic-like portion reported in
page 21
.
At medium/ light load, depending also from the converter input voltage, the device enters in Valley-skipping mode. The internal oscillator, synchronized to MOSFET’s turn-on, defines the maximum operating frequency of the converter, F
OSClim
.
The VIPER15 is available as type ‘L’ or type ‘H’, depending from the value of F
Table 8 on page 8. During the normal operation the converter works with a frequency below
F
, so the ‘L’ type is suitable for application where the priority is on the EMI filter
OSClim
minimization. The ‘H’ type is suitable when an extended QR operation range is a plus or the priority is the transformer size reduction.
Figure 27 on
OSClim
, see
As the load is reduced, and the switching frequency tends to exceeds the limit F
OSClim
, MOSFET’s turn-on will not any more occur on the first valley but on the second one, the third one and so on, see piecewise linear portion in
Figure 29 on page 22. In this way a “frequency clamp” effect is achieved,
Figure 27 on page 21.
When the load is extremely light or disconnected, the converter enters in burst mode operation, see the relevant
Section 7.14 on page 32. Decreasing the load will then result in
frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations or recommendations. Being the peak current low enough, no issue of audible noise.
The above mentioned way of operation is based on the ZCD pin. This pin is the input of the integrated ZCD circuit which allows the power section turn-on at the end of the transformer demagnetization. The input signal for the ZCD is obtained as a partition of the auxiliary voltage used to supply the device, see
When the integrated triggering circuit senses the negative going edge of the voltage V going below the threshold V
ZCDTth
Figure 28 on page 21.
,
ZCD
, the power MOSFET is turned on with a delay that helps to achieve the minimum drain-source voltage during the switch on. The mentioned triggering circuit has to be previously armed by a positive going edge of the voltage V the threshold V
. See the Table 8 on page 8.
ZCDAth
, exceeding
ZCD
After the MOSFET turn-off there is a typical noise generated by the transformer's leakage inductance resonance ringing and coupled with the ZCD pin. The blanking time, T
BLANK
,
helps to filter this noise avoiding false triggers of the ZCD circuit.
20/40 Doc ID 15455 Rev 5
VIPER15 Operation description
Y

Figure 27. Switching frequency vs output load

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Figure 28. Zero current detection circuit and oscillator circuit

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Doc ID 15455 Rev 5 21/40
Operation description VIPER15

7.7 Frequency foldback function and valley skipping mode

The switching frequency, in Quasi Resonant mode, is not fixed and it depends on both the load and the converter’s input voltage. The switching frequency increases when the load decreases, or when the input voltage mains increases, and vice versa. In principle it could reach an infinite value. To avoid that, the VIPER15 taps the maximum switching frequency of the application by its control logic.
The frequency limit is realized with an internal oscillator switching at 136 kHz for VIPER15L or at 225 kHz for the VIPER15H, sees the parameter F oscillator is synchronized with power MOSFET turn-on. When the power MOSFET is off, if the first negative-going edge voltage of the ZCD pin, resulting from transformer’s demagnetization, appears after at least one oscillator cycle has been completed, the MOSFET is turned ON and the oscillator re-synchronized.
Otherwise, if the first negative-going edge voltage appears before completing one oscillator cycle, the signal is ignored. Due to the ringing of the drain voltage, the ZCD pin will experience another positive-going edge voltage that arms the circuit and a subsequent negative-going edge voltage. Again, if this appears before the oscillator cycle is complete, it is ignored, otherwise the MOSFET is turned ON and the oscillator re-synchronized. In this way, one or more drain ringing cycles will be skipped (
Figure 29 on page 22 shows the so
called “valley-skipping mode”) and the switching frequency will be prevented from exceeding the limit F
OSClim
.
on Table 8 on page 8. This
OSClim

Figure 29. Drain ringing cycle skipping as the load is progressively reduced

V
DS
T
T
ON
T
FW
V
T
os c
in'
Pin= P
(limit condition)
V
DS
t
T
osc
in''
< P
in'
Pin= P
V
DS
t
T
os c
in'''
< P
in''
Pin= P
t
When the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the OFF-time of the power MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for cycle-by-cycle energy balance could fall in between. Thus one or more longer switching cycles will be compensated by one or more shorter cycles and vice versa. This mechanism is natural and there is no appreciable effect on the converter’s performances and on its output voltage.
The operation described so far does not consider the blanking time T MOSFET's turn OFF. Actually T
after power
does not come into play as long as the following
BLANK
BLANK
condition is met:
Equation 2
T
BLANK
1D =
T
limOSC
FT1
limOSCBLANK
where D is the MOSFET duty cycle. If this condition is not met, the time during which MOSFET's turn-ON is inhibited is extended beyond T consequence, the maximum switching frequency will be a little lower than the internal limit set by the oscillator and valley-skipping mode will take place slightly earlier than expected.
22/40 Doc ID 15455 Rev 5
by a fraction of T
OSClim
BLANK
. As a
VIPER15 Operation description
V
t
0
D
t
t
t
t
D
y
r
V
V

7.8 Double blanking time

The blanking time, T value) and the higher one is 6,3 μs (typical value). The value is linked to the voltage V sampled during the time T
Section 7.11 on page 26). The time T
has the higher value if is detected V
page 23
.
, can have two different values: the lower one is 2,5 μs (typical
BLANK
STROBE
defined as for the overvoltage protection (see the relevant
has the lower value if is detected V
BLANK
> 1V, refer to Table 8 on page 8 and Figure 30 on
ZCD
< 1V or it
ZCD
ZCD
,
The higher value of the blanking time is normally activated during the start-up phase or in case of output short-circuit; when the output voltage of the converter is quite lower than the regulated value. In this condition can happens that during the demagnetization of the transformer, the V V
) and the ZCD circuit can be erroneously trigged, leading the system to work at
ZCDTth
is very close to the arming and triggering thresholds (V
ZCD
ZCDAth
and
higher frequency and in continuous mode. This false trigger is inhibited by the selection of the higher value of T
During the normal operation, in steady state condition, the voltage V demagnetization is higher than 1V and the selected T
Figure 30 shows the typical waveforms during the power up and the linked T
Figure 30. Double T
Vaux
when V
BLANK
timing diagram
BLANK
Mosfet switched on by the starte
is lower than 1 V.
ZCD
during the
value is the lower one. The
BLANK
ZCD
Quasi Resonant Operation
BLANK
selection.
ZC
(pin 3)
1
0.8
0. 6
T
ST R O B E
A
T
BLANK
C
F
1.5
6.3μs
0.5
2. 5 μs
Dela
4
F
limOSC
t
t
t
Doc ID 15455 Rev 5 23/40
Operation description VIPER15

7.9 Starter

If the amplitude of the voltage on ZCD pin at the end of one oscillator cycle is smaller than the V system would stop.
This is what normally happens during converter’s power-up or under overload/short-circuit conditions.
During the converter’s startup phase, the voltage on ZCD pin is not high enough to arm the triggering circuit. Thus, the converter operates at a fixed frequency, F
on page 8
arm the ZCD circuit, MOSFET's turn-ON is locked to transformer demagnetization, hence setting up quasi-resonant operation.
arming threshold, in which case MOSFET's turn-ON could not be triggered, the
ZCDAth
STARTER
(see Ta bl e 8
). As the voltage developed across the auxiliary winding becomes high enough to
As protection, in case the ZCD voltage is permanently above the threshold V switching frequency is reduced to the minimum value, F
page 8
.
, reported on Ta b l e 8 o n
OSCmin

7.10 Current limit set point and feed-forward option

The VIPER15 is a current mode converter and the drain current is limited cycle by cycle according to the FB pin voltage value that is related with the feedback loop response and the load. When the drain current, sensed by the integrated Sense-FET, reaches the current limitation, after the internal propagation delay, the MOSFET is switched OFF. The current limitation cannot exceed a certain value, I sunk from the ZCD pin during MOSFET’s ON-time.
Usually a resistor, R
, connected from ZCD pin to ground is used to fix this sunk current
LIM
and then the peak drain current set-point: the lower the resistor is, the lower I
For a QR fly-back converter the power capability strongly depends on the input voltage. In wide-range applications at maximum line the power capability can be more than twice the value at minimum line, as shown by the upper curve in the diagram of To reduce this dependence, the current limit I increment of the input voltage, implementing the so called line feed-forward. It’s realized with a resistor, R
on page 26
, connected between the ZCD pin and the auxiliary winding, see the Figure 32
FF
. Since the voltage across the auxiliary winding during MOSFET’s on-time is proportional to the input voltage through the auxiliary-to-primary turns ratio N current proportional to the input voltage is sunk from the ZCD pin, thus lowering the overcurrent set point.
, that can be adjusted acting on the current
Dlim
Figure 31 on page 25.
has to be reduced according to the
Dlim
ZCDAth
will be.
Dlim
/NP, a
AUX
, the
24/40 Doc ID 15455 Rev 5
VIPER15 Operation description
@

Figure 31. Typical power capability vs input voltage in quasi-resonant converter’s

2.5
2
inmi n
1.5
V
inli m
P
1
0.5
11.522.53 3.54
sy s tem not
compensated
system opti mally
compensated
V
in
V
inmi n
In order to proper select the value of the resistance RFF (see Figure 32 on page 26), once are known the proper I voltage. The following approximated formula calculates the value of the resistor R
set points at minimum and at the maximum converter input
Dlim
FF
Equation 3
VV
R
=
FF
min_inmax_in
)II(n
2ZCD1ZCDaux
Where:
V
n
I
the selected I current is reported on
and V
in_Max
is the primary to auxiliary winding turn ratio
aux
, and I
ZCD1
ZCD2
are the maximum and minimum converter rectified input voltage
in_min
are the currents needed to sink from the ZCD pin, in order to obtain
set points, respectively at V
Dlim
Figure 16 on page 12).
in_max
and V
in_min
, the graph I
Dlim
vs I
ZCD
The
R
Value can be calculated from the following formula knowing the RFF value:
LIM
Equation 4
⎞ ⎟
⎟ ⎟ ⎟ ⎟
V
2ZCD
⎟ ⎟
⎟ ⎠
LIM
⎛ ⎜
⎜ ⎜ ⎜
=
MaxR
⎜ ⎜
I
⎜ ⎝
V
1ZCD
V
min_in
+
n
aux
1ZCD
R
FF
,
V
1ZCD
I
V
2ZCD
V
max_in
+
n
aux
2ZCD
R
FF
Where:
V
and V
ZCD1
respectively (see
are the ZCD pin voltages when the sunk current is I
ZCD2
Figure 15 on page 12).
Doc ID 15455 Rev 5 25/40
ZCD1
and I
ZCD2
Operation description VIPER15
G

Figure 32. ZCD pin typical external configuration

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7.11 Overvoltage protection (OVP)

The VIPER15 has integrated the logic for the monitor of the output voltage using as input signal the voltage V the voltage from the auxiliary winding tracks the output voltage, through the turn ratio N
.
N
SEC
The ZCD pin has to be connected to the auxiliary winding through the diode D resistors R the voltage V
OVP
and R
ZCD
Table 8 on page 8) the overvoltage protection will stop the power MOSFET and the
converter enters the auto-restart mode.
during the OFF time of the power MOSFET. This is the time when
ZCD
as shows the Figure 32 on page 26. When, during the OFF time,
LIM
exceeds, four consecutive times, the reference voltage V
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and the
OVP
(reported on
OVP
!-V
AUX
/
In order to bypass the noise after the turn off of the power MOSFET, the voltage V sampled inside a short-window after the time T
Figure 33 on page 27. The sampled signal, if higher than V
digital signal and increments the internal counter. The same counter is reset every time the signal OVP is not triggered in one oscillator cycle.
Referring to the
Figure 32, the resistors divider ratio k
Equation 5
k
OVP
26/40 Doc ID 15455 Rev 5
---------------------------------------------------------------------------------------------------=
N
AUX
--------------
N
SEC
STROBE
V
OVP
V
OUTOVPVDSEC
+()V
, see the Table 8 on page 8 and
ZCD
, trigger the internal OVP
OVP
will be given by:
OVP
DAUX
is
VIPER15 Operation description
U
Equation 6
OVP
----------------------------------=
R
+
LIMROVP
k
R
LIM
Where:
V
V
is the OVP threshold (see Table 8 on page 8)
OVP
OUT OVP
is the converter output voltage value to activate the OVP (set by designer)
designer
N
N
V
V
R
Than, fixed R
is the auxiliary winding turns
AUX
is the secondary winding turns
SEC
is the secondary diode forward voltage
DSEC
is the auxiliary diode forward voltage
DAUX
together R
OVP
according to the desired I
LIM,
make the output voltage divider
LIM
Dlim
, the R
can be calculating by:
OVP
Equation 7
1k
OVP
R
OVP
-----------------------
×=
R
LIM
k
OVP
The resistor values will be such that the current sourced and sunk by the ZCD pin be within the rated capability of the internal clamp.

Figure 33. OVP timing diagram

VA
ZCD
V
STROBE
STROBE
COUNTER
COUNTER
RESET
RESET
COUNTER
COUNTER
STATUS
STATUS
FAULT
FAULT
X
0
0
OVP
OVP
OVP
0 0 0
0 0 0
0.5 µs
0.5 µs
2 µs
2 µs
1
1
0
1
0
1
2
0
2
0
2
2
1
1
2
3
2
0
1
0
1
3
3
2
2
3
ERULIAF POOL KCABDEEFECNABRUTSID YRAROPMETNOITAREPO LAMRON
ERULIAF POOL KCABDEEFECNABRUTSID YRAROPMETNOITAREPO LAMRON
t
t
t
t
t
t
t
t
t
t
t
40
40
t
t
t
t
Doc ID 15455 Rev 5 27/40
Operation description VIPER15

7.12 Summary on ZCD pin

Referring to the Figure 32 on page 26, the circuitry connected to the ZCD pin enables to implement the following functions:
1. Current limit, I
2. Line feed-forward compensation
3. Output overvoltage protection (OVP)
4. Zero current detection for QR operation
, set point
Dlim
Chosen R
, RFF and R
LIM
as described in previous paragraphs this function are
OVP
automatically defined.
Ta bl e 9 refers to the Figure 32 and list the external resistance combinations needed to
activate one or more functions associated to the ZCD pin.

Table 9. ZCD pin configurations

Function / component R
I
set point See Equation 4 Required for ZCD Not required Yes
Dlim
LIM
R
OVP 22 kΩ See Equation 7 Not required Yes
Line feed-forward 22 kΩ Required for ZCD See Equation 3 Ye s
I
set point and OVP
Dlim
See Equation 4
FF
=
with R
See Equation 7 Not required Yes
OVP and line feed-forward 22 kΩ See Equation 7 See Equation 3 Ye s
set point and line feed-forward See Equation 4 Required for ZCD See Equation 3 Ye s
I
Dlim
reduction+ OVP +
I
Dlim
Line feed-forward
See Equation 4 See Equation 7 See Equation 3 Ye s

7.13 Feedback and overload protection (OLP)

The feedback pin (FB) controls the PWM operation, enters the burst mode and manages the delayed overload protection.
OVP
R
FF
D
OVP
The thresholds V
FBbm
and V
(reported on Table 8 on page 8) are respectively the low
FBlin
and the high limit of the PWM operations, where the drain current is sensed trough the integrated resistor R
and applied to the comparator PWM. The PWM logic turns OFF
SENSE
the power MOSFET as soon as the sensed voltage is equal to the voltage applied to the FB pin and trough the integrated resistors network, see the
on page 14
.
As shows the IC block diagram reported in comparator there is the OCP comparator that limits the drain current as maximum to the value I
In case of higher load the voltage V drain current is limited to I As soon as the voltage V
, reported on Table8 on page8.
Dlim
and the internal current starts the charge of the capacitor CFB.
Dlim
reaches the threshold V
FB
FB
protection turns off the IC. After, the auto-restart mode is activated using the low value of the current I
28/40 Doc ID 15455 Rev 5
, see Table 7 on page 7.
DDch
Figure 2 on page 4 and Figure 20
Figure 2 on page 4, in parallel with the PWM
increases, when it reaches the threshold V
, see Figure 36 on page 31, the
FBolp
FBlin
the
VIPER15 Operation description
The time, from the high load detection, VFB = V depends from the value of the capacitor C
and from the internal charge current, IFB. The
FB
, to the overload turn-off, VFB = V
FBlin
FBolp
,
OLP delay time can be calculating by the formula:
Equation 8
V
FBolpVFBlin
T
OLP delay
The current, I also a part of the compensation loop
is 3 μA as minimum value. The components connected to the FB pin are
FB,
, so they have to be selected taking into account the
proper delay and loop stability consideration. The
page 30
In the
show two different feedback networks.
Figure 33 on page 27, the capacitor, CFB, connected to FB pin is used as part of the
----------------------------------------
C
×=
FB
3μA
Figure 34 on page 30 and Figure 35 on
circuit to compensate the feedback loop but also as element to delay the OLP shut down owing to the time needed to charge the capacitor (see the
After the start-up time, t
, during which the feedback voltage is fixed at V
SU
Equation 8).
, the output
FBlin
capacitor could not be at its nominal value and the controller interpreter this situation as an overload condition. In this case, the OLP delay helps to avoid an incorrect device shut down during the start-up. See the relevant
Section 7.3 on page 16.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the initial output voltage transient and check the overload condition only when the output voltage is in steady state. The output transient time depends from the value of the output capacitor and from the load.
When the value of the C
capacitor calculated for the loop stability is too low and cannot
FB
ensure enough OLP delay, an alternative compensation network can be used and it is showed in
Using this alternative compensation network, two poles (f introduced by the capacitors C
The capacitor C
Figure 35 on page 30.
FB
introduces a pole (f
FB
and C
and the resistor R
FB1
) at higher frequency than f
PFB
PFB
, f
) and one zero (f
PFB1
.
FB1
ZB
and f
. This pole
PFB1
ZFB
) are
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
Figure 35 on page 30 are reported by the equations below:
in
Equation 9
f
ZFB
=
1
RC2
π
1FB1FB
Equation 10
RR
+
f
=
PFB
()
1FB)DYN(FB
RRC2
π
1FB)DYN(FBFB
Doc ID 15455 Rev 5 29/40
Operation description VIPER15
Equation 11
1
()
RRC2
+⋅π
)DYN(FB1FB1FB
The R
FB(DYN)
f
=
1PFB
is the dynamic resistance seen by the FB pin and reported on Tab l e 8 o n
page 8.
The C
Equation 8 on page 29 can be still used to calculate the OLP delay time but C
capacitor fixes the OLP delay and usually C
FB1
results much higher than C
FB1
has to be
FB1
FB
. The
considered instead of CFB. Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 34. FB pin configuration (option 1)

From sense FET
Cfb
PWM
CONTROL
BURST-MODE
REFERENCES
OLP comparator
4.8V
PWM
+
-
BURST-MODE
LOGIC
+
-
To PWM Logic
BURST
To disable logic

Figure 35. FB pin configuration (option 2)

From sense FET
PWM
OLP comparator
4.8V
+
-
BURST-MODE
LOGIC
+
-
PWM
CONTROL
Rfb1
Cfb1
Cfb
BURST-MODE
REFERENCES
To PWM Logic
BURST
To disable logic
30/40 Doc ID 15455 Rev 5
VIPER15 Operation description

Figure 36. Timing diagram: Overload protection

I
OUT
V
I
DRAIN
V
V
V
FBolp
FBlin
OUT
I
Dlim
t
t
FB
SOFT
START
START UP
OVER LOAD
Warning
OVER LOAD
Warning
STOP
OPERATION
t
t
Doc ID 15455 Rev 5 31/40
Operation description VIPER15

7.14 Burst-mode operation at no load or very light load

When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it falls down the burst mode threshold, V switched on. After the MOSFET stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding the level, V V
FBbmhys
reported on
, the power MOSFET starts switching again. The burst mode thresholds are
Ta bl e 8 and Figure 37 shows this behavior. Systems alternates period of time
where power MOSFET is switching to period of time where power MOSFET is not switching; this device working mode is the burst mode. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. During the burst-mode the drain current peak is clamped to the level, I

Figure 37. Burst mode timing diagram, light load management

V
COMP
V
FBbm+VFBbmhys
V
FBbm
, the power MOSFET is not more allowed to be
FBbm
FBbm
, reported on Ta b le 8 .
D_BM
+
I
DD
I
DD1
I
DD0
I
DRAIN
I
D_BM

7.15 Brown-out protection

Brown-out protection is a not-latched shutdown function activated when a condition of mains under voltage is detected. The Brown-out comparator is internally referenced to V threshold, see is below this internal reference. Under this condition the power MOSFET is turned off. Until the Brown out condition is present, the V V
and the UVLO thresholds, as shown in the timing diagram of Figure 38 on page 33. A
DDon
voltage hysteresis is present to improve the noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus the before said voltage hysteresis. See
The Brown-out comparator is provided also with a current hysteresis, I has to set the rectified input voltage above which the power MOSFET starts switching after brown out event, V switched off, V be set separately.
Table 8 on page 8, and disables the PWM if the voltage applied at the BR pin
INon
. Thanks to the I
INoff
time
time
BRth
time
Burst Mode
voltage continuously oscillates between the
DD
Figure 5 on page 10.
. The designer
BRhyst
, and the rectified input voltage below which the power MOSFET is
, see Table 8 on page 8, these two thresholds can
BRhyst
32/40 Doc ID 15455 Rev 5
VIPER15 Operation description

Figure 38. Brown-out protection: BR external setting and timing diagram

V
IN_DC
R
H
R
+
VDD
L
BR
C
I
BRhyst
Fixed the V
and the V
INon
V
DIS
V
BRth
+
-
Disable
+
-
INoff
V
in_OK
levels, with reference to Figure 38, the following relationships
can be established for the calculation of the resistors R
V
DRAIN_START
V
in_OK
I
V V
V
DD(RESTART)
V
V
V
INon
V
INoff
V
V
BRth
I
BR
BRhyst
V
DDon
DDoff
V
DS
OUT
IN
BR
DD
and RL:
H
Equation 12
V
R ×
BRhyst
L
I
BRhyst
+=
VVV
BRhystINoffINon
VV
BRthINoff
V
BRth
I
BRhyst
Equation 13
VVV
R
=
H
I
BRhyst
For a proper operation of this function, V minimum mains and V
less than the minimum voltage on the input bulk capacitor at
IN off
BRhystINoffINon
×
must be less than the peak voltage at
IN on
R
L
V
R
BRhyst
+
L
I
BRhyst
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the OFF threshold when the converter operates or gives origin to undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind.
If the brown-out function is not used the BR pin has to be connected to GND, ensuring that the voltage is lower than the minimum of V
threshold (50 mV, see Ta b le 8 ). In order to
DIS
enable the brown-out function the BR pin voltage has to be higher than the maximum of V
threshold (150 mV, see Ta b le 8 ).
DIS
Doc ID 15455 Rev 5 33/40
Operation description VIPER15

7.16 2nd level overcurrent protection and hiccup mode

The VIPER15 is protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturation of fly-back transformer. Such as anomalous condition is invoked when the drain current exceed the threshold I
page 8
.
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a “warning state” is entered after the first signal trip. If in the subsequent switching cycle the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the I
threshold is exceeded for two consecutive
DMAX
switching cycles a real malfunction is assumed and the power MOSFET is turned OFF.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the V decays till the V
The start up HV current generator is still off, until V V
DD(RESTART)
and the converter switching restarts if the V
under voltage threshold (V
DD
), which clears the latch.
DDoff
voltage goes below its restart voltage,
DD
. After this condition the VDD capacitor is charged again by 600 µA current,
occurs. If the fault condition is not removed
DDon
the device enters in auto-restart mode. This behavioral results in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing diagram of
Figure 39.
, see Ta b l e 8 o n
DMAX
DD
capacitor

Figure 39. Hiccup-mode OCP: timing diagram

V
Vcc
V
DD
V
DD
V
DD
Vccrest
Vccrest
IDRAIN
V
DS
DD
OFF
IDmax
IDmax
ON
Secondary diode is shorted here
Secondary diode is shorted here
t
t
t
t
t
t
34/40 Doc ID 15455 Rev 5
VIPER15 Package mechanical data

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

Table 10. DIP-7 mechanical data

1. Creepage distance > 800 V
2. Creepage distance as shown in the 664-1 CEI / IEC standard
3. Creepage distance 250 V
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
mm
Dim.
Typ. Min. Max.
A 5.33
A1 0.38
A2 3.30 2.92 4.95
b 0.46 0.36 0.56
b2 1.52 1.14 1.78
c 0.25 0.20 0.36
D 9.27 9.02 10.16
E 7.87 7.62 8.26
E1 6.35 6.10 7.11
e 2.54
eA 7.62
eB 10.92
L 3.30 2.92 3.81
(1)(2)
M
2.508
N 0.50 0.40 0.60
N1 0.60
(2)(3)
O
0.548
Note: The leads size is comprehensive of the thickness of the leads finishing material.
Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
Package outline exclusive of metal burrs dimensions.
Datum plane “H” coincident with the bottom of lead, where lead exits body.
Ref. POA mother doc. 0037880
Doc ID 15455 Rev 5 35/40
Package mechanical data VIPER15

Figure 40. DIP-7 package dimensions

2 - 3
36/40 Doc ID 15455 Rev 5
1 - 2
VIPER15 Package mechanical data

Table 11. SO16 narrow mechanical data

Databook (mm.)
Dim.
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
Doc ID 15455 Rev 5 37/40
Package mechanical data VIPER15

Figure 41. SO16 package dimensions

38/40 Doc ID 15455 Rev 5
VIPER15 Revision history

9 Revision history

Table 12. Document revision history

Date Revision Changes
05-Mar-2009 1 Initial release
07-Apr-2009 2
Updated
Figure 21
Ta bl e 3 , Tab l e 6 , Tab l e 8 , Figure 16, Figure 20 and
20-Jul-2009 3
Updated application paragraph in coverpage and
page 8
Table 8 on
26-Aug-2009 4 Content reworked to improve readability, no technical changes
27-Aug-2010 5 Updated
Section 7.1, Section 7.15
Doc ID 15455 Rev 5 39/40
VIPER15
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40/40 Doc ID 15455 Rev 5
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