The TS2007 is a class D power audio amplifier.
Able to drive up to 1.4 W into an 8 Ω load at 5 V, it
achieves outstanding efficiency compared to
typical class AB audio power amplifiers.
This device allows switching between two
different gains: 6 or 12dB via a logic signal on the
GS pin. A pop & click reduction circuitry provides
low on/off switching noise while allowing the
device to start within 5 ms. A standby function
(active low) allows lowering the current
consumption down to 10 nA typ.
May 2011Doc ID 13123 Rev 41/29
The TS2007 is available in DFN8 3 x 3 mm leadfree packages.
www.st.com
29
ContentsTS2007
Contents
1Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3
Figure 42. THD+N vs. frequencyFigure 43. THD+N vs. frequency
10
RL=4Ω + 15μH
G=6dB
Bw < 30kHz
Vcc=5V
1
Tamb = 25°C
Po=1.5W
10
RL=4Ω + 30μH
G=6dB
Bw < 30kHz
Vcc=5V
1
Tamb = 25°C
Po=1.5W
Po=0.25W
20k20
THD + N (%)
0.1
0.01
Po=0.75W
100100010000
Frequency (Hz)
20k20
THD + N (%)
0.1
0.01
Po=0.75W
100100010000
Frequency (Hz)
Figure 44. THD+N vs. frequencyFigure 45. THD+N vs. frequency
10
1
THD + N (%)
0.1
0.01
RL=8Ω + 15μH
G=6dB
Bw < 30kHz
Vcc=5V
Tamb = 25°C
100100010000
Po=0.9W
Po=0.45W
20k20
Frequency (Hz)
10
1
THD + N (%)
0.1
0.01
RL=8Ω + 30μH
G=6dB
Bw < 30kHz
Vcc=5V
Tamb = 25°C
100100010000
Po=0.9W
Po=0.45W
Frequency (Hz)
20k20
20k20
20/29 Doc ID 13123 Rev 4
TS2007Electrical characteristics
Figure 46. Power derating curvesFigure 47. Startup and shutdown phase
V
=5 V, G=6 dB, Cin=1 µF, inputs
CC
grounded
3.5
3.0
2.5
2.0
1.5
1.0
0.5
DFN8 Package Power Dissipation (W)
0.0
0255075100125150
Ambiant Temperature (°C)
Figure 48. Startup and shutdown phase
V
=5 V, G=6 dB, Cin=1 µF,
CC
V
=1 Vpp, F=10 kHz
in
Mounted on a 4-layer PCB
No Heat sink
Figure 49. Startup and shutdown phase
=5 V, G=12 dB, Cin=1 µF,
V
CC
V
=1 Vpp, F=10 kHz
in
Doc ID 13123 Rev 421/29
Application informationTS2007
4 Application information
4.1 Differential configuration principle
The TS2007 is a monolithic fully-differential input/output class D power amplifier. The
TS2007 also includes a common-mode feedback loop that controls the output bias value to
average it at V
always have a maximum output voltage swing, and by consequence, maximize the output
power. Moreover, as the load is connected differentially compared to a single-ended
topology, the output is four times higher for the same power supply voltage.
The advantages of a full-differential amplifier are:
●High PSRR (power supply rejection ratio)
●High common-mode noise rejection
●Virtually zero pop without additional circuitry, giving a faster startup time compared to
conventional single-ended input amplifiers
●Easier interfacing with differential output audio DAC
●No input coupling capacitors required thanks to common-mode feedback loop
/2 for any DC common-mode input voltage. This allows the device to
CC
4.2 Gain settings
In the flat region of the frequency-response curve (no input coupling capacitor or internal
feedback loop + load effect), the differential gain can be set to either 6 or 12 dB depending
on the logic level of the GS pin:
GSGain (dB)Gain (V/V)
16 dB2
012 dB4
Note:Between the GS pin and VCC there is an internal 300 kΩ resistor. When the pin is floating
the gain is 6 dB.
4.3 Common-mode feedback loop limitations
As explained previously, the common-mode feedback loop allows the output DC bias
voltage to be averaged at V
Due to the V
limitation of the input stage (see Table 2: Operating conditions on page 3), the
ic
/2 for any DC common-mode bias input voltage.
CC
common-mode feedback loop can fulfill its role only within the defined range.
4.4 Low frequency response
If a low frequency bandwidth limitation is required, it is possible to use input coupling
capacitors. In the low frequency region, the input coupling capacitor C
effect. C
forms, with the input impedance Zin, a first order high-pass filter with a -3 dB cutoff
in
frequency (see Ta bl e 5 to Tab l e 9).
22/29 Doc ID 13123 Rev 4
starts to have an
in
TS2007Application information
1
------------------------------------=
F
CL
⋅⋅ ⋅
2 π Z
inCin
So, for a desired cutoff frequency F
with F
The input impedance Z
in Hz, Zin in Ω and Cin in F.
CL
is for the whole power supply voltage range, typically 75 kΩ . There
in
CL
is also a tolerance around the typical value (see Ta b le 5 to Ta bl e 9 ). With regard to the
tolerance, you can also calculate tolerance of F
●
F
CLmax
F
●
CLmin
1.103 FCL⋅=
0.915 FCL⋅=
4.5 Decoupling of the circuit
A power supply capacitor, referred to as CS, is needed to correctly bypass the TS2007.
The TS2007 has a typical switching frequency of 280 kHz and output fall and rise time of
about 5 ns. Due to these very fast transients, careful decoupling is mandatory.
A 1 µF ceramic capacitor is enough, but it must be located very close to the TS2007 in order
to avoid any extra parasitic inductance created by a long track wire. Parasitic loop
inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency
of the device and may cause, if this parasitic inductance is too high, a TS2007 breakdown.
we can calculate Cin:
C
in
1
------------------------------------- -=
⋅⋅ ⋅
2 π Z
CL
inFCL
:
In addition, even if a ceramic capacitor has an adequate high frequency ESR value, its
current capability is also important. A 0603 size is a good compromise, particularly when a
4 Ω load is used.
Another important parameter is the rated voltage of the capacitor. A 1µF/6.3V capacitor
used at 5 V, loses about 50% of its value. With a power supply voltage of 5 V, the decoupling
value, instead of 1 µF, could be reduced to 0.5 µF. As C
has particular influence on the
S
THD+N in the medium to high frequency region, this capacitor variation becomes decisive.
In addition, less decoupling means higher overshoots which can be problematic if they reach
the power supply AMR value (6 V).
4.6 Wake-up time (twu)
When the standby is released to set the device ON, there is a wait of 5 ms typically. The
TS2007 has an internal digital delay that mutes the outputs and releases them after this
time in order to avoid any pop noise.
Note:The gain increases smoothly (see Figure 49) from the mute to the gain selected by the GS
pin (Section 4.2).
Doc ID 13123 Rev 423/29
Application informationTS2007
4.7 Shutdown time
When the standby command is set, the time required to put the two output stages into high
impedance and to put the internal circuitry in shutdown mode, is typically 5 ms. This time is
used to decrease the gain and avoid any pop noise during shutdown.
Note:The gain decreases smoothly until the outputs are muted (see Figure 49).
4.8 Consumption in shutdown mode
Between the shutdown pin and GND there is an internal 300 kΩ resistor. This resistor forces
the TS2007 to be in shutdown when the shutdown input is left floating.
However, this resistor also introduces additional shutdown power consumption if the
shutdown pin voltage is not 0 V.
Referring to Table 2: Operating conditions on page 3, with a 0.4 V shutdown voltage pin for
example, you must add 0.4V/300k = 1.3 µA in typical (0.4V/273 k = 1.46 µA in maximum) to
the shutdown current specified in Ta bl e 5 to Tab le 9 .
4.9 Single-ended input configuration
It is possible to use the TS2007 in a single-ended input configuration. However, input
coupling capacitors are needed in this configuration. The following schematic diagram
shows a typical single-ended input application.
Figure 50. Typical application for single-ended input configuration
VCC
Cs
H
Bridge
1uF
TS2007
OUT+
OUT-
8
5
Speaker
Gain Select Control
CinInput
Cin
Standby Control
4
3
21
GSVcc
IN-
Gain
Select
IN+
Standby
Control
Standby
67
-
+
PWM
Oscillator
Gnd
24/29 Doc ID 13123 Rev 4
TS2007Application information
4.10 Output filter considerations
The TS2007 is designed to operate without an output filter. However, due to very sharp
transients on the TS2007 output, EMI radiated emissions may cause some standard
compliance issues.
These EMI standard compliance issues can appear if the distance between the TS2007
outputs and loudspeaker terminal are long (typically more than 50 mm, or 100 mm in both
directions, to the speaker terminals). As the PCB layout and internal equipment device are
different for each configuration, it is difficult to provide a one-size-fits-all solution.
However, to decrease the probability of EMI issues, there are several simple rules to follow:
●Reduce, as much as possible, the distance between the TS2007 output pins and the
speaker terminals.
●Use a ground plane for “shielding” sensitive wires.
●Place, as close as possible to the TS2007 and in-series with each output, a ferrite bead
with a rated current of minimum 2.5 A and impedance greater than 50 Ω at frequencies
above 30 MHz. If, after testing, these ferrite beads are not necessary, replace them by
a short-circuit.
●Allow extra footprint to place, if necessary, a capacitor to short perturbations to ground
(see Figure 51).
Figure 51. Ferrite chip bead placement
From TS2007 output
Ferrite chip bead
to speaker
about 100pF
gnd
In the case where the distance between the TS2007 output and the speaker terminals is too
long, it is possible to have low frequency EMI issues due to the fact that the typical operating
frequency is 280 kHz. In this configuration, it is necessary to use the output filter
represented in Figure 1 on page 4 as close as possible to the TS2007.
Doc ID 13123 Rev 425/29
Package informationTS2007
5 Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in
ECOPACK
category of second level interconnect is marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics
trademark. ECOPACK specifications are available at: www.st.com
Figure 52. Pinout (top view)
Figure 53. Marking (top view)
®
packages. These packages have a lead-free second level interconnect. The
.
8
1
1
2
2
3
3
4
4
Logo: ST
Part number: K007
Three digit date code: YWW
The dot is for marking pin 1
8
7
7
6
6
5
5
Figure 54. Recommended footprint for the TS2007 DFN8 package
1.8 mm0.8 mm
2.2 mm
1.4 mm
26/29 Doc ID 13123 Rev 4
0.35 mm
0.65 mm
TS2007Package information
Figure 55. DFN8 package mechanical data
Dimensions
Ref
MillimetersMils
MinTypMaxMinTypMax
A0.500.600.6519.623.625.6
A10.020.050.81.9
A30.228.6
b0.250.300.359.811.813.8
D2.853.003.15112.2118.1124
D21.601.701.806366.970.8
E2.853.003.15112.2118.1124
E21.101.201.3043.347.251.2
e0.6525.5
(1)
L
0.500.550.6019.621.623.6
ddd0.083.1
SEATING
PLANE
C
C
ddd
A
A3
D
e
12
E2
8
1. The dimension of L is not compliant with JEDEC MO-248 which recommends 0.40 mm +/-0.10 mm.
7
D2
34
65
b
A1
E
Note:The DFN8 package has an exposed pad E2 x D2. For enhanced thermal performance, the
exposed pad must be soldered to a copper area on the PCB, acting as a heatsink. This
copper area can be electrically connected to pin 7 or left floating.
Doc ID 13123 Rev 427/29
Ordering informationTS2007
6 Ordering information
Table 11.Order code
Part numberTemperature rangePackageMarking
TS2007IQT-40 °C, +85 °CDFN8K07
7 Revision history
DateRevisionChanges
11-Jan-20071Initial release (preliminary data).
11-May-20072
24-May-20073
First complete datasheet. This release of the datasheet includes
electrical characteristics curves and application information.
Corrected error in Table 4: Pin descriptions: descriptions of pin 5 and pin
8 were inverted.
02-May-20114Added minimum R
to Table 1: Absolute maximum ratings
L
28/29 Doc ID 13123 Rev 4
TS2007
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