ST TN1337, SPC58EHx, SPC58NHx User manual

TN1337

Technical note

SPC58EHx/SPC58NHx giga Ethernet TX_CLK DoS analysis

Introduction

The SPC58EHx/SPC58NHx microcontroller (MCU) embeds the 1 Gbps Ethernet controller RGMII compliant.

This microcontroller introduces a new clock schema designed to manage the RGMII. The RGMII clock schema is designed to be very flexible and it supports several different programming modes as described in the reference manual (see

Section A.2 Reference documents). The SPC58EHx/SPC58NHx microcontroller has a new dedicated PLL_ETH and a logic to introduce a delay on the TX_CLK signal. While negotiating the 1000 link speed an improper or not enough margin to align the data to the clock can make unstable or unusable the whole network connectivity. So, the delay on source is designed to provide a phase shift of 90 degree guaranteeing enough margin to toggle the data.

The purpose of this technical note is to detail some measurements performed on the SPC58NHADPT302S evaluation board in order to demonstrate the delay on source functionality applied on the TX_CLK. The document also provides some information and some examples about the solutions that can be adopted to introduce skew.

TN1337 - Rev 1 - January 2021	www.st.com
For further information contact your local STMicroelectronics sales office.

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RGMII overview

1RGMII overview

The Reduced Gigabit Media Independent Interface (RGMII) has become a widely used alternative to the Gigabit Media Independent Interface (GMII) by offering lower pin count.

The RGMII standard achieves this by reducing the width of the parallel data bus and through double data rate (DDR). RGMII specifies that the clock and data will be generated simultaneously from the transmitting source and that a skew has to be introduced between clock and data. Skew can be achieved from the transceiver either using an internal delay or via PCB trace routing.

The interface definition supports two delay modes:

•Delay on Destination (DoD): the delay of the clock signal has to be accomplished by the receiver device.

•Delay on Source (DoS): the transmitter device already provides a delayed clock signal.

The SPC58EHx/SPC58NHx microcontroller has DoS capability as described in the following chapters.

1.1RGMII timing specification

The RGMII version 2.0 specification defines RGMII data-clock imbalances only for operation at 1000 Mbps, which uses both clock edges to sample data and control signals at the clock rate of 125 MHz (8 ns period). For 10/100 Mbps operations, the data signals are sampled on the rising clock edge and the control signals are sampled on both clock edges.

With slower clock rates, 2.5 MHz for 10 Mbps and 25 MHz for 100 Mbps, RGMII imbalances for 10/100 Mbps operations will have larger timing margins than running at 1000 Mbps, and therefore can be relaxed, such as maximum value, from 2.6 ns from 1000 Mbps to 160 ns for 10 Mbps and 16 ns for 100 Mbps.

Figure 1. RGMII RX timing diagram

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RGMII timing specification

Figure 2. RGMII TX Timing diagram

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SPC58EHx/SPC58NHx RGMII clocking schema

2SPC58EHx/SPC58NHx RGMII clocking schema

The TX_CLK can be selected using an internal PLL_ETH clock or the receive clock that is routed by the PHY transceive. When PLL_ETH is selected as reference clock for TX_CLK, MC_CGM Aux10 must be programmed to configure the reference clock for this source. Check the reference manual (see Section A.2 Reference documents) for detailed information on MC_CGM module.

There are three possibilities:

•XOSC

•a divided version of PLL0

•a divided version of RXCLK

The delay on the source can be enabled by programming the related mux: rgmii_txclk_dos.

The following figure shows the clock diagram for the RGMII clock selections and DoS clock selection:

Figure 3. SPC58EHx RGMII clock schema

2.1TX_CLK selection with Delay on Source (DoS)

DoS selection is the recommended configuration on this platform and can be performed referring to Figure 3. SPC58EHx RGMII clock schema, by setting the rgmii_txclk_dos = 1 and rgmii_txclk_sel = 0.

2.2TX_CLK selection with Delay on Destination (DoD)

In this mode no delay is introduced internally by the microcontroller.

This mode can be activated by:

•selecting the RX_CLK as TX_CLK (both for MAC / PHY)

–rgmii_txclk_dos=0

–rgmii_txclk_sel=1

•selecting the ETH_PLL divided output as TX_CLK

–rgmii_txclk_dos=0

–rgmii_txclk_sel=0

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Microchip KSZ9031RNX RGMII transceiver

3Microchip KSZ9031RNX RGMII transceiver

The KSZ9031RNX RGMII microchip complies with the timing requirements in the RGMII specification version 2.0 for internal PHY chip delay. For the transmission path, that is from MAC to KSZ9031RNX, the PHY transceiver by default does not add any delay to its GTX CLK, TEN and data lines. The GTX CLK delay is expected to be provided by the MAC.

The GTX_CLK on the transceiver is wired to the TX_CLK on the MAC side.It has been verified that, without DoS selection, on the SPC58NHADPT302S board, used as the reference PCB in these experiments, it is mandatory to program the KSZ9031RNX to add an additional delay when the giga link speed is negotiated. Without any delay on TX_CLK, issues occurred when ping the interface from a remote host, e.g. packet lost or no connectivity (see Section Appendix A Network setup).

In case of DoS selection, it has been demonstrated that the PHY does not need to introduce any further delay, so the microcontroller DoS logic satisfy the requirements. It does not need any extra delay on 100 Mbps speed .

3.1GTX_CLK delay from transceiver registers

In case of DoD, MAC does not provide any delay for the TX_CLK, the KSZ9031RNX can be used to provide it.

In fact, the KSZ9031RNX has skew pad registers for all RGMII pins (clock, control signals and data) to provide programming options to adjust or correct the timing relationship for each RGMII pin.

Here is a piece of the code invoked by the low-level driver to provide the delay on TX_CLK:

#define	MMD2_RGMII_CTRL_PAD_SKEW	4
#define	MMD2_RGMII_RXDATA_PAD_SKEW	5
#define	MMD2_RGMII_TXDATA_PAD_SKEW	6
#define	MMD2_RGMII_GTX_CLK_PAD_SKEW	8
#define	SPC5_RGMII_RX_CTL_VALUE	0
#define	SPC5_RGMII_TX_CTL_VALUE	0
#define	SPC5_RGMII_RXDATA_VALUE	0
#define	SPC5_RGMII_TXDATA_VALUE	0
#define	SPC5_RGMII_GTX_RX_CTL_VALUE	16
#define	SPC5_RGMII_GTX_TX_CTL_VALUE	(16 << 5) // 0.96ns

if (phydev->speed == SPEED_1000) { ksz9031_rgmii_pad_skew(phydev,MMD2_RGMII_CTRL_PAD_SKEW,

(SPC5_RGMII_RX_CTL_VALUE | SPC5_RGMII_TX_CTL_VALUE)); ksz9031_rgmii_pad_skew(phydev,MMD2_RGMII_RXDATA_PAD_SKEW,

SPC5_RGMII_RXDATA_VALUE); ksz9031_rgmii_pad_skew(phydev,MMD2_RGMII_TXDATA_PAD_SKEW,

SPC5_RGMII_TXDATA_VALUE);

ksz9031_rgmii_pad_skew(phydev, MMD2_RGMII_GTX_CLK_PAD_SKEW, (SPC5_RGMII_GTX_RX_CTL_VALUE|

SPC5_RGMII_GTX_TX_CTL_VALUE));

}

Where:

static void ksz9031_rgmii_pad_skew(struct phy_device *phydev, uint16_t reg, uint16_t delay)

{

int value;
/* RGMII Control Signal Pad Skew */	reg);
value = ksz9031_extended_read(phydev, 1, 2,
value |= delay;
ksz9031_extended_write(phydev, 1, 2, reg, value);
value = ksz9031_extended_read(phydev, 1, 2,	reg);

}

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	PCB trace routing on GTX_CLK
Note:	the transceiver software set is available within the SPC5Studio tool (https://www.st.com/en/development-tools/
	spc5-studio.html).

3.2PCB trace routing on GTX_CLK

The additional delay can be solved in the PCB. In this scenario, neither the PHY transceiver nor the MCU for DoS may need to be programmed.

The figure below shows an example of another PCB where the tune is created by a serpentine trace route on GTX_CLK for the KSZ9031RNX with a fixed length of 1 ns (how to calculate it is out of scope of this document).

Figure 4. PCB trace routing on GTX_CLK

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