ST TN100 User Manual

Features

VFQFPN2-48

■ Single-chip solution for ISM 2.45 GHz RF

transceiver

■ Built-in ranging capability for link distance

estimation

■ Modulation technique: chirp spread spectrum

(CSS)

■ FDMA support: 7 channels, 3 non-overlapping

■ Data rates: 2 and 1 Mbps; 500, 250 and 125

kbps

■ Adjustable output power from -33 dBm to

0dBm

■ Receiver sensitivity: -97 dBm @ 250 kbps,

FEC, and BER=10-3

■ In-band carrier-to-interference C/I = 0 to 3 dB

@ 250 kbps & C=-80 dBm

■ Supports external power amplifier to increase

output power

■ High precision ranging: 2 m indoors and 1 m

outdoors

■ Supply voltage range from 2.3 V to 2.7 V

■ Current consumption: 27 mA (RX), 30 mA (TX)

@ 0 dBm

■ Standby current with active RTC: 2 µA

■ RSSI sensitivity: -95 dBm

■ 32.768 kHz clock available for external MCU

■ Integrated fast SPI interface (27 Mbps)

■ Integrated MAC controller with FEC, CRC

checking

■ CSMA/CA, FDMA, and TDMA modes

■ Automatic retransmission and

acknowledgement

■ Automatic address matching

■ Industrial temperature range from -40°C to

+85°C

■ VFQFPN2-48 ECOPACK® package

TN100

High performance CSS transceiver

enabling location awareness

Preliminary Data

Description

The TN100 transceiver is a highly integrated mixed signal chip that uses the wireless communication technology CSS (chirp spread spectrum) developed by Nanotron Technologies.

With its unique ranging capability, TN100 can measure the link distance between two nodes. Thus, TN100 supports location awareness applications including location based services (LBS) and asset tracking (2D/3D RTLS). Ranging is performed during regular data communication and does not require additional infrastructure, power, and/or bandwidth.

For an even better ranging accuracy, a high precision mode is provided. SDS-TWR algorithm (symmetrical double-sided two-way ranging) allows superior accuracy even with the use of low cost crystals for the oscillators.

September 2008 Rev 1 1/235

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents TN100

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 TN100 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Built-in ranging capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Channelization using FDMA for improved coexistence . . . . . . . . . . . . . . 15

3.3 Incorporated digital dispersive delay-line (DDDL) . . . . . . . . . . . . . . . . . . 15

3.4 Selectable symbol durations and symbol rates . . . . . . . . . . . . . . . . . . . . 15

4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Analog part - TX and RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Digital part - programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.1 Digital part – ON Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.2 Digital part – PWD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 Commonly used set of register default values . . . . . . . . . . . . . . . . . . . . . 17

4.5 Programmable pull-resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Input and/or output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Configuring the digital I/O pins – D0 to D3 (pins 19 to 22) . . . . . . . . . . . . 21

5.3 Configuring the IRQ Pin – µCIRQ (pin 27) . . . . . . . . . . . . . . . . . . . . . . . . 22

5.4 Power-on reset – /POnReset (pin 30) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 Selecting a memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.2 128-byte programmable register block . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2.1 Accessing a register address location . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2.2 Setting a shadow variable for the RAM access register . . . . . . . . . . . . . 26

6.3 Correlator RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 Chirp sequencer RAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/235

TN100 Contents

7 Clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.2 32.786 kHz real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.2.1 Updating and reading the RTC through software . . . . . . . . . . . . . . . . . 28

7.2.2 Manually or automatically updating the RTC using TimeB packets . . . . 29

7.2.3 Using the RTC as wake-up event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.3 SPI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 32-MHz baseband clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.4.1 Stopping / enabling the 32-MHz baseband clock . . . . . . . . . . . . . . . 32

7.5 CSQ (Chirp Sequencer) clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5.1 Stopping / enabling the Chirp Sequencer clock (CSQ) . . . . . . . . . . . . . 33

7.5.2 Using the default matrix for transmission . . . . . . . . . . . . . . . . . . . . . . . . 33

8 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1 Power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.2 Power management module – ON and PWD sections . . . . . . . . . . . . . . . 34

8.3 Power management state model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.4 Power management fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.5 PowerDownModeFull state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.6 PowerDownModePad state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.7 PowerUp state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.8 Standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.9 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.10 Powering off the chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9 Programming interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1 SPI controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1.1 SPI controller and power management . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1.2 SPI controller and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.2 SPI bit ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.3 SPI signals: SpiClk, SpiSsn, SpiTxD, SpiRxD . . . . . . . . . . . . . . . . . . . . . 43

9.4 SPI TxD output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.5 SPI bus timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.6 SPI transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.6.1 Maximum transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3/235

Contents TN100

9.6.2 Bytes per transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.7 SPI interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.7.1 Four-wire configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.7.2 Three-wire configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.7.3 Multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.8 Read timing of the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.9 Write timing of the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.10 SPI address format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.10.1 Byte 1: instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.10.2 Byte 2: address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.10.3 N Bytes: data payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.11 SPI read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.12 SPI write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.12.1 Write access example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10 Chirp sequencer (CSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.1 Purpose of the Chirp sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2 Formatting the I and Q values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3 CSQ writing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11 Packet and MACFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.1 General packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.2 General packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.3 Preamble field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.4 SyncWord field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.5 MACFrame field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.5.1 MACFrame of a data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.5.2 MACFrame of an acknowledgement (Ack) Packet . . . . . . . . . . . . . . . . 61

11.5.3 MACFrame of a broadcast (Brdcast) packet . . . . . . . . . . . . . . . . . . . . . 61

11.5.4 Time beacon packet (TimeB) MACFrame . . . . . . . . . . . . . . . . . . . . . . . 62

11.5.5 Request to send (Req2S) packet MACFrame . . . . . . . . . . . . . . . . . . . . 63

11.5.6 Clear to send (Clr2S) packet MACFrame . . . . . . . . . . . . . . . . . . . . . . . 63

11.6 Tail field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

12 Frame control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4/235

TN100 Contents

12.1 Logical channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.1.1 Link control channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

12.1.2 User data channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.2 Link control management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

13 MACFrame configuration (Auto/Transparent) . . . . . . . . . . . . . . . . . . . . 67

13.1 Field for setting MACFrame auto and transparent mode . . . . . . . . . . . . . 67

13.2 MACFrame auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

13.2.1 Setting MACFrame auto mode (default) . . . . . . . . . . . . . . . . . . . . . . . . 68

13.3 MACFrame transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

13.3.1 Setting MACFrame transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . 68

14 Baseband RAM configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

14.1.1 Configurable spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

14.2 Memory usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

14.3 Auto/Duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

14.3.1 Setting Auto/Duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

14.3.2 Start addresses of the RX/TX data buffers . . . . . . . . . . . . . . . . . . . . . . 71

14.4 Auto/Simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

14.4.1 Setting Auto/Simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

14.4.2 Start addresses of the RX/TX data buffer . . . . . . . . . . . . . . . . . . . . . . . 72

14.5 Transparent/Duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

14.5.1 Setting Transparent/Duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

14.5.2 Start addresses of the RX/TX data buffers . . . . . . . . . . . . . . . . . . . . . . 73

14.6 Transparent/Simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

14.6.1 Setting Transparent/Simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

14.6.2 Start addresses of the RX/TX data buffer . . . . . . . . . . . . . . . . . . . . . . . 75

15 Buffer configuration (simplex/duplex) . . . . . . . . . . . . . . . . . . . . . . . . . 76

15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

15.2 Field for setting duplex and simplex mode . . . . . . . . . . . . . . . . . . . . . . . . 76

15.3 Duplex mode (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

15.3.1 Configuring the baseband RAM for Duplex mode . . . . . . . . . . . . . . . . . 76

15.4 Simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

15.4.1 Configuring the baseband RAM for Simplex mode . . . . . . . . . . . . . . . . 77

5/235

Contents TN100

16 Buffer swapping between TX and RX buffers . . . . . . . . . . . . . . . . . . . . 78

16.1 Enabling buffer swapping (duplex mode only) . . . . . . . . . . . . . . . . . . . . . 78

16.2 Buffer swapping in auto / duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . 79

16.3 Buffer swapping in transparent / duplex mode . . . . . . . . . . . . . . . . . . . . . 79

16.4 Buffer swapping and frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

16.5 Buffer swapping and short MACFrames . . . . . . . . . . . . . . . . . . . . . . . . . . 80

17 Buffer control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

17.1 Transmit buffer control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

17.2 Receive buffer control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

18 Buffer access synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

18.1 Flags and commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

18.2 Receive and transmit flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

18.3 Receive and transmit commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

19 Bit processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

19.1 Bit stream processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

19.2 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

19.2.1 CRC1 field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

19.2.2 CRC2 field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

19.2.3 CRC types 1, 2, and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

19.3 Bit scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

19.4 Forward error correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

19.5 Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

20 Chirp modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

20.1 Chirp spread spectrum (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

20.2 Secondary modulation systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

20.2.1 Upchirp/downchirp modulation system . . . . . . . . . . . . . . . . . . . . . . . . . 89

20.2.2 Upchirp/off modulation system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

20.2.3 Downchirp/off modulation system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

20.2.4 Physical channels and the on-off keying modulation systems . . . . . . . . 91

21 Local oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6/235

TN100 Contents

21.1 Purpose of the local oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

21.2 Calibrating the local oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . 92

21.2.1 Fields for updating the local oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 93

22 RF transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

22.1 Adjusting the baseband filter frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 94

22.2 Setting the power amplifier bias current . . . . . . . . . . . . . . . . . . . . . . . . . . 95

22.3 Adjusting the transmitter output power . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

22.3.1 Output power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

22.3.2 Fields for adjusting the RF Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 97

23 Media access control methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

23.1 Symbol definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

23.2 Direct access (DA) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

23.3 Random access (CSMA/CA) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

23.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

23.3.2 Carrier sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

23.3.3 Backoff time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

23.3.4 Retransmissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

23.3.5 Three-way handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

23.3.6 Three-way handshake and ARQ mode . . . . . . . . . . . . . . . . . . . . . . . . 103

23.3.7 Adjusting transmit power levels for three-way handshakes . . . . . . . . . 105

23.3.8 Prioritized access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

23.4 Time slotted access (TDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

23.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

23.4.2 Time slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

23.4.3 Logical channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

23.4.4 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

23.5 FDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

23.5.1 Field for enabling FDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

24 Data transmission control methods . . . . . . . . . . . . . . . . . . . . . . . . . . 110

24.1 Symbol definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

24.2 Error correction (ARQ scheme) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

24.3 Retransmit filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

24.4 Fragmentation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7/235

Contents TN100

24.5 Unconfirmed data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

25 Address formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

25.1 General address format / addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

25.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

26 Chip registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

26.1 Chip register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

26.2 Description of chip registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

26.2.1 0x00 – SPI bit order and IRQ pad configuration . . . . . . . . . . . . . . . . . 125

26.2.2 Configuring SPI transfers when the bit order is unknown . . . . . . . . . . 126

26.2.3 0x01 – Digital controller version number and wake-up time byte . . . . . 127

26.2.4 0x02 – Digital controller revision number and wake-up time . . . . . . . . 127

26.2.5 0x03 – Battery management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

26.2.6 0x04 – Digital I/O controllers and digital I/O alarm status . . . . . . . . . . 129

26.2.7 0x05 – Write enable digital I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

26.2.8 0x06 – Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

26.2.9 0x07 – Reset digital baseband/baseband clock and power down . . . . 133

26.2.10 0x08 – Power on/off baseband crystal and clock . . . . . . . . . . . . . . . . . 134

26.2.11 0x09 – Setting SPI pads as pull-up or pull-down . . . . . . . . . . . . . . . . . 135

26.2.12 0x0A – Setting additional pads as pull-up or pull-down . . . . . . . . . . . . 136

26.2.13 0x0B – Writing pull-up/pull-down settings to pads . . . . . . . . . . . . . . . . 138

26.2.14 0x0E – Baseband memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

26.2.15 0x0F – LO, BBTimer, RX/TX IRQ event status and enabling . . . . . . . . 139

26.2.16 0x10 – TX raw interrupt status and reset [Index] . . . . . . . . . . . . . . . . . 141

26.2.17 0x11 – RX Raw Interrupt Status and Reset [Index] . . . . . . . . . . . . . . . 142

26.2.18 0x12 – LO and BBTimer raw interrupt status and reset [Index] . . . . . . 143

26.2.19 0x13 – Enable transmitter interrupts [Index] . . . . . . . . . . . . . . . . . . . . 144

26.2.20 0x14 – Receiver interrupt enable [Index] . . . . . . . . . . . . . . . . . . . . . . . 145

26.2.21 0x15 – Local oscillator interrupt enable [index] . . . . . . . . . . . . . . . . . . 147

26.2.22 0x16 to 0x18 – RF local oscillator RX capacitors . . . . . . . . . . . . . . . . 147

26.2.23 0x19 to 0x1B – RF local oscillator TX capacitors . . . . . . . . . . . . . . . . 148

26.2.24 RF local oscillator controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

26.2.25 0x1D to 0x1E – RF local oscillator target value . . . . . . . . . . . . . . . . . . 149

26.2.26 0x1F – AGC threshold 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

26.2.27 0x20 – AGC threshold 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

26.2.28 0x21 – AGC hold frame/bit synchronization controls . . . . . . . . . . . . . . 151

8/235

TN100 Contents

26.2.29 0x22 – AGC change gain length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

26.2.30 0x23 to 0x24 – AGC integration time . . . . . . . . . . . . . . . . . . . . . . . . . . 152

26.2.31 0x25 – AGC value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

26.2.32 0x26 – RF AGC controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

26.2.33 0x27 – RC oscillator tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

26.2.34 0x28 to 0x29 – Baseband timer start value . . . . . . . . . . . . . . . . . . . . . 154

26.2.35 0x2A to 0x2B – ToaOffset for received Ack packet . . . . . . . . . . . . . . . 155

26.2.36 0x2C to 0x2D – Round trip time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

26.2.37 0x2E – Phase offset for RX data and Ack packets . . . . . . . . . . . . . . . 155

26.2.38 0x2F to 0x30 – ToaOffset for received data packet (read only) . . . . . . 156

26.2.39 0x2A to 0x31 – Transceiver SyncWord (write only) . . . . . . . . . . . . . . . 156

26.2.40 0x31 – Receiver mode controls (read only) . . . . . . . . . . . . . . . . . . . . . 157

26.2.41 0x32 – Receive correlator error controls . . . . . . . . . . . . . . . . . . . . . . . 158

26.2.42 0x33 to 0x34 – Transmit time slot start (write only) . . . . . . . . . . . . . . . 158

26.2.43 0x35 to 0x36 – Transmit time slot end (write only) . . . . . . . . . . . . . . . . 159

26.2.44 0x33 – Receiver encryption (read only) . . . . . . . . . . . . . . . . . . . . . . . . 159

26.2.45 0x34 to 0x35 – Receive FEC single bit error count (read only) . . . . . . 160

26.2.46 0x37 – Transmitter and receiver time slot control (TDMA) . . . . . . . . . . 161

26.2.47 0x38 to 0x39 – RX packet slot (read only) . . . . . . . . . . . . . . . . . . . . . . 161

26.2.48 0x38 to 0x39 – RX time slot start and packet slot (write only) . . . . . . . 162

26.2.49 0x3A to 0x3B – RX time slot end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

26.2.50 0x3C – ARQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

26.2.51 0x3D – RF chirp generator controls . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

26.2.52 0x3F – Correlator controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

26.2.53 0x40 – Frame synchronization and bit synchronization . . . . . . . . . . . . 165

26.2.54 0x41 – Bit synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

26.2.55 0x42 – Local oscillator, chirp sequencer and external PA controls . . . 166

26.2.56 0x43 – RF Rx low noise amplifier and TX power amplifier bias . . . . . . 167

26.2.57 0x44 – Transmitter output power (Data, TimeB, and BrdCast) . . . . . . 168

26.2.58 0x45 – Transmitter output power (Ack, Req2S, and Clr2S) . . . . . . . . . 168

26.2.59 0x46 – Quantization threshold for I . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

26.2.60 0x47 – Quantization threshold for Q . . . . . . . . . . . . . . . . . . . . . . . . . . 169

26.2.61 0x48 – Symbol duration, symbol rate, and modulation system . . . . . . 169

26.2.62 0x49 – CRC2, CRC2 encryption, FEC, and encryption clock mode . . 170

26.2.63 0x4A – Baseband buffer and MACFrame configuration . . . . . . . . . . . . 172

26.2.64 0x4B to 0x4C – Transceiver chirp matrix . . . . . . . . . . . . . . . . . . . . . . . 173

26.2.65 0x4D – TX underrun, CIFS waiting, and preamble/tail sequences . . . 174

9/235

Contents TN100

26.2.66 0x4E – Media access control for transmitter . . . . . . . . . . . . . . . . . . . . 175

26.2.67 0x4F – Back-off seed for back-off time . . . . . . . . . . . . . . . . . . . . . . . . 178

26.2.68 0x50 – Transmission encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

26.2.69 0x51 – Transmit scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

26.2.70 0x52 to 0x53 – TX data size in transparent mode . . . . . . . . . . . . . . . . 180

26.2.71 0x54 – Packet type for auto mode and TX source address . . . . . . . . . 180

26.2.72 0x55 – Start/stop transmissions and TX buffer fill command . . . . . . . . 181

26.2.73 0x56 – Start/stop receptions and RX buffer fill command . . . . . . . . . . 182

26.2.74 0x57 – Receiver decryption sequence reset . . . . . . . . . . . . . . . . . . . . 182

26.2.75 0x58 to 0x59 – RX data size in transparent mode . . . . . . . . . . . . . . . . 183

26.2.76 0x5A – RX ES and IS address matching, CRC1, CRC2, and ARQ . . . 183

26.2.77 0x5B – RX Data, Brdcast, TimeB, address mode, and ranging pulses 185

26.2.78 0x5C – Delay detection tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

26.2.79 0x5D – Receive bit detector controls (bit detectors) . . . . . . . . . . . . . . 188

26.2.80 0x5E – Bit detection gate size and adjustment . . . . . . . . . . . . . . . . . . 188

26.2.81 0x5F – Bit synchronization/unsynchronization thresholds . . . . . . . . . . 190

26.2.82 0x60 – Real-time clock TimeB transmission delay adjustment . . . . . . 190

26.2.83 0x61 – Real-time clock TimeB reception delay adjustment . . . . . . . . . 191

26.2.84 0x62 – Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

26.2.85 0x63 – AGC amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

26.2.86 0x64 – Alternative AGC and AGC range offset . . . . . . . . . . . . . . . . . . 193

27 Baseband registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

27.1 Baseband register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

27.1.1 Auto/duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

27.1.2 Auto/simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

27.1.3 Transparent/duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

27.1.4 Transparent/simplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

27.2 Description of baseband registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

27.2.1 Auto/duplex [Pg 0] 0x80 to 0x85 – source station address 0 . . . . . . . . 197

27.2.2 Auto/duplex [Pg 0] 0x88 to 0x8D – source station address 1 . . . . . . . 197

27.2.3 Auto/duplex [Pg 0] 0x90 to 0x95 – TX destination address . . . . . . . . . 198

27.2.4 Auto/duplex [Pg 0] 0x98 to 0x99 – TX data length and bits for sw usage . 198

27.2.5 Auto/duplex [Pg 0] 0xA8 to 0xAD – RX destination address . . . . . . . . 199

27.2.6 Auto/duplex [Pg 0] 0xB0 to 0xB5 – RX source address . . . . . . . . . . . . 199

10/235

TN100 Contents

27.2.7 Auto/duplex [Pg 0] 0xB8 to 0xB9 – RX data length and bits for SW usage 200

27.2.8 Auto/duplex [Pg 0] 0xE0 to 0xE5 – TX Real-time clock buffer . . . . . . . 200

27.2.9 Auto/duplex [Pg 0] 0xE8 to 0xED – RX Real-Time Clock buffer . . . . . 201

27.2.10 Auto/duplex [Pg 0] 0xF0 to 0xFF – RX Real-Time Clock buffer . . . . . . 201

27.2.11 Auto/duplex [Pg 1] 0x100 to 0x17F – register (mirrored) . . . . . . . . . . . 202

27.2.12 Auto/duplex [Pg 1] 0x180 to 0x1BF – encryption key . . . . . . . . . . . . . 202

27.2.13 Auto/duplex [Pg 1] 0x1C0 to 0x1CF – TX encryption clock value . . . . 202

27.2.14 Auto/duplex [Pg 1] 0x1E0 to 0x1EF – RX decryption clock value . . . . 203

27.2.15 Auto/duplex [Pg 2] 0x200 to 0x27F – register (mirrored) . . . . . . . . . . . 203

27.2.16 Auto/duplex [Pg 2] 0x280 to 0x2FF – RX data buffer . . . . . . . . . . . . . . 203

27.2.17 Auto/duplex [Pg 3] 0x300 to 0x37F – register (mirrored) . . . . . . . . . . . 204

27.2.18 Auto/duplex [Pg 3] 0x380 to 0x3FF – TX data buffer . . . . . . . . . . . . . . 204

27.2.19 Auto/simplex [Pg 0] 0x80/0x0FF – same as auto/duplex [Pg 0] . . . . . . 204

27.2.20 Auto/simplex [Pg 1] 0x180/0xEFF – same as auto/duplex [Pg 1] . . . . 205

27.2.21 Auto/simplex [Pg 2/3] 0x280 to 0x3FF – TX/RX data buffer . . . . . . . . 206

27.2.22 Transparent/duplex page [Pg 0/1] 0x080 to 0x1FF – RX data buffer . . 206

27.2.23 Transparent/duplex page [Pg 2/3] 0x280 to 0x3FF – TX data buffer . . 207

27.2.24 Transparent/simplex [Pg 0/1/2/3] 0x080/0x3FF – RX/TX data buffer . . 208

28 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

29 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

29.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

29.2 Nominal conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

29.3 General DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

29.4 Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

29.4.1 General parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

29.4.2 Programmable RAM for chirp sequencer . . . . . . . . . . . . . . . . . . . . . . . 214

29.4.3 Chirp specification (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

29.5 Receiver (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

29.5.1 General parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

29.5.2 Radio signal strength indicator (RSSI) . . . . . . . . . . . . . . . . . . . . . . . . . 215

29.6 Dynamic performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

29.7 Quartz controlled oscillator for reference frequency . . . . . . . . . . . . . . . . 216

29.8 Quartz-controlled oscillator for real-time clock (RTC) . . . . . . . . . . . . . . 216

11/235

Contents TN100

29.9 Local oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

29.10 Digital interface to sensor/actor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

29.11 Interface to digital controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

29.12 Power supply for the external digital microcontroller . . . . . . . . . . . . . . . 218

30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Appendix A Attributes and constants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Appendix B Default register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

12/235

TN100 Summary description

1 Summary description

The TN100 transceiver IC is designed to build robust, short distance wireless networks operating in the 2.45 GHz ISM band with extremely low power consumption over a wide range of operating temperatures.

The TN100 supports 7-frequency channels with 3 non-overlapping channels. This provides support for multiple physically independent networks and improved coexistence performance with existing 2.4 GHz wireless technologies. Data rates are selectable between

31.25 kbps and 2 Mbps. Due to the chip's unique chirp pulse, adjustment of the antenna is not critical. This significantly simplifies the system's installation and maintenance (“pick-andplace”).

The TN100 transceiver includes a sophisticated MAC controller with CSMA/CA and TDMA support as well as forward error correction (FEC) and 128-bit hardware encryption. It also provides scrambling, automatic address matching, and packet retransmission, thus minimizing the requirements for microcontroller and software.

Through its high-speed standard SPI interface, the TN100 can be interfaced with a wide range of external microcontrollers. It includes a 4-Kbit frame buffer which allows even very slow microcontrollers to work with the transceiver. This means that several receive and transmit frames can be stored simultaneously in the buffers. This solution eliminates the problems of different peak data rates between air and microcontroller interfaces.

In order to meet environmental requirements, ST offers these devices in ECOPACK packages. ECOPACK

packages are lead-free. The category of second Level Interconnect

is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Target applications

Target applications for the TN100 include:

● Asset tracking

● Enabling 2D/3D real-time location systems

● Security

● Industrial monitoring and control

● Medical applications

Development environment

● Simple API access to chip registers

● Easy-to-use evaluation boards for testing the TN100 in any environment

● Ready-to-customize development boards for quick application development

13/235

TN100 block diagram TN100

VDDA_ADC

SpiRxD

SpiTxD

SpiSSn

SpiClk

VDD1V2Cap

µCIRQ

µCReset

POnReset

Te st

TestRxN

TestRxP

TestCom

AnalogueVcc

AnalogueGND

DigitalVcc

Xtal32kN

Xtal32kP

RRef

Xtal32MN

Xtal32MP

VDDA_DCO

VBalun

DigitalGND

TxP

TxN

Tx/Rx

RxP

TxP

µCVcc

MCU

Chirp

Pulse

Sequencer

Digital

Processing

Battery

Digital I/O

Synthesizer

32 kHz

Osc

RTC

DAC

ADC

LPF

IQ DEMOD

VGA

VGA VGA

VGA

LNA

2 TN100 block diagram

Figure 1. Simplified TN100 block diagram

14/235

TN100 Key features

3 Key features

The TN100 transceiver incorporates robust wireless communication capabilities including:

● Built-in precise ranging capabilities

● Channelization using FDMA for improved coexistence

● Different symbol durations and symbol rates

● Standard set of default register values set into chip

● Digital Dispersive Delay Line (DDDL) incorporated in the chip

● Programmable pull resistors

3.1 Built-in ranging capability

The TN100 transceiver provides a built-in ranging capability. The chip can be enabled to provide Round Trip of Flight (RToF) information using a special Data / Ack packet transmission. Because the processing time for generating a hardware acknowledgment is known and the time of transmission a data packet is known, these two values can be used to calculate a ranging distance between the two TN100 stations.

3.2 Channelization using FDMA for improved coexistence

Channelization is the subdividing of the available frequency band (in this case, the 83 MHz ISM band) into many narrow frequency bands, which for the TN100 transceiver is 22 MHz channels. This increases coexistence with devices sharing the same ISM band. The TN100 transceiver channelizes the 2.4 GHz ISM band into multiple 22 MHz frequency channels using Frequency Division Multiple Access (FDMA). With register settings, the chip can be set to 80 MHz or 22 MHz signal bandwidth. The chip is set by default to use FDMA on startup and can be programmed to use one of multiple 22 MHz channels in the ISM band.

3.3 Incorporated digital dispersive delay-line (DDDL)

The TN100 transceiver incorporates a Digital Dispersive Delay Line (DDDL), which in previous chips was an external component. Reference values for I and Q can be stored in Baseband RAM. These values are used to detect incoming signals generated by another transceiver chip. The detectable signals can be one of the following:

● An Upchirp (linear frequency modulation, where frequency increases in time)

● A Downchirp (linear frequency modulation, where frequency decreases in time)

● An OffChirp, which is the absence of a chirp

Note: For more details, see Section 20: Chirp modulation on page 89.

3.4 Selectable symbol durations and symbol rates

The TN100 transceiver provides selectable symbol durations and symbol rates.

● Symbol durations include: 0.5 µs, 1 µs, 2 µs, and 4 µs

● Symbol rates include: 2 Mbps, 1 Mbps, 0.5 Mbps and 0.25 Mbps

Note: See Section 26.2.61: 0x48 – Symbol duration, symbol rate, and modulation system on

page 169.

15/235

Architecture TN100

4 Architecture

The TN100 is a extremely low power, highly integrated mixed signal chip incorporating both an analog and a digital part in one silicon die. This section provides a brief overview of the digital and analog parts of the chip.

4.1 Analog part - TX and RX

For transmission, the analog part of the chip converts data obtained from the digital part into chirp pulses and sends packets over the air using an RF link. For reception, it detects received chirp pulses into a form that can be used by the digital part.

4.2 Digital part - programming interface

The digital part of the chip provides an SPI interface for reading and writing to chip registers. Application data is written to chip buffers in the digital part, which is then provided to the analog part of the chip for transmission over the air. Data received from the analog part is provided to an application via buffers in the digital part. To achieve maximum power savings, the digital part of the TN100 transceiver is divided into two sections called an ON section (that is, always powered) and a PWD section (that is, powered during operating mode).

4.2.1 Digital part – ON Section

The ON section, which is always powered, contains the minimum number of required controls that are used to maintain the chip settings. It also is connected to the digital I/O pins as these pins are used for power management.

4.2.2 Digital part – PWD section

The PWD section, which is powered up only during operating mode, contains the remaining controls that are used when the chip is required for data transmission and reception.

16/235

TN100 Architecture

Analog

Application

data sent

and received over SPI interface

ON PWD

Always powered

Only powered when

chip is in

operating mode

Packets sent and received

over an RF

Link

PINS

4.3 Signal flow

Figure 2 illustrates the signal flow within the chip.

Figure 2. Signal flow in the TN100 transceiver

4.4 Commonly used set of register default values

The chip has been set with a number of default values that would be required for most standard applications to reduce the time required for chip initialization.

Note: A full listing of register default values is provided in Appendix B: Default register settings on

page 224.

4.5 Programmable pull-resistors

The TN100 transceiver uses programmable pull-resistors to lower the cost of the bill of materials. The following pads can now be set as either pull-up or pull-down:

● SpiClk (pin 15)

● SpiSsn (pin 16)

● SpiTxd (pin 17)

● SpiRxd (pin 18)

● POnReset (pin 30)

● TxRx (pin 9)

● µCIRQ (pin 27)

● µCReset (pin 28)

● Digital IO pads (pins 19 to 22)

17/235

Pin description TN100

15 18 19 21 22 23 242016 171413

48 43 42 40 39 38 3741454647 44

VDDA

RRfef

VSSA

VDDA_DCO

Xtal32kP Xtal32kN

Xtal32MP

Xtal32MN

Tx/Rx

VSSD VSSD

VDDD

VSSD

SpiClk

/SpiSsn

SpiTxD

SpiRxD

D0D1D2

VSSD

VDDD

VSSD

µCReset

µCIRQ

VDD1V2_Cap

µCVcc

/POnReset

VSSD

VDDA_ADC

VSSA

VDDA

VSSA

RxN

RxP

VSSA

TxN

TxP

VSSA

VBalun

VDDA

Pin 1 Identification

GND

Exposed die

attach pad

5 Pin description

This section provides a brief overview of the location and function of each pin.

Figure 3. Pinout

18/235

Table 1. Pin descriptions

Pin Signal Direction Description

1 VDDA Supply Power supply for analog parts

2 RRef Analog IO Pin for external reference resistor

3 VSSA Supply Power supply for analog parts

4 VDDA_DCO Supply Power supply for DCO

5 Xtal32kP Analog IO

6 Xtal32kN Analog IO Crystal 32768 Hz

7 Xtal32MP Analog IO

8 Xtal32MN Analog IO 32.0 MHz crystal oscillator

9 Tx/Rx Digital output Output signal to distinguish between transmit and receive

10 VSSD Supply Power supply for digital parts

11 VSSD Supply Power supply for digital parts

Crystal 32768 Hz, input from external 32768 Hz frequency reference

32.0 MHz crystal oscillator, input from external 32 MHz frequency reference

TN100 Pin description

Table 1. Pin descriptions (continued)

Pin Signal Direction Description

12 VDDD Supply Power supply for digital parts

13 VDDD Supply Power supply for digital parts

14 VSSD Supply Power supply for digital parts

15 SpiClk Digital input SPI clock

16 SpiSSn Digital input SPI slave selected

17 SpiTxD Digital output SPI transmit data (MISO)

18 SpiRxD Digital Input SPI receive data (MOSI)

19 D0 Digital IO Digital input or output line 0

20 D1 Digital IO Digital input or output line 1

21 D2 Digital IO Digital input or output line 2

22 D3 Digital IO Digital input or output line 3

23 VSSD Supply Power supply for digital parts

24 VDDD Supply Power supply for digital parts

25 Test Digital IO Pin for digital tests

26 µCReset Digital output Reset for external microprocessor

27 µCIRQ Digital output Interrupt request to external microprocessor

28 VDD1V2_CAP Supply 1.2 V digital power supply decoupling.

29 µCVCC Supply Switchable power supply for external microcontroller

30 POnReset Digital input Power on reset line

31 VSSD Supply Power supply for digital parts

32 VDDA_ADC Supply Power supply for analog parts (Rx ADC)

33 TestCom LF signal Test pin for analogue signals

34 VSSA Supply Power supply for analog parts

35 VDDA Supply Power supply for analog parts

36 VDDA Supply Power supply for analog parts

37 TestRxP LF Signal Test pin for RX signals

38 TestRxN LF Signal Test pin for RX signals inverted

39 VSSA Supply Power supply for analog parts

40 VSSA Supply Power supply for analog parts

41 RxN RF input Differential receiver input (inverted)

42 RxP RF input Differential receiver input

43 VSSA Supply Power supply for analog parts

44 TxN RF output Differential transmitter output (inverted)

45 TxP RF output Differential transmitter output

46 VSSA Supply Power supply for analog parts

Power supply for external balun (DC for TxP/TxN; needs to

47 VBalun Supply

48 VDDA Supply Power supply for analog parts

be blocked with an external capacitor in the 27pF to 47pF range close to the balun)

19/235

Pin description TN100

5.1 Input and/or output pins

Ta bl e 2 describes the digital pins and analog pins of the TN100 transceiver.

Table 2. Digital input pins

Pin Pin no. Direction Description

Analog pin. 32.768 kHz crystal oscillator pin 1 or input

Xtal32kP 5 Input

Xtal32kN 6 Output Analog pin. 32.768 kHz crystal oscillator pin 2.

Xtal32MP 7 Input

Xtal32MN 8 Output Analog pin. 32 MHz kHz crystal oscillator pin 2.

/POnReset 30 Input Power on reset signal.

SpiClk 15 Input

/SpiSSn 16 Input

for an external 32.768 kHz clock generator. Used to connect crystal or active frequency reference.

Analog pin. 32 MHz crystal oscillator pin 1 or input for an external 32 MHz clock generator. Used to connect crystal or active frequency reference.

The SPI Clock is generated by the microcontroller (master) and synchronizes data movement in and out of the device through the pins SpiRxD and SpiTxD.

SPI Slave Select (low active) is externally asserted before the microcontroller (master) can exchange data with the TN100 transceiver. Must be low before data transactions and must stay low for the duration of the transaction.

SpiRxD 18 Input SPI Receive Data (MOSI).

SpiTxD 17 Output SPI Transmit Data (MISO).

Distinguishes between the TX and RX phase. Can also

Tx/Rx 9 Output

µCReset 26 Output Reset for external microprocessor.

µCIRQ 27 Output Interrupt request to external microprocessor.

D0 19 Input/Output

D1 20 Input/Output

D2 21 Input/Output

D3 22 Input/Output

µCVcc 29 Output Analog pin. Power supply for external microprocessor.

be used to provide an external power amplifier control. Active Low during TX, otherwise High.

Digital Input or Output (programmable, see configuration bits below), line 0.

Digital Input or Output (programmable, see configuration bits below), line 1.

Digital Input or Output (programmable, see configuration bits below), line 2

Digital Input or Output (programmable, see configuration bits below), line 3. Note that a 32.768 kHz clock operates on this pin after reset/power up.

20/235

TN100 Pin description

5.2 Configuring the digital I/O pins – D0 to D3 (pins 19 to 22)

Each digital I/O pin can be configured as either an input or an output pin. Signal levels or an alarm occurrence can be reported at a digital I/O pin that has been set as input. Ta bl e 3 lists the fields are used for configuring digital I/O pins.

Table 3. Digital I/O pin configuration

Field Offset R/W Description

DioDirection 0x04 WO

DioOutValueAlarmEnable 0x04 WO

DioAlarmStart 0x04 WO

DioAlarmPolarity 0x04 WO

DioUsePullup 0x04 WO

DioUsePulldown 0x04 WO

Controls the direction of Digital I/O port. Set it as either an input or an output pin.

When a Digital I/O port is configured as input, this bit selects to be reported either the signal level at the port or the occurrence of an alarm.

Starts the alarm, and is set after the digital I/O port is configured to report the occurrence of an alarm.

When the digital I/O port is configured as an input that should report the occurrence of an alarm, then this bit is used to select the edge which should trigger the alarm.

When the digital I/O port is configured as an output, then this bit selects whether the value programmed in DioOutValueAlarmEnable or the feature clock should be driven out of the digital I/O port.

When set to true, a pull-up resistor is connected to the corresponding digital I/O pad.

When set to true, a pull-down resistor is connected to the corresponding digital I/O pad only, but when DioUsePullup is false.

Each digital I/O pin has one write strobe, as listed in Tab l e 4 .

Table 4. Digital I/O pin write strobe

Field Offset R/W Description

DioPortWe 0x04 WO

Writes the settings of the 6 configuration bits to the digital I/O controller.

Each digital I/O pin has one status bit, as listed in Tab l e 5 .

Table 5. Digital I/O pin status

Field Offset R/W Description

Each bit reports the signal level or the occurrence of an alarm at one of the four

DioInValueAlarmStatus 0x04 RO

21/235

digital I/O ports, where bit 0 belongs to D0, bit 1 belongs to D1, bit 2 belongs to D2, and bit 3 belongs to D3.

Pin description TN100

V level

Start of

internal reset

Time

min

delay

Stop

Threshold

levels

High ≥ V

DDD

* 0.7

Low

# V

DDD

* 0.2

5 µs

≥ 400 µs

IC Ready

5.3 Configuring the IRQ Pin – µCIRQ (pin 27)

The IRQ pin (µCIRQ) can be configured with either a high or low active polarity and can be driven as either push-pull or open-drain. The source of the interrupt can also be set.

The following fields are used to configure the IRQ pins as either low or high active, as well as either push-pull or open-drain:

Table 6. IRQ pin configuration

Field Offset R/W Default

IrqPolarity

(high/low active)

IrqDriver

(push-pull/open-drain)

0x00 RW

Defines the polarity of the IRQ signal as either high or low active. The default is low active.

Switches between push-pull or open-drain for IRQ output driver. The default is open-drain.

The following fields are used to drive the interrupt of the IRQ pin by either a transmitter interrupt, a receiver interrupt, a baseband timer interrupt, or a local oscillator interrupt:

Table 7. Interrupts driving the IRQ pin

Field Offset R/W Description

TxIrqEnable

RxIrqEnable

BbTimerIrqEnable

LoIrqEnable

0x0F RW

The transmitter interrupt can be enabled to drive the interrupt line. Default is disabled.

The receiver interrupt can be enabled to drive the interrupt line. Default is disabled.

The baseband timer can be enabled to drive the interrupt line. Default is disabled.

The Local Oscillator interrupt can be enabled to drive the interrupt line. Default is disabled.

5.4 Power-on reset – /POnReset (pin 30)

/POnReset signal is active low. Figure 4 shows a timing diagram for /POnReset.

Figure 4. /POnReset timing diagram

22/235

TN100 Memory map

Address

Memory

Typ e

Page

Select

Bits 6-0

11-10 9-8 7

Hex FFF

1 Correlator RAM Page 3

1 Correlator RAM Page 2

0 Register Block

1 Correlator RAM Page 1

0 Register Block

1 Correlator RAM Page 0

Hex C00 0 Register Block

Hex BFF

1 Chirp Sequencer Page 3

0 Register Block

1 Chirp Sequencer Page 2

0 Register Block

1 Chirp Sequencer Page 1

0 Register Block

1 Chirp Sequencer Page 0

Hex 800 0

Hex 7FF

Hex 400

Hex 3FF

1 Baseband Page 3

0 Register Block

1 Baseband Page 2

0 Register Block

1 Baseband Page 1

0 Register Block

1 Baseband Page 0

Hex 000 0

Correlator RAM

Chirp Sequencer

Baseband RAM

Unused

6 Memory map

This section describes the memory map of the TN100 transceiver. Procedures are provided for accessing the chip’s programmable Register Block, as well the Baseband RAM, Chirp Sequencer RAM, and Correlator RAM. Figure 5 shows the memory map of the TN100 transceiver.

Figure 5. Memory map

23/235

Memory map TN100

Ta bl e 8 lists the sections provided in the memory map.

Table 8. Memory map section

Address Memory type Description

0x000 to

0x3FF

0x800 to

0xBFF

0xC00 to

0xFFF

0x000 to

0x07F

Baseband RAM

Chirp Sequencer

RAM

Correlator RAM

512 bytes of Baseband RAM stores both data payload and MAC header values, depending on buffer configuration settings.

Delivers two sequences of 6-bit values that synthesize the I and Q signals of a symbol.

Stores the reference and threshold values for detection. It is are initialized with the FDMA, 4 µs default detector matrix. When other symbols are needed this register must be programmed with the appropriate values. The threshold must be programmed with the appropriate value in any case (even for the default matrix).

128-byte programmable chip register block provides chip configuration settings and is mapped to the entire memory of the TN100 transceiver.

Note: For a description of the Chirp sequencer, see Section 10: Chirp sequencer (CSQ) on

page 53. The Correlator RAM is described in Section 6.3: Correlator RAM access on page 26. The Register Block is described in Section 6.2: 128-byte programmable register block on page 25.

6.1 Selecting a memory address

There are two ways to access the TN100 transceiver memory map: direct and indirect access. The Register block is accessed using a direct access model. The Baseband, Chirp Sequencer and Correlator RAM blocks are accessed using an indirect access model.

To access one of these RAM blocks using an indirect access model through register 0x0E –

Baseband memory access:

1. Select the memory type (Baseband, Chirp Sequencer or Correlator) using bits DeviceSelect.

2. Select the page pointer using bits RamIndex.

3. A Read or Write operation can now be performed.

For example to write a value to the Chirp Sequencer RAM at location 0x185, write in register

0x0E – Baseband memory access:

1. Write DeviceSelect = 0x2 to select the Chirp Sequencer

2. Write RamIndex = 0x1 to select the RAM column 1.

3. Write to address 0x85.

For example to read a value from the Correlator RAM location at 0x280, write in register

0x0E – Baseband memory access:

1. Write DeviceSelect = 0x03 to select the Correlator RAM.

2. Write RamIndex = 0x02 to select the Threshold.

3. Read from address 0x80.

Note: For a Read or Write operation at an address higher than 0x7F, the absolute address is

always relative to the value stored in register 0x0E.

24/235

TN100 Memory map

Baseband RAM 3

128 bytes

0x300

0x37F

0x380

0x3FF

128 bytes

Baseband RAM 2

128 bytes

0x200

0x27F

0x280

0x2FF

128 bytes

Baseband RAM 1

128 bytes

0x100

0x17F

0x180

0x1FF

128 bytes

Baseband RAM 0

128 bytes

0x000

0x07F

0x080

0x0FF

128 bytes

≅

Page 0

Page 1

Page 2

Page 3

First mapping of register block

Second mapping of register block

Third mapping of register block

6.2 128-byte programmable register block

The TN100 transceiver provides a 128-byte programmable register block for chip configuration settings. The address space for the register is from 0x00 to 0xFF. However, it is mapped to three additional mapped registers within the 1024-byte memory space of the baseband RAM, where:

● Page 1 begins at offset 0x100

● Page 2 begins at offset 0x200

● Page 3 begins at offset 0x300.

These three mapped registers are logically equivalent to the register memory locations 0x00 to 0x7F. Figure 6 illustrates this mapping.

Figure 6. Register mapping in the 1024-byte TN100 memory space

Note: All user accessible registers in this register block is fully described in Section 26.2:

Description of chip registers on page 125.

6.2.1 Accessing a register address location

To access a memory location in the register only one SPI transfer is required, where:

● SPI Address[7] = 0

● SPI Address[6:0] = <offset address in register>

Note: A wraparound SPI burst transfer leads to unpredictable behavior. A wraparound SPI burst is

Either an SPI single byte operation or an SPI burst transfer can be used to access chip memory. The lower 7 bits of a given memory location are identical with the start address in the selected segment. SPI burst transfers are limited to 128 bytes (which is the segment size).

when the number of bytes to be accessed is greater than the number of bytes from the start address to the end of the segment.

25/235

Memory map TN100

6.2.2 Setting a shadow variable for the RAM access register

When bit 7 of the 10 bit memory address is 1, the RamIndex field must be set with the two highest bits of this address (shifting right by 8 positions). The lower 8 bits are directly used in the next SPI access, which writes this data.

To reduce the overhead caused by writing the RamIndex field for each memory access, it is recommended that an RamIndex shadow variable be maintained in software. This variable can be used to back up the last value of the RamIndex field. If address locations in the same segment are accessed sequentially, write operations to the RamIndex field can be eliminated by comparing the RamIndex value with the shadow variable.

6.3 Correlator RAM access

The Correlator RAM contains the reference sequences of the detector and the detection thresholds. Use Correlator Memory I for programming the In-Phase values of the detector and use Correlator Memory Q for Quadrature-Phase values. Use Correlator Memory Thresholds to set the thresholds for In-Phase and Quadrature-Phase detection.

A Correlator RAM page is selected by setting DeviceSelect and RamIndex as shown in

Ta bl e 9 .

Table 9. Selecting a correlator RAM page

DeviceSelect setting RAMIndex setting Selected correlator memory page

RamIndex = 0x0 (default value) I (RamD3IPatI)

DeviceSelect =

0x3

RamIndex = 0x1 Q (RamD3IPatQ)

RamIndex = 0x2 Thresholds (RamD3IThresholds)

RamIndex = 0x3 Unused

6.4 Chirp sequencer RAM access

The Chirp Sequencer (CSQ) RAM space contains the values for I and Q, which are used to calculate Upchirps and Downchirps. The CSQ is set with a default matrix that has a symbol duration of 4 µs (4000 ns) and a 22 MHz bandwidth.

A Chirp Sequencer RAM page is selected by setting DeviceSelect and RamIndex as shown in Ta bl e 1 0.

Table 10. Selecting a correlator RAM page

DeviceSelect setting RAMIndex setting Selected correlator memory page

RamIndex = 0x0 (default value) Column 0

DeviceSelect =

0x2

RamIndex = 0x1 Column 1

RamIndex = 0x2 Column 2

RamIndex = 0x3 Unused

Note: For more details about the Chirp Sequencer, see Section 10: Chirp sequencer (CSQ) on

page 53.

26/235

TN100 Clocking structure

Digital IO Control

ON PWD

DDDL Memory

SPI Controller

Real-Time Clock

CSQ Memory

Others

Baseband Control

Radio Control

Power Management

(4 kHz)

D[3:0]

Tx/Rx

SPI

µCirq

µCReset

µCVcc

Protection

32.786 kHz clock: SPI clock:

32 MHz Baseband clock:

CSQ (Chirp Sequencer) clock:

7 Clocking structure

This section describes the four clocks provided by the TN100 transceiver: 32.768 kHz clock, SPI clock, 32 MHz baseband clock, and the Chirp Sequencer (CSQ) clock.

7.1 Overview

The TN100 transceiver provides the following four clocks:

32.786 kHz clock – Used to run the real-time clock and power management.

SPI clock – Used for the SPI Controller and for the Digital IO Control used for

running the four digital IO pins. The frequency of the SPI clock is dependent on the

frequency required by the microcontroller. The maximum frequency is 27 MHz.

32 MHz baseband clock – Used for baseband control, radio control, and other baseband uses. The frequency of the baseband clock for the TN100 transceiver is

32 MHz and can be enabled or disabled by software.

CSQ (Chirp Sequencer) Clock – Used by the Chirp Sequencer (CSQ) Memory. The frequency of the CSQ clock is determined by dividing the Local Oscillator (LO)

frequency by 10. The CSQ clock can be enabled or disabled by software.

Figure 7. Clock structure

7.2 32.786 kHz real-time clock (RTC)

This real-time clock (RTC) runs at 32.768 kHz. It can be set or read through software using a 48-bit real-time clock value. As this clock is part of the ON section of the chip’s digital part, it is always powered (unless the chip is completely powered off) and can, therefore, be used for creating a wake-up time event.

27/235

Clocking structure TN100

ON PWD

Real-Time Clock

Power Management

(4 kHz)

D[3:0]

Tx/Rx

SPI

µCIRQ

µCReset

µCVcc

Protection

32.786 kHz Clock:

The real-time clock is also used to generate a 4 kHz clock (the Power Management clock) for use by the Power Management module in the ON section. Like the real-time clock, this slow clock is always available during power down mode to protect the connections between the SPI and the SPI Controller.

Figure 8 shows the real-time clock and Power Management modules that use the 32.768

kHz RTC.

Figure 8. 32.786 kHz real-time clock

7.2.1 Updating and reading the RTC through software

The 48-bit real-time clock is set and read through software. Since the real-time clock is updated every 1/(32.768 kHz), it is not directly accessible by the user. A RAM buffer RamRtcReg is used to hold the value of the internal real-time clock after it has been read. This buffer is also used to hold a value that will be written to the real-time clock.

Fields for updating RTC by software

Ta bl e 1 1 lists the fields used for updating the real-time clock with software.

Table 11. RTC and TimeB packets

Field Offset R/W Description

RtcCmdWr 0x62 WO Writes the 48-bit RTC value.

RtcCmdRd 0x62 WO Reads the 48-bit RTC value

48-bit RTC value read from the RTC by software or written to the RTC by software

RamRtcReg 0xF0 RW

Updating the value of the RTC

To update the value of the real-time clock, do the following

1. Write a 48-bit value for the real-time clock to the buffer RamRtcReg.

2. Write this buffer to the real-time clock using the write command RtcCmdWr.

28/235

TN100 Clocking structure

Reading the value of the RTC

To read the value of the real-time clock, do the following:

1. Read the real-time clock using the read command RtcCmdRd to place the 48-bit value of the real-time clock in the buffer RamRtcReg.

2. Read out the buffer RamRtcReg.

7.2.2 Manually or automatically updating the RTC using TimeB packets

The real-time clock can also be updated from TimeB packets that have been sent from a base station or other stations in a network. This updating can be performed automatically or manually.

If the updating is performed automatically, then when a TimeB packet is received, the RTC value in the packet is automatically written to the real-time clock.

If the updating is performed manually, then when a TimeB packet is received, the RTC value in the packet must be manually updated as described in Section 7.2.1: Updating and

reading the RTC through software on page 28.

Fields for updating RTC by TimeB packets

Ta bl e 1 2 lists the fields used for updating the real-time clock by TimeB packets.

Table 12. RTC and TimeB packets

Field Offset R/W Description

RtcTimeBAutoMode 0x62 WO

RtcTimeBRxAdj 0x61 WO Adjusts the RTC value for receiver delay.

RtcTimeBTxAdj 0x60 WO Adjusts the RTC value for transmitter delay

RamRtcTx 0xE0 RW

RamRtcRx 0xE8 RW

When set to 1, the RTC value is transferred in TimeB packets

The 48-bit RTC value that is to be transmitted (loaded/written) in a TimeB packet

The 48-bit RTC value that has been received in a TimeB packet

Manually updating the RTC

To manually update the real-time clock through the RTC value in a TimeB packet, enable Manual mode for TimeB packets by setting:

RtcTimeBAutoMode = NA_RtcTimeBAutoModeOff_BC_C (0x0)

This causes the 48-bit RTC value in the received TimeB packets to be stored in the real-time clock buffer RamRtcReg, where it can then be written to the real-time clock using the write command RtcCmdWr.

Automatically updating the RTC

To automatically update the real-time clock through from the RTC value in a TimeB packet, enable Auto mode for TimeB packets by setting:

RtcTimeBAutoMode = NA_RtcTimeBAutoModeOn_BC_C (0x1)

This causes the RTC values in received TimeB packets to be automatically stored in the real-time clock.

29/235

Clocking structure TN100

47 31 8

023

3 12

RtcWakeUpTime

(RTC)

Wake Uptim e

WakeUpti meB yte We

WakeUptimeByte

7.2.3 Using the RTC as wake-up event

The real-time clock can be used to create a wake-up time event at a predefined time. The field EnableWakeUpRtc enables the real-time clock to be used as a wake-up event.

The RTC wake-up time is set in RtcWakeUpTime but can only be accessed through the use of WakeUpTimeByte and WakeUpTimeWe.

The wake-up time is a 24-bit value split into 3 bytes. The field WakeUpTimeByte is used to set each of the three segments of the wake-up time (the segment to write is selected using the a byte-selector field WakeUpTimeWe). This wake-up time value is then compared to bits 31 to 8 of the real-time clock. When these values match, a wake-up event is then triggered. This process is shown in Figure 9.

Figure 9. Using real-time clock as wake-up event

Fields for setting RTC as wake-up event

Ta bl e 1 3 lists the fields using the real-time clock as a wake-up time event.

Table 13. Wake-up time fields

Field Offset R/W Description

Stores a one byte value for the wake-up time, which

WakeUpTimeByte 0x01 WO

WakeUpTimeWe 0x02 WO

EnableWakeUpRtc 0x06 RW Enable real-time clock as Wake-Up Source

is programed to the wake-up time RtcWakeUpTime using WakeUpTimeWe.

Loads the value of RtcWakeUpTimeByte to the appropriate byte of the wake-up time in the wake-up time circuitry.

7.3 SPI clock

The SPI Clock is an externally delivered clock provided to the chip through an SPI signal from a master device, such as a microcontroller. The frequency of the SPI clock is dependent on the frequency of the master device. The maximum frequency of the SPI clock, however, is 27 MHz. It is provided as one of the four signals of the SPI interface: SpiClk.

Figure 10 shows the Digital IO Control and DDDL Memory modules as well as the SPI

Controller that use the SPI clock.

30/235

+ 205 hidden pages