ST TDA911 Series, TDA9112, TDA9113, TDA9115, TDA9116 Application Note
AN1290
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®
Application Note
How to Use the TDA911X and Improve Performances
TDA911x Deflection Processors at a Glance
The TDA911x is a family of deflection processors f o r multisync monitors, incorporating horizontal
and vertical processing, geometry correction, dynamic corrections (focus and/or brightness etc.),
DC/DC conversi on and various safety and auxiliary functions. They are entirely controlled through
an I²C interface.
The TDA9112 was designed as an upgrade of the TDA9109/9111, using the same 32-pin shrink
DIP package. The pin-out remains nearly the same in order to simplify new layouts; howe ver some
minor changes were necessary, mainly to pack more functions inside. Those already f amiliar with
TDA9109/9111 will recognize all the functions and operation styles they are accustomed to use.
For low- and medium-range applications where certain sophisticated features are not required,
several different economical versions of the TDA9112 are available: TDA9113, TDA9115 and
TDA9116. Table 1 summarizes their respective features. All versions are pin- and software-
compatible, with minor exceptions
1
.
Recently, the most complete ver sion of the TDA9112 has been upgraded into the higher
performance TDA9112A. Improvements concern mainly geometry and focus corrections, but also
jitter behavior, B+ function, safety and I²C control. The design guidelines provide that the
TDA9112A should operate at once when fi tted in the place of an existing TDA9112 (even if the
ideal I²C register settings may differ slightly).
Section 2: Special Features of the TDA9112A summarizes the improv ements incorporated in
TDA9112A. For a detailed description of each, please ref er to the relevant chapter s.
1. Hard-wired H Moire function of the TDA9115/9116 replaces the Focus/Brightness functions.
16 Septembre 2002 Revision 1.1 1/62
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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AN1290
Table of Contents
Chapter 1 Main Characteristics of the TDA9112 Deflection Processor Family . . . . . . . . .5
Chapter 2 Special Features of the TDA9112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chapter 3 TDA9112 Family Pin Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Chapter 4 Horizontal Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1 Theory of Operation ...........................................................................................................11
4.1.1 Horizon tal Sect ion Structure ................................. ...... ..... ................................................. .................11
4.1.2 Digital Sync Detec tio n .......................... ...... ...... ..... ................................................... ..... .....................12
4.1.3 Composite Sync .................................................................................................................................12
4.1.4 Voltage-controlled Oscillator ..............................................................................................................12
4.1.5 PLL1 ..................................................................................................................................................13
4.1.6 Free-running Frequency and Range ..................................................................................................13
4.1.7 Frequency Precision ..........................................................................................................................14
4.1.8 PLL1 Inhibition ...................................................................................................................................15
4.1.9 Frequency Change Speed Limitation .................................................................................................16
4.1.10 PLL2, Duty Factor, ON/OFF ...............................................................................................................16
4.1.11 Soft-start ............................................................................................................................................17
4.1.12 Output Stage ......................................................................................................................................17
4.1.13 X-ray Protection .................................................................................................................................17
4.1.14 Lock-Unlock Detection .......................................................................................................................17
4.1.15 H Moire Cancellation ............................................ ...... ..... ............................................. .....................18
4.2 Application Hints ................................................................................................................19
4.2.1 Minimizing Jitter .................................................................................................................................19
4.2.2 Output Stage ......................................................................................................................................20
4.2.3 Enlarging the Frequency Range ........................................................................................................21
4.2.4 X-Ray Protection ................................................................................................................................22
Chapter 5 Vertical Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.1 Theory of Operation ...........................................................................................................23
5.1.1 Structure of V Section ........................................................................................................................23
5.1.2 Ramp Generator and AGC Loop .......................................................................................................23
5.1.3 Frequency Range and Precision ........................................................................................................24
5.1.4 Sync Detection ...................................................................................................................................25
5.1.5 A G C Loop Stability ................................................ ...... ..... ...... ...... ......................................................26
5.1.6 S and C Correction (TDA9112 to TDA9116) ......................................................................................26
5.1.7 Output Stage and Vertical Shift ..........................................................................................................28
5.1.8 Vertical Signal Management in the TDA9112A ..................................................................................29
5.1.9 ON/OFF Function ..............................................................................................................................30
5.1.10 V Lock/Unlock ....................................................................................................................................30
5.1.11 V Moire ..............................................................................................................................................31
5.1.12 V ertical Breathing Functi on (EHT Compens ation) .................................. ...........................................31
5.1.13 Implementing the Breathing Function ................................................................................................31
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5.1.14 Breathing Functions in the TDA9112A ..................................................................................... ..........33
5.2 Application Hints ................................................................................................................33
5.2.1 Coupling to Booster ...........................................................................................................................33
5.2.2 Ripple Rejection .................................................................................................................................34
5.2.3 Vertical Vibration ................................................................................................................................35
5.2.4 Leakage on Cs ...................................................................................................................................36
Chapter 6 Geometry and Focus Control Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.1 Theory of Operation ...........................................................................................................37
6.1.1 Geometry Corrections through E/W (PCC) Output ............................................................................37
6.1.2 Tracking with Horizontal Size .............................................................................................................39
6.1.3 Tracking with Horizontal Frequency ...................................................................................................39
6.1.4 Geometry Corrections through HPhase Control ................................................................................39
6.1.5 Tracking with Vertical .........................................................................................................................39
6.1.6 Dynamic Corrections .........................................................................................................................40
6.1.7 Horizon tal Dyna mi c Focus/Brightness ................................... ...... ..... ........................................ .........40
6.1.8 Vertical Dynamic Focus/Brightness ...................................................................................................41
6.1.9 Vertical Dynamic Focus .....................................................................................................................41
6.2 Application Hints ................................................................................................................42
6.2.1 E/W Output Stage ..............................................................................................................................42
Chapter 7 DC/DC Converter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7.1 Structure of the DC/DC Converter and B+ Loop ................... ....................... ......................44
7.1.1 Structure of the Converter Section ....................................................................................................44
7.1.2 External or Internal Sawtooth Configuration ......................................................................................44
7.1.3 B+ Output Polarity ..............................................................................................................................45
7.1.4 Soft-start ............................................................................................................................................45
7.1.5 Selecting the Trigger Tim in g ............................................................. ...... ..... ...... ................................46
7.1.6 Structure of the Regulation Loop (Step-up, Current mode) ...............................................................46
7.1.7 Structure of the Regulation Loop (Step-down, Current Mode) ..........................................................47
7.1.8 Structure of the Regulation Loop (Step-down, Voltage mode) ...........................................................48
7.1.9 Structure of the DC/DC Converter (Open Loop) ................................................................................49
7.2 Application Hints ................................................................................................................50
7.2.1 Parasites induced by DC/DC Converter (Timing Selection) ...............................................................50
7.2.2 Frame-top Distortion related to Keystone Correction .........................................................................51
Chapter 8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.1 Summary of Safety Functions ............................................................................................52
8.2 Early V Blanking and Lock/Unlock .....................................................................................53
8.3 Application Hints ................................................................................................................53
8.3.1 Using Inhibition Properly ....................................................................................................................53
Chapter 9 I²C Control Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.1 I²C Bus Reminder ...............................................................................................................55
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9.2 TDA9112 Family as I²C Bus Device ........... ........................................................................55
9.3 Receiving Data ...................................................................................................................55
9.4 Sending Data ............................ ...................... ...................... .............................................56
9.5 Register Organization ........................ ........................ ....................... .................................56
9.6 Management of Status Register and Sync Priority ............................................................58
Chapter 10 I²C Bus Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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AN1290 Main Characteristics of the TDA9112 Deflection Processor Family
1 Main Characteristics of the TDA9112 Deflection
Processor Family
Control
● Control of all functions and status reading through I²C interface (status reading is no t available
with the TDA9115).
● I²C settings take effect during the Vertical Oscillator Retrace for an improved screen aspect.
These parameters can be sent at any moment.
Horizontal
● Dual PLL structure
● Maximum frequency of 150 kHz
● Self-adaptable f requency range from 1 to 4.5 or more
● Improved ji tter control functions
● X-ray protection with digital filtering
● Lock/Unlock output; data also available on I²C bus (except for the TDA9115)
● ON/OFF Output function for Power Management
● I²C control of duty cycle, H-position and H-amplitude values with frequency tracking if required
● Smooth frequency transitions
● Internal soft-start
Vertical
● Constant amplitude, self-adaptive vertical ramp generator
● 50 to 185 Hz frequency range
● ON/OFF Output function for Power Management
● I²C control of V-amplitude, V-position, S- and C-correction amplitudes
● S-correction adapted to normal or super-flat tubes
● Lock/Unlock data by I²C (except for the TDA9115)
● Signal for early V Blanking.
East/West Pincushion Correction and Advanced Geometry Corrections
● Pincushion Parabola generator, with DC coupling possible for H-Size control
● I²C control of Pincushion, H-amplitude, Keystone and Corner corrections
● Corner correction, top and bottom independent, symmetric and asymmetric
— No symmetric corner correction for the TDA9115; no asymmetric corner correction for t he
TDA9113, the TDA9115 and the TDA9116
● H and V compensations of EHV variations (breathing inputs)
● Auto-tr acking of all the corrections above with H-frequency (if required) and H-amplitude
● I²C control of parallelogram and side-pin balance correction
● Auto-tr acking of all geometry corrections with V-amplitude and V-position
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Main Characteristics of the TDA9112 Deflection Processor Family AN1290
Dynamic Correction
● Auto tracking with V-position and V-amplitude
● Composite Dynamic output (e.g. focus or brightness) providing:
— Horizontal Parabola with I²C control of amplitude and symmetry (except for the
TDA9115/9116)
— Vertical parabola with I²C control of amplitude (TDA9112 only).
● Extra dynamic output with programmable polarity (e.g. separate V focus)
DC/DC Converter
● Control section for DC/DC converter, based on UC 3842 architecture
● Programmable for step-up or step-down configurations
● In step-down mode, control of power P-MOS transistor without tr ansformer, or N-MOS
transistor through tr ansformer.
● Internal soft-start
● Can operate as open-loop converter.
Miscellaneous
● Accepts positive and negative H and V sync signals
● Accepts Composite sync signals with the automatic management of serration pulses
● Sync on Green is not extr acted (this function is avail a ble in ST Video preamps)
● Vertical Moire compensation controlled by I²C programming
● Horizontal Moire compensation (I²C prog ramming), ma y be optimiz ed for combi ned or separate
structure (EHV/Scanning).
— TDA9112/9113/9116: self-contained
— TDA9115/9116: hardwired
● I²C bus can read Sync polarity and status, Lock/Unlock status and X-ray status (except the
TDA9115).
● I²C can reset X-ray status.
Table 1 summarizes the differences between the various family versions.
T a ble 1: Family Differences
Description 9112 - 9113 - 9115 - 9116 -
I²C Status reading (sync status, Lock/Unlock, X-ray) Yes Yes No Yes
Symmetrical Corner Correction Yes Yes No Yes
Asymmetric Corner Correction Yes No No No
Pin 11 function Comp DyCor Hor DyCor Moire Moire/DAC
DC/DC converter with internal sawtooth Yes No No No
I²C programmable DC/DC converter reference Yes Yes No Yes
Internal/Hardwired Moire Int Int Ext Int/Ext
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AN1290 Special Features of the TDA9112A
2 Special Features of the TDA9112A
The TDA9112A provides features and performances at least equal to those of the TDA9112, with
one exception: the DC/DC converter configuration using an internal oscillator has not been
continued because very few customers used it. Software compatibility is maintained.
The new or improved functions are listed below and details may be found in the relevant chapters.
The most important improvements concern geometry and focus correction.
Control
● 8-bit control of the H-size and H-position. Compatibility with the rest of the family is maintained
since only the LSB is affected.
● A dedicated bit enables the MCU to automatical ly detect whether the circuit present is the
TDA9112 or the TDA9112A.
Horizontal
● In PLL1, now there is a choice betw een 4 values of the charge-pump current , to better opti mize
jitter in relation to the horizon tal frequency.
● The indication of H-freque ncy Unlock can be made twice as fast as pre viously.
Vertical
● The block diagram of S and C linearity corrections has been modified to fit in the “tracking”
feature. As a result, it is possible to adjust amplitude or to switch between the VGA modes
without impairing linearity.
● The law of S correction has been modified, all owing perfect fitting to various types of tubes.
● Further to regular amplitude and centring settings (which maintain ideal linearity and
pincushion correction thanks to the “tracking” feature), the new prescale settings (wit hout
tracking feature) provide better flexibility, for instance to adapt one chassis to va rious tubes.
● New EHT compensation has a two-quadrant sensitivity adjustment (i.e. you can choose the
compensation sign as well). This allows perfect compensation throughout the H-frequency
range.
East/We st Pin Cushio n Correcti on and Advanced Geometry Corrections
● Two new controls of E/W are provided, namely S and W control. Their action is symmetrical
versus center. They leave top, bottom and middle of the screen unaffected:
— S correction inflates th e top 1/4 and defl ates the bottom 3/4 or the opposite,
— W correction inflates top 1/4 and bottom 3/4, or deflates both.
These corrections may help prevent certain distortions related to the DC/DC converter.
● A control bit can disable the tracking of E/W corrections versus H-amplitude.
● New EHT compensation has a two-qua dr ant sensi tiv it y adjust ment, in dependent of t he one for
the Vertical section.
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Special Features of the TDA9112A AN1290
Dynamic Correction (Focus/Brightness)
● The new composite H/V output can pro vide any signal polarity (concavity up or down; same
polarity for H and V).
● The signal at horizontal frequency, previously parabolic, may be set to any power index from 2
to 4. Indeed the useful range is f rom 2 t o 2.5, to adapt t o v a rious tube s a vailable on the market.
● Because the combination of high power index and phase setting may lead to high transients
during H flyback, means are provided to limit transients.
DC/DC Converter
As previously mentioned, the “Internal sawtooth” configurat ion is no l onger av ail able . Impro vement s
include:
● Choice of the maximum current threshold using pin 16 (Isense): previous 2V is convenient
when implementing a sawtooth oscillator, but the new value 1.2V (same as in UC 384x family)
is better adapted for Isense, as in current-mode step-up converters.
● A new control bit performs the ON/OFF function, independently of Horizontal and with soft-
start.
● In addition to the three possible phases for the DC/DC converter (HOut Up, HOut Down, after
HFlyback), a new option is: triggered with top of H sawtooth, with frequency divided by 2. It
may extend the range of step-up conv erters to higher frequencies. Nevertheless, caref u l
filtering and parasitic suppression will be necessary.
Miscellaneous
● B+ Safety: If the control bit is selected, the DC/DC converter will stop whenever HLock is lost.
Restart will take place in a soft way.
● Internal current sinks: E/W and Dynamic correction outputs (pins 11, 24 and 32) now have an
internal current sink which in most cases makes an external resistor unnecessary.
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AN1290 TDA911x Family Pin Review
3 TD A911x F amily Pin Review
The main features of the TDA9112, TDA9113, TDA9115 and TDA9116 are described in Table 2.
The additional feat ures for the TDA9112A are given in Section 2: Special Featur es of the
TDA9112A.
Table 2: TDA911x Pin Descriptions (Sheet 1 of 2)
Pin No. Pin Description
1 Receives Horizontal or Composite sync signals (TTL compatible, threshold approximately 1.4V, any polarity).
2 Receives separate V sync signals (same level as pin 1, any polarity).
Warning! The functionality of pins 1 and 2 may be affected by I²C.
3 Provides an early V blanking signal (amplitude 1V, High = Blank) to be ORed with V retrace ; combined with an H
Lock/Unlock signal (amplitude 5V, High = Unlocked).
Warning! Blanking and H Lock/Unlock functions are programmable through I²C.
4 Should be filtered to HGND, it improves H Jitter by filtering the H oscillator peak level.
5 (PLL2 filter) should be filtered to HGND (typical value 22nF), it improves jitter by filtering the level at which the
scanning is triggered.
6 The oscillator capacitor Co (typically 820pF) is connected between Pin 6 and HGND. A sawtooth at H frequency will
appear on this pin.
7 HGND; to be connected to General Ground pin 27 and to the components of H section only.
8 The oscillator resistor Ro (typically 5.2kΩ) is connected between Pin 8 and HGND. Co·Ro sets the free-running
frequency as Fo = 0.1215 / (Co·Ro). Voltage on pin 8 is always the same as on Pin 9.
9 The PLL1 loop filter is connected between pin 9 and HGND: 10nF to HGND, and in parallel: 1.8kΩ in series to 4.7µF
electrolytic. The electrolytic sets the speed of H-frequency change when sending a new video mode; the other
components are critical for H jitter characteristics. Voltage on pin 9 is proportional to H Oscillator frequency.
10 Should be filtered to HGND, it improves H jitter by filtering the DC level for H position. Capacitor on pin 10 also sets
the time constant for soft-start.
11 Output pin for composite dynamic H/V Focus (or Brightness). The waveform on this pin is the sum of two parabolas,
one at horizontal frequency, one at vertical frequency. The internal structure is NPN emitter-follower; a pull-down
resistor (10kΩ) is recommended.
The TDA9113 has an H-frequency parabola only.
On the TDA911 5 and the TDA9116, dyna mi c focus is absent, H-Moire c om pen sation is available in the place. To use
it, connect pin 11 to HGND through a resistor divider with ratio of 1000 to 2000, connect the low side of PLL2
capacitor to the middle point (rather than to HGND).
Warning! In the TDA9116, H Moire is I²C-programmable as either external (available on pin 11) or internal; in latter
case, pin 11 is a DAC with a voltage range between 0 and 5V.
12 H Flyback input, a v oltage compara tor (the base of a NP N transis tor with emitter ground ed). It should be connecte d to
a positive H flyb ac k p ulse; a r esist or con nected in s eries is nece ssary to li mit th e inpu t curre nt to less than 5 mA while
the pulse is positive.
13 Reference voltage, 8V nominal, to be filtered versus HGND. Since there is no reference voltage dedicated to the
14 Output of the op-amp that amp lifies the error si gnal of the D C/DC con ve rter feedbac k loop . Its v oltage sets the curre nt
15 Inverting input of the same op-amp.The feedback elements (typically 1MΩ parallel to 10nF) should be connected
Vertical section, pin 13 should also be used for biasing the non-inverting input of vertical booster through a suitable
resistor bridge.
level (represented by voltage on pin 16) at which the power MOS transistor will switch OFF.
between pins 14 and 15. The op-amp non-inverting input is not available; it is internally biased by a 4.8V reference
voltage, adjustable through I²C (e x ce pt the TDA9115).
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TDA911x Family Pin Review AN1290
Table 2: TDA911x Pin Descriptions (Sheet 2 of 2)
Pin No. Pin Description
16 When the DC/DC converter is used in the External sawtooth configuration, Pin 16 should receive a sawtooth (less
than 2V peak), either represen tativ e of the curre nt in the switch (current mode) or prov ided b y a n R/C oscil lator (op en
loop). In both cases, the po w er MOS tr ansist or is s wi tched O FF when pin 16 v o ltage e x ceed s one-thi rd of the v olta ge
on pin 14. Biasing Pin 16 with more than 6V will set the so-called “internal sawtooth”, in voltage mode configuration
(TDA9112 only).
17 & 18 High-impedance inputs which control H and V amplitude respectively. Each one should receive an image of the EHT
(for instance, a fraction of the Automatic Beam Limiter voltage) for size compensation versus EHT variations. Both
have the sa me act ive range: 1 to 8V, and sign: amplitude increases when pin voltage increases. The gains of the two
channels have to be separately set to the correct values by external resistive dividers.
19 Presents a DC level equal to Vertical sawtooth negative peak, it should be filtered to VGND to improve vertical jitter.
20 The capacitor on pin 20 s tores the AGC value to maint ain the c on sta nt Vertical Sawtooth amplitude regardle ss of th e
frequency. It should be a 0.47µF non-electrolytic capacitor.
21 Vertical ground. In addition to the main GND on pin 27, it should be only connected to Vertical section components.
22 A 0.15µF film capacitor shou ld be conne cted betwe en Pin 22 and V GND to obtain the Vertical Sawtooth with constant
amplitude (between 2 and 5V).
23 The same sawto oth is available on pi n 23 , buffered and wit h ad jus ta b l e a mpl itu de and offset for the control of vertical
size and position. The middle value of this signal is (3.5/8) of the reference voltage (pin 13). An equal voltage should
be derived from pin 13 through a resistive divider, to bias the Vertical booster positive input.
24 Provides the complete waveform to control Horizontal amplitude, including DC (for H Size, with EHV compensation),
Pincushion, K e yston e and s ymm etric Corner. It has the structure of an Em itter follower; a pull-down resistor (10k Ω) is
necessary. Voltage range is 2 V to 8.5V. The TDA9115 does not have corner correction.
25 High-impedance comparator input for X-ray detection, with 8V threshold. It should be filtered to GND (VGND is
recommended).
26 HOut: open-collector NPN with more than 30mA capability. The NPN is switched OFF (pin 26 High) when the
scanning transistor is to be switched OFF (“Reverse control”). An external pull-up resistor connected to pin 29 is
necessary. Direct control of a bipolar NPN driver is possible.
27 General GND. The general GND track should enter the IC area by this pin, then be connected only to the special H
and V ground tracks.
28 BOut: open-collector NPN, with more than 10mA capability. An external pull-up resistor connected to pin 29 will be
necessary to make the power switch conductive.
Warning! The polarit y should be selec ted b y I²C. By default: High level (NPN OFF) is meant to make the power switch
conductive (adapted for N-type power switches).
29 General supply (10.8 V to 13.2 V, 70 mA). It should be filtered to pin 27.
30 & 31 SCL and SDA for the high-speed I²C bus. Threshold voltage is 2.2V typically.
32 Extra V Focus output, to allow separate H Focus and V Focus channels. It provides a parabola at Vertical frequency.
It presents the structure of an emitter follower and requires a 10kΩ pull-down resistor to GND. Quiescent voltage is
4V.
Warning! The signal polarity may be selected through I²C (Default is: Downwards Concavity ∩).
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AN1290 Horizontal Section
4 Horizontal Section
4.1 Theory of Operation
4.1.1 Horizontal Section Structure
The TDA9112 horiz onta l sectio n is s imilar t o the T DA9109/9111. It includes a sa wtoo th osci llator, a
sync detector, two phase-locked loops (PLLs) and an output st age. Moreover, X-ray protection and
PLL1 lock/unlock detection are provided.
Figure 1: H Oscillator
V9
I8
0.5 x I8
4 x I8
8 6
R0
S
6.4V
R
1.6V
C0
PLL1 locks the oscillator frequency to the HSync frequency, then adjusts its phase, until the sync
pulse coincides with an adjustab le level on the sawtooth. Changing the le v el is us ed to adjust the Hposition.
PLL2 adjusts the phase of the output stage (compensating for the storage time of the H scanning
transistor), until the middle of the H flyback pulse coincides with a predetermined level on the
sawtooth.
The horizontal phase and duty f actor may be adjusted b y I²C programming ( Registers 00h and 01h) .
All voltage values meaningful for the H section (like comparator and oscillator thresholds) are
derived from a common reference voltage (between 7.4V to 8.6V with 8V typical) and keep a
constant ratio with this reference.
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Horizontal Section AN1290
4.1.2 Digital Sync Detection
The H/HV sync pulse is detected on pin 1 by a comparator with hysteresis, compatibl e with the
standard TTL. It is intended for digital sync only (separate or composite). The IC synchronizes on
the pulse front edge. A pull-down resistor (200 k
Ω) is included.
Sync polarity recognition is performed as follows: The comparator output controls the charge or
discharge of an internal 50pF capacitor with ±0.1µA current . Depending on the polarity of the sync
signal, the capacitor voltage will either drift towards the ground or the 8V supply. A comparison of
capacitor voltage with a 4V threshold indicates the sync polarity. The recognition delay is
approximately 2ms (typi cal) with a minim um value of 0. 75 ms. This w a y, in the event of a Composite
sync signal, vertical sync pulses up to 0.75ms will not be unduly int erpreted as a change in HSync
polarity.
Þ Serration pulses: When they are missing, the inhibition of PLL1 during Vertical sync pulse
(described later) prevents any disturbance of the Horizontal oscil lator. F o r this purpose, the
composite V pulse must be recogniz ed within one horizontal half-period (see Section
4.1.3: Composite Sync).
4.1.3 Composite Sync
In order to extra ct the VSync pulse from the composite signal, the duration of each sync pulse is
compared with the horizontal period. As soon as the durati on of a pulse e xceeds 21% (minimum) of
the horizontal period (30% typical), this pulse is recognized as a VSync pulse.
The VSync duration measurement uses an internal capacitor and a current source that keeps a
constant ratio with Horizontal oscillator current source. Consequently, the system will work as
indicated only if the recommended va lue of 820 pF for oscillator capacitor Co is applied.
Otherwise for instance , when using a higher val ue, at the same frequency, all charge currents will be
higher and therefore the rec ogni tion delay will decrease possibly to less than 21% of the horizontal
period. This would lead to the incorrect detection of the Vertical Sync signal.
See Section 9: I²C Control Section for more information about sync management through I²C
programming.
4.1.4 Voltage-controlled Oscillator
The H oscillator is similar to the one in the TDA9109/9111. See Figure 1 for the schematic diagram
and Figure 2 for w a veforms.
A voltage-follower stage imposes the same voltage on pin 8 as on pin 9, which is the PLL1 output.
The current in pin 8 is then fixed to:
V
8
I
-------=
8
R
0
Current mirroring provides two current sources, with values of 0.5 x I
(“source”) and 4 x I8 (“sink”).
8
Two comparators with thresholds of respec tivel y 1.6V and 6.4V control a toggle that s wit ches ON or
OFF the 4 x I
Supposing this latter source is initially OFF, capacitor C
until the 6.4V threshold is reached. At that moment, the 4 x I
establishing a global discharge current equal to 3.5 x I
12/62 STMicroelectronics Confidential
current source.
8
dV
------dt
dV
-------
dt
0.5xI
---------------- -=
C
3.5xI
---------------- -=
C
will charge at a rate:
0
8
0
current source is switched ON,
8
. Discharge will continue at a rate:
8
8
0
Obsolete Product(s) - Obsolete Product(s)
AN1290 Horizontal Section
until the 1.6V threshold is reached; then a new charge phase starts. As a result, the voltage on pin
6 will be a sawtooth with a (6.4-1.6 )V ampli tude and a period of:
∆ThC0x ∆V
Replacing I
exceeds 1.5 mA, the oscillator compon ents will not work in the optimal conditions; mor eover, if
If I
8
at the same time V
by its val ue and taking the reverse , one obtains the theoretical formula:
8
is higher than 6.2 V, there is a risk of saturation of internal circui try. These two
8
æö
---------------- -
èø
èø
0.5xI
f
-----------------------------------------------------------
h
2.286x R0xC0x∆V()()
1
æö
reasons combined led to recommend R
8
V
8
0
1
---------------- -+
3.5xI
8
>4.2kΩ.
with∆V6.41.6
------------------------------------------ -==
10.97x R0xC
– 4.8===
V
8
()
0
Note: All details relative to the oscillator waveform are represented in Figure 2 with: Period = 12 µs,
Flyback duration = 3.2 µs, Duty factor = 50%, Sync pulse duration = 1 µs, Storage time = 2 µs.
4.1.5 PLL1
The aim of PLL1 is to control the osc illator 's fr equency and phase , until the fr ont edge of the H sync
pulse just coincides with a determined (and adjustable) voltage (V
Two current generators (one “source” and one “sink”) are connected to the PL L1 output (pin 9). This
pin is connected to an external low-pass filter, it controls pin 8 voltage through a voltage follower.
● If the front edge of the HSync pulse arrives before the V
φ
current is activated in the interval: this will increase the voltage and the oscillation frequency.
) on the sawtooth.
φ
point on sawtooth, the “source”
● If the V
point on sawtooth arrives before the HSync pulse front edge, the “sink” current is
φ
activated in the interv al, this will decrease the oscillation frequency;
● when PLL1 is locked, there i s a very narrow “source” current pulse just before the V
point and
φ
a very narrow “sink” pulse just after; therefore the voltage on pin 9 remains stable.
may be adjusted by ±0.6V around the a v erage v alue of 3.4V, through I²C programming ( Register
V
φ
01), allowing a cont r ol of t he horizont al phase, up to ±10% of a period. F or an opt im um ji tter, pin 10
should be filtered to GND (no limit on the capacitor value. It also sets the soft-start time constant).
The PLL1 capture range is large enough to synchronize with all incoming sync frequencies.
Normally, both “sink” and “source” currents should be set to 1mA, and the recommended
components in PLL filter are optimized accordingly. Nevertheless, the current value may be
switched to 0.3 mA by I²C programming (Sad16h/d3:2). Jitter may be improved by switching to
0.3 mA at low frequencies and to 1 mA at high frequencies. The default value is 0.3 mA.
In the TDA9112A there are four values for the current that can be selected by I²C programming
(Sad16h/d3:2).
4.1.6 Free-running Frequency and Range
When HSync pulses are absent or at low frequency, the PLL1 output will clamp to 1.33 V, which
corresponds to the free-run frequency (f
f
------------------------------------------ -
0
10.97x R0xC
). From the formula for frequency, we get:
0
1.33
()
0.1215
------------------ -==
R0xC
0
0
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Horizontal Section AN1290
When HSync pulses are receiv ed, the v oltage on pin 9 will i ncrease until the loc al oscillator mat ches
the incoming frequency. Since the range for pin 9 voltage is between 1.3V and 6.2V, the relative
capture frequency range (ratio of maximum to minimum frequency) is:
6.2
------- -4.77=
1.3
4.1.7 Frequency P recision
All the terms in the f0 equation have a spread. Both voltages are derived from the same reference,
their ratio will remain quit e accurate. In regards to the other v a riables, we have to consider a
tolerance of ±1% for R, ±5 or 10% for C and ±6% for the numerical fact or which incorporates a
current ratio.
Consequently the free-running frequency can vary from ±12 or 17% of the designed value, using
safety marg ins can reduce the usab le relati ve frequency r ange b y 2 x 12% or 2 x 17%; or ±9% if y ou
can afford a ±2% capacitor.
An other consequence of the free-running f requency spread is to mak e the design of a B+ conv erter
more difficult, because in free-running mode, the B+ converter may have to follow the oscillator
frequency down to l o w values. (This may be av oided if fake HSync pulses are sent by t he MCU a t a
convenient frequency, as soon as there is no sync coming through the input plugs.)
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Figure 2: H Oscillator Waveform
V
6.4V
5
4V
V
φ
Duty factor
setting voltage
PLL2 Threshold
0
Sync
pulse
V26
Fly
back
t
st
Range for PLL2
5
Forced OFF
1.6V
10 12µs
Forced ON
4.1.8 PLL1 Inhibition
The PLL1 operation remains undisturbed if one (an d only one) sync pulse front edge arriv es in each
horizontal period, in phase with the V
sync pulse, this condition is no longer fulfilled during Vsync, when there are no serration pulses.
point on each sawtooth. In the event of a composite digital
φ
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When PLL1 endures this sev ere di sturbance , it requires some time to reco v er the proper phase. As
this could entail a visible distortion on top of the screen, the TDA9112 has been provided with a
PLL1 inhibition fe ature: th e two current sour ces of PLL1 will be turned OFF during the Vsync pulse
and 2 complete lines later. Internal inhibition is activated only by the Vsync pulse extracted from
composite sync.
This features may be disabled through I²C programming (Sad16h/d1).
4.1.9 Frequency Change Speed Limitation
It is well-known that when receiving a new horizontal frequency, PLL1 should not synchronize
immediately with the new frequency, especially when it is lower than the former one. Otherwise the
horizontal scanning tr ansistor w ould conduct for a longer period of time, while the v alue of B+ w ould
not have ti me to de crease to its newly assigned lower value. This would lead to excessive current
and voltage and possibly destroy the transistor.
In the TDA9112, the PLL1 changing speed has been limited to a safe value.
Warning! This limitation is ineffective when imposing a frequency jump by switching Ro or Co.
4.1.10 PLL2, Duty Factor, ON/OFF
Supposing the oscillator is loc ked to the Hsync pulse, then PLL2 controls the H scanning tra nsi stor
so that the flyback takes place at a definite point on the sawtooth. (Refer to Figure 2.)
For this purpose, a positive flyback signal must be sent to pin 12, which is connected to a voltage
comparator with a thr eshold of one V
other possibilities, pin 12 may be connected to a secondary of the scanning transformer through a
current-limiting resistor. In order to allow lower values of the limiting resistor, and therefore faster
transmission of the flyback data, the maximum input current into this pin has been increased to
5mA.
The reference point for PLL2 is the middle of the flyback pulse (as seen on pin 12). PLL2 will
manage to make it coincide with the 4V point on the sawtooth.
PLL2 is a classical charge pump PLL. Its output (pin 5) must be connected to a capacitor as a lowpass filter. For the entire fl ybac k puls e durat i on, one of th e tw o 0. 15-mA internal curr ent gen erat ors
connected to pin 5 will be activated:
● the source current, when the ramp voltage is lower than 4 V,
● the sink current, when the ramp voltage is higher than 4 V.
With the flyback pulse centr ed on the 4V point, the capacitor will receive a null global charge for
each period.
The capacitor value is not critical (22nF for good jitter). With a low capacitor value, PLL2 will more
rapidly recover of any change in the H transistor storage time caused by a black/white video
transition. This will mini mize the corresponding distortion of vertical lines.
, and to the Ground through a 20kΩ (typical ) resistor . Among
BE
The Pin 5 voltage directly controls which point on the sawtooth will trigger the scanning transistor
switching OFF. The possible range for pin 5 is between 1.6V and 4V, allowing a transistor storage
time between 0 and:
t
Similarly, the scanning transistor ON state is triggered when the oscillator sawtooth reaches a
determined voltage; the offset between OFF and ON voltages is constant (adjustable by I²C). As a
result, the TDA9112 will maintain constant duty factor, regardless of PLL2 voltage variations . The
typical Duty factor range is between 30% and 65% and is selected through I²C programming
(Register 00). This is the OFF duty factor, i.e. the ratio of the OFF drive time to the total period.
16/62 STMicroelectronics Confidential
æö
0.438x T
èø
æö
èø
–
h
flyback
---------------------2
Obsolete Product(s) - Obsolete Product(s)
AN1290 Horizontal Section
Hex code 00 corresponds to a 65% duty factor. This is the default value at start-up, in order to
minimize the stress on the scanning transistor.
4.1.11 Soft-start
The TDA9112 is equipped with a self-contained soft-start. When switching ON, HOut will remain
inhibited until the supply voltage ramps up to more than 8.5V. Afterwards, the initial duty factor will
progressiv ely d ecrea se f rom 85 % to 65 % (t he scannin g t r ansist or wil l be contr olle d OFF for 65% of
the period), then to the v al ue that has bee n set through I²C progra mming. The same ev ents will take
place in the reverse order when the supply ramps down through a 6.5V threshold (t hresholds for
TDA9112A: 8.0V and 6.8V).
The time constant that controls the soft-start is the charge rate of H-positi on capacitor on pin 10.
The soft-start is effectiv e when swit ching ON and when resett ing the HOut inhib ition. It als o controls
the duty factor of the DC/DC converter (except in the so-called “internal sawtooth, voltage mode
configuration”). For more information, refer to Se ction 7: D C/D C Converter Se ction.
4.1.12 Output Stage
The drive signal f or the H scanning transistor is available on pin 26, which is connected to the
collector of the output NPN transi stor. The transistor is conductive (pin 26 LOW) when the H
scanning transistor is t o be ON and vice-v er sa. Pin 26 sh ould be connected t o the supply th rough a
pull-up resistor . Of cour se, some ki nd of driver st age is mandatory to control the scanning tr ansistor
base.
The saturation v oltage on pin 26 (less than 0. 4V f or 30 mA) is lo w enough to all ow d irect control of a
bipolar driver . Ne v ertheless and for ot her reasons we recomme nd keeping an A C coupling bet ween
pin 26 and the driver. For more information, refer to Section 4.2.2: Output Stage.
The output transistor is forced ON during the negative slope part of the sawtooth. It is forced OFF
during flyback (as seen on pin 12), and this safety function has the priority over any other control.
The goal is to prevent the scanning transistor from turning ON again, while it still sustains the high
flyback voltage.
4.1.13 X-ray Protection
Pin 25 is a comparator with 8V (typical) threshold for X-ray detection. A voltage higher than 8V on
pin 25 will stop H scanning (and the DC/DC converter as well). This situation will last until some
Reset takes place, for instance by switching the supply voltage on pin 29, OFF and ON again
(resetting threshold: 6.5V typ at supply fall-down).
In fact, once the voltage on pin 25 exceeds 8V, it must remain at this value for 2 lines befor e the Xray safety is triggered. This digital filtering provides a protection against very short parasitic
voltage, affecting pin 25, due for instance, to an arcing of the tube.
It is possible to read the current state of X-ray protection through the I²C bus. It is also possible to
reset it in the same way (Sad16h/d7).
4.1.14 Lock-Unlock Detect ion
Remembering how the PLL1 works with two current generators (one sink and one source), it
appears that when PLL1 is loc k ed bot h genera tors ar e OFF almost al l t he time; when out of phase,
one generator will be ON f or part of the period. When frequencies differ, one gen erat or or the other
will be ON for approximately half the time (mean value).
This is used to build a lock- unloc k detector (Figure 3) where a gate output is LOW whenever one of
the current sources is ON. It controls very low charge and discharge currents to an internal
capacitor. The capacitor voltage will take a value of approximately 8V when PLL1 is locked, and
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Horizontal Section AN1290
approximately 4V when it is unlocked. The last elements are an internal comparator referenced to
6.25V (with hysteresis) and a CMOS inverter ; you will find on its output pin 3 a HIGH state when
PLL1 is unlocke d. The same data can also be read in the IC through the I²C bus. Nevertheless, a
Read request is necessar y in this case.
There may be an ill-defined state and erratic pulses may appear during Lock
↔ Unlock transitions,
mainly when oscillator f requency approaches Loc k state . The reasons f or this are basic and cannot
be avoided. To pre vent malfunctions, provide an external supplementary delay. Since the delay is
external, it can be made longer f o r the Unlocked
pulses), while being kept very short for the opposite Locked
→ Locked transiti on (thus avoiding the parasitic
→ Unlocked transition, when
emergency measures should be triggered in a short time.
Because some customers asked for a shorter reaction time to transition Locked
→ Unlocked, the
TDA9112A pro vides an option through I²C progr amming (Sad1Fh/d2) for a dela y divided b y two . Be
aware that as a conseque nce, a very long composite VSync signal wit hout serration pulses could be
unduly interpreted as a loss of locking.
Further to this indication, as soon as an Unlock state is detected, the oscillator frequency change
rate is decreased. When switching from High to Low frequency, the B+ regulation loop will have
enough time to decrease the B+ value accordingly, thus preventing th e destruction of the scanning
transistor by overcurrent and overvoltage. According to the typical application schematic, the
frequency will be reduced by approximately 0.1 kHz/ms.
Since pin 3 is also used for V b lanking, levels on pin 3 are defined as follows:
● approximately 0V: locked, not blanked
● higher than 5V: unlocked
● the blanking signal adds to Lock/Unlock level (+1V if Blanked).
The Lock/Unlock signal is availab le only if selected through I²C programming (Sad16h/d0).
Figure 3: Lock/Unlock
To I²C
6.25V
3
1V = Lock, Blank
0V = Lock
6V = Unlock, Blank
5V = Unlock
I
SINK
I
SOURCE
8V
4.1.15 H Moire Cancellation
The Moire phenomenon only takes plac e on color screens and when dis playi ng grey areas resulting
from an alternation of black and white dots.
It may happen that the succession of black and white dots presents a pitch which is very close to
that of the TV screen. If in an are a of t he sc reen, th e whit e dots fall exactly on the tube pi xels, then,
at some further distance, they will fall exactly between the pixels. The result will be a succession of
bright and dark stripes with an approximately v e rtical direction. The nearer t he dot pi tch to t he tube
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pitch, the wider the stripes (however, if the dot arra y is not uniform, the basi cally vertical stripes will
be strongly distorted).
Please notice that if the succession of dots is shifted horizontal ly b y half a pix el, the dark and bright
stripes will be exchanged. This pro vides a way to compensat e the H Moire: by artificially introducing
an horizontal jitter with an amplitude of half a pixel, any point on the screen will be successively on
a dark then bright stripe. As a result the eye will see medium brightness everywhere.
Since Moire can also appear with other less simple combinations of dots and pixels, the setting of
the Moire cancellation must be left to the end user for optimum results.
A self-contained H-Moire cancellation system is available on the TDA9112: an internal logic circuit
provides a series of pulses related to H freque ncy with an adjustable amplitude through I²C
(Register 02). After a co nvenient attenuation, this pulsed v oltage wil l modul ate the voltage on PLL2
capacitor , introducing the r equired artificial H jitter . The phase of this jitter is re vers ed for e v ery other
frame, in orde r to make it less noticeable.
This Moire cancellation sy stem can b e used f or any t ype of monitor ( be it common or se parat e EHV
and H scanning). Two modes can be selected through I²C programming (Sad02h/d7). In the event
of a “common” structure, better results will be obtained when set to 0, while 1 is mandatory with a
“separate” structure. If Moire is not needed, the level must be set to 0 through I²C programming.
On the low-cost TD A9115 version, the Moire compensation is av ailable on pin 11 rather than being
applied internally. First, the pulse amplitude of pin 11 must be divided in a ratio of 1000 to 2000 with
a resistor bridge referenced to HGND. Then connect the low-side end of PLL2 capacitor (formerly
grounded) to the medium point of res istor bridge. This wa y, the compensation pulses will be applied
to pin 5 through the capacitor.
The TDA9116 provides either internal or external compensation which is selected by I²C
programming (Sad16h/d3:2). When internal compensation i s selected, pin 11 becomes a 7-bit D A C
with a span between 0 and 5 V.
4.2 Application Hints
4.2.1 Minimizing Jitter
The TDA9112 provides low intrinsic horizontal jitter, but some care must be taken not to spoil its
naturally good performances. Since all horizontal timings are based on the comparison of the
oscillator sawtooth with various DC levels, all these voltages should be kept perfectly clean. Let us
make a “rule-of-thumb” calculation: if the oscillator sawtooth amplitude: 4.8V, corresponds to 7/8 of
the period, then a 1mV parasitic voltage on either the sawtooth or one of the DC levels will induce:
31778 x (7/8)/4800 = 5.8 ns of jitter in VGA, which is an unacceptable value.
Here are some basic precautions to obtain the best ji tter value:
● First, care should be taken not to corrupt the incoming sync pulse. Typically, it will have some
20ns transition time and an 5V amplitude. In these conditions, adding a 0.25 V amplitude
parasitic voltage (ground ripple for instance) will cause 1ns of jit ter on the incoming sync.
Similar considerations apply to Hfly pulse, which is not very fast.
More precisely, we can consider that the components of the PLL1 fil ter hav e been optimiz ed f or
jitter. If jitter is found to decrease when using other values than the ones indicated for theses
components, usually the reason is that the input HSync is already jittered; suppressing this
jitter on the HSync input will lead to a jitter performance unattainable before.
● A separate ground connection, tied to pin 7, should be devoted to all horizontal-related
components, i.e. those connected to pins 4, 5, 6, 8, 9, 10, 12 and 13. This connection must be
tied to pins 21 and 27, but it should not carry any other current, especially those not
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