–2
– Programmable center frequency
– 15 dB with 1 dB steps
– Selectable high frequency boost
– Selectable flat-mode
■ Volume
– +15 dB to -15 dB with 1 dB step resolution
– Soft-step control with programmable blend
times
■ Bass
–2
– Center frequency programmable in 4 steps
– Q programmable 1.0/1.25/1.5/2.0
– DC gain programmable
– -15 to 15 dB range with 1 dB resolution
■ Middle
–2
– Center frequency programmable in 4 steps
– Q programmable 0.5/0.75/1.0/1.25
– -15 to 15dB range with 1dB resolution
■ Treble
–2
– Center frequency programmable in 4 steps
– -15 to 15dB range with 1dB resolution
■ Speaker
– 4 independent soft step speaker controls
– 0dB to -79dB with 1dB steps
–Direct mute
■ Subwoofer
–2
cut off frequency
– 2 independent soft step level control,
■ Mute functions
nd
order frequency response
nd
order frequency response
nd
order frequency response
nd
order frequency response
nd
order low pass filter with programmable
TDA7719
3 band car audio processor
TSSOP28
– Direct mute
– Digitally controlled SoftMute with 4
programmable mute-times
■ Offset detection
– Offset voltage detection circuit for on-board
power amplifier failure diagnosis
■ Level meter
– Provide rectified level voltage of main
source signal (before loudness)
■ Rear seat selector
– Full source selector for rear seat output
■ Mixing selector
Description
The TDA7719 is a high performance signal
processor specifically designed for car radio
applications. The device includes a high
performance audioprocessor with fully integrated
audio filters and new Soft Step architecture. The
digital control allows programming in a wide range
of filter characteristics. By the use of BCMOSprocess and liner signal processing low distortion
and low noise are obtained.
= -40 to 85 °C; RL= 10 kΩ; all gains = 0 dB; f = 1 kHz; unless otherwise
amb
V
s
I
s
Input selector
R
in
V
CL
S
IN
Differential stereo inputs
R
in
CMRR1
CMRR2
e
No
Supply voltage7.58.510V
Supply current35mA
Input resistanceAll single ended inputs
Clipping levelInput gain = 0 dB2V
(1)
70100130kΩ
RMS
Input separation100dB
Input resistanceDifferential70100130kΩ
=1 VRMS@ 1 kHz4660dB
Common mode rejection ratio
for main source
Common mode rejection ratio
nd
source
for 2
Output noise @ speaker
outputs
V
CM
1 VRMS@ 10 kHz4660dB
V
CM=
V
=1 VRMS@ 1 kHz4660dB
CM
20 Hz-20 kHz, A-weighted;
all stages 0dB
12µV
Doc ID 13698 Rev 49/46
Electrical specificationsTDA7719
Table 5.Electrical characteristics (continued)
SymbolParameterTest conditionMin.Typ.Max.Unit
Loudness control
A
MAX
A
STEP
f
Peak
Volu m e con t ro l
Max attenuation15dB
Step resolution1dB
Peak frequency
f
P1
f
P2
f
P3
400Hz
800Hz
2400Hz
G
A
A
V
MAX
MAX
STEP
E
A
E
T
DC
Max gain15dB
Max attenuation-15dB
Step resolution0.511.5dB
Attenuation set error-0.750+0.75dB
Tracking error2dB
DC steps
Soft mute
A
MUTE
T
V
TH Low
V
TH High
R
V
D
PU
PU
Mute attenuation80 100dB
Delay time
Low threshold for SM pin1V
High threshold for SM pin2.5V
Internal pull-up resistor324558kΩ
Internal pull-up Voltage3.3V
Bass control
FcCenter frequency
Q
BASS
C
RANGE
A
STEP
DC
GAIN
Quality factor
Control range±14±15±16dB
Step resolution0.511.5dB
Bass-DC-gain
Adjacent attenuation steps0.13mV
From 0 dB to G
MIN
0.55mV
T10.48ms
T20.96ms
T38ms
T416ms
f
C1
f
C2
f
C3
f
C4
Q
1
Q
2
Q
3
Q
4
546066Hz
728088Hz
90100110Hz
180200220Hz
0.911.1
1.11.251.4
1.31.51.7
1.822.2
DC = off-10+1dB
DC = on, Gain =
±15 dB±4.4dB
10/46 Doc ID 13698 Rev 4
TDA7719Electrical specifications
Table 5.Electrical characteristics (continued)
SymbolParameterTest conditionMin.Typ.Max.Unit
Middle control
C
RANGE
A
STEP
f
c
Q
BASS
Treble control
Control range±14±15±16dB
Step resolution0.511.5dB
Center frequency
Quality factor
f
C1
f
C2
f
C3
f
C4
Q
1
Q
2
Q
3
Q
4
400500600Hz
0.811.2kHz
1.21.51.8kHz
22.53 kHz
0.450.50.55
0.650.750.85
0.911.1
1.11.251.4
C
RANGE
A
STEP
f
c
Clipping level±14±15±16dB
Step resolution0.511.5dB
Center frequency
Speaker attenuators
A
A
A
STEP
A
MUTE
V
MIN
MAX
E
DC
E
Min attenuation-101dB
Max attenuation-89-79-69dB
Step resolution0.511.5dB
Mute attenuation8090dB
Attenuation set error2dB
DC stepsAdjacent attenuation steps0.15mV
Audio outputs
Clipping level
Output impedance30100
Output load resistance2kΩ
Output load capacitor10nF
DC voltage level3.84.04.2V
R
V
V
CL
OUT
R
L
C
L
DC
Subwoofer attenuator
f
C1
f
C2
f
C3
f
C4
81012kHz
1012.515kHz
121518kHz
1417.521kHz
d = 0.3%; Byte8_D6=12V
d = 1%; Byte8_D6=02.2V
RMS
RMS
Ω
G
MAX
A
A
STEP
A
MUTE
MAX
E
E
Max gain141516 dB
Max attenuation-83-79-75dB
Step resolution0.511.5dB
Mute attenuation8090dB
Attenuation set error2dB
Doc ID 13698 Rev 411/46
Electrical specificationsTDA7719
Table 5.Electrical characteristics (continued)
SymbolParameterTest conditionMin.Typ.Max.Unit
V
DC
Subwoofer lowpass
f
LP
DC offset detection circuit
V
th
t
sp
I
CHDCErr
I
DISDCErr
V
OutH
V
OutH
Level meter
DC stepsAdjacent attenuation steps0.15mV
Lowpass corner frequency
f
f
f
LP1
LP2
LP3
728088Hz
108120132Hz
144160176Hz
V1±25mV
Zero comp window size
V2±50mV
V3±75mV
V4±100mV
11µs
Max rejected spike length
22µs
33µs
44µs
DCErr charge current5µA
DCErr discharge current5mA
DCErr high volotage3.3V
DCErr low voltage100mV
VoutOutput voltage range03.3V
= 1 Vrms1.6V
V
V
LEVEL
T
DEL
Output level
Analog output delay time2µs
in
= AC grounded0V
V
in
General
BW = 20 Hz to 20 kHz
e
NO
Output noise
A-Weighted, all gain = 0 dB
BW = 20 Hz - 20 kHz
A-Weighted, output muted
S/NSignal to noise ratio
DDistortionV
S
C
1. When DC offset detector is not used, the impedance of mono single-ended input is 50 kΩ instead of 100 kΩ.
Channel separation left/right90dB
all gain = 0 dB, A-weighted;
= 2 V
V
o
RMS
IN
=1 V
all stages 0dB0.01%
RMS;
12µV
6µV
104dB
12/46 Doc ID 13698 Rev 4
TDA7719Description
4 Description
4.1 Input configuration
4.1.1 Front and rear selector
The input stage (Main source and 2nd source) is configurable to adapt to different
application. There are 7 different configurations which provide different input structure and
different number of input sources as shown below.
●4 x QD,
●2 x QD + 3 x SE,
●1 x QD + 5 x SE,
●1 x QD + 3 x SE + 2 x MD,
●3 x QD + 1 x FD,
●3 x QD + 2 x SE,
●1 x QD + 2 x SE + 1 x FD + 1 x MD,
●1 x QD + 3 x SE + 1 x FD
Note:QD = Quasi-Differential, SE = Single-ended input, FD = Full Differential, MD = mono
Differential
The configuration of the input stage is controlled by ‘Input Configuration’ bits in I
table (Byte0 Bit5~Bit7). The table below shows the configuration of input pins in different
configurations.
Table 6.Input pin configuration
PinPin name
QD1L_SE1L
1
_MD3+
QD1R_SE1R
2
_MD3-
QD1G_SE2LQD1GSE2L
3
QD2G_SE2RQD2G
4
QD2L_SE3LQD2LSE3L
5
QD2R_SE3RQD2RSE3RSE3RSE3RQD2RQD2RSE3RSE3R
6
QD3LQD3L
7
QD3GQD3GQD3GQD3GQD3GQD3GQD3GQD3GQD3G
8
QD3RQD3RQD3RQD3RQD3RQD3RQD3RQD3RQD3R
9
QD4L_FD4+
10
_SE4L_MD1+
QD4G_FD4L
11
_SE4R_MD1-
QD4G_FD4R_S
12
E5L_MD2-
QD4R_FD4R+_
13
SE5R_MD2+
Configuration bits (Byte0 Bit7~Bit5)
"000""001""010""011""100""101""110""111"
CFG0CFG1CFG2CFG3CFG4CFG5CFG6CFG7
QD1L
QD1RSE1RSE1RSE1RQD1RQD1RMD3-SE1R
QD4L
QD4GQD4GSE4RMD1-FD4L-SE4RFD4L-FD4L-
QD4GQD4GSE5L
QD4RQD4RSE5RMD2+
SE1L
IN0
SE2RSE2RSE2RQD2G
IN1
QD3L
IN2
QD4L
IN3
IN0
IN4
IN1
IN2
IN3
SE1L
SE2L
SE3L
QD3L
SE4L
IN0
IN4
IN1
IN2
IN5
IN6
SE1L
SE2L
SE3L
QD3L
MD1+
MD2-
QD1L
IN0
QD1GQD1GSE2L
IN4
QD2LQD2LSE3L
IN1
QD3L
IN2
FD4L+
IN3
FD4R-SE5L
IN3
FD4R
+
QD1L
IN0
QD2G
IN1
QD3L
IN2
SE4L
IN3
SE5RFD4R+FD4R+
MD3+
IN0
SE2RSE2R
IN1
QD3L
IN2
FD4L+
IN5
FD4R-FD4R-
IN6
IN7
IN4
IN1
IN2
IN3
2
C control
SE1L
SE2L
SE3L
QD3L
FD4L+
IN0
IN4
IN1
IN2
IN3
Doc ID 13698 Rev 413/46
DescriptionTDA7719
With different input configuration, the input source can be selected with input selector
(Byte0/1 Bit0~Bit2). The following matrix defines the selector configuration of different input
sources dependant on the configuration bits.
Table 7.Selector configuration matrix
Selector Bits
000001010011100101110111
(Byte0/1
Bit2~Bit0)
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
IN0IN1IN2IN3IN4IN5IN6IN7
QD1QD2QD3QD4NANANANA
SE1SE3QD3QD4SE2NANANA
SE1SE3QD3NASE2SE4SE5NA
SE1SE3QD3MD1/2SE2NANANA
QD1QD2QD3FDNANANANA
QD1QD2QD3NANASE4SE5NA
NASE3QD3FDSE2NANAMD3
SE1SE3QD3FDSE2NANANA
Note:In each configuration, only the light grey cells are allowed. The dark grey cells are not
allowed.
MD1/MD2 selection is defined by extra bit – ‘MD1/2 selection’ in I
2
C control table (Bit3 of
Byte0/1).
The input stage can be configured to 0dB or 3dB gain with I
2
C bus. The 0dB configuration
allows up to 2Vrms input signal level, while with 3dB gain, the internal signal will start to clip
when input signal level is higher than 1.414Vrms.
The Pin10~Pin13 can be configured as full differential input stage or quasi-differential input.
When it is configured as quasi-differential input, both Pin11 and Pin12 are used as the QD
common input pins. These two pins must be connected together externally in application. In
this case the input impedance of QD4 common is reduced to 50k
Ω (half of QD4 left and
right input). The diagram below shows both QD and FD configuration of QD4/FD4.
14/46 Doc ID 13698 Rev 4
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