ST TDA7572 User Manual

TDA7572

200W mono bridge PWM amplifier with built-in step-up converter

Preliminary Data

Features

■ Input stage and gain compressor

■ Over-modulation protection and current limiting

■ Modulator

■ DAC

■ Step-up

■ Mode control

■ Diagnostics / safety

■ Power control

Description

TDA7572 is a highly integrated, highly versatile, semi-custom IC switch mode audio amplifier. It integrates audio signal processing and power amplification tailored for standalone remote bass box applications, while providing versatility for full bandwidth operation in either automotive or consumer audio environments. It's configured as one full bridge channel, using two clocked PWM modulators driving external, complementary FET's.

Broad operating voltage is supported, allowing operation from both 14V and 42V automotive power buses, as well as from split supplies for consumer electronics use.

A current mode control boost converter controller is provided to allow high power operation in a 14V environment. Turn-on and turn-off transients are minimized by soft muting/unmuting and careful control of offsets within the IC.

Digital Audio input is supported by an integrated one channel DAC. Sophisticated diagnostics and protection provide fault reporting via I power shutdown for safety related faults.

TDA7572 is packaged in a HiQUAD-64 package.

HiQUAD-64

C and

Table 1. Device summary

Order code Package Packing

TDA7572 HiQUAD-64 Tray

September 2007 Rev 1 1/64

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents TDA7572

Contents

1 Detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3.1 Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3.2 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.3 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.4 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.6 Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.7 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4 Voltage booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.1 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4.2 I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4.3 Op. amp. cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4.4 Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4.5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

C and mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1 Input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 Faults 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3 Faults 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5 Modulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.6 Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 Input stage and gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2/64

TDA7572 Contents

6.2 Gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2.1 Setting in I2C bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2.2 Soft-mute function, without pre-limiter . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1 FET drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2 ANTI-POP shunt driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9 Step-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1 Faults during operation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.1 DC offset across the speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.2 Die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.3 External temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.4 Output clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.5 Output over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.6 Power supply overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1.7 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1.8 Faults during power-up: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12 Under voltage lock out (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.1 VSP-UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2 V14 - UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.3 SVR - UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

13 Start-up procedures, modulator turn-on after a tristate condition. . . 56

13.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

13.2 Tristate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

14.1 Single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

14.2 Split supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3/64

Contents TDA7572

14.3 THD+N step-up on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4/64

TDA7572 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin list by argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Pin list by pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Voltage booster. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Op. amp. cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 17. Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. Analog operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. Power-up mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. I

Table 22. Input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Faults 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. Faults 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25. Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 26. Modulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27. Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 28. Distortion versus gain step size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 29. Sets the maximum release rate of the gain compressor. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 30. Sets the maximum attack rate of the gain compressor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 31. Attack/release rate and gain compression effort selection . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 32. PWMClock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 33. Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 34. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

C chip address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5/64

List of figures TDA7572

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. Mute by external command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 4. Mute by I

Figure 5. Modulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 6. Current sourced by the shunt pin in NO I

Figure 7. DAC circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 8. Two interpolator structure diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 9. I

Figure 10. Step-up application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 11. Threshold of current limiting diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Single supply evaluation board schematic.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 13. Single supply evaluation PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 14. Split supply evaluation board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 15. Split supply evaluation PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 16. THD+N step-up on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 17. HiQUAD-64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

S format diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

C bus command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Cbus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6/64

TDA7572 Detailed features

1 Detailed features

● Input Stage and Gain Compressor

– Differential, high CMRR, analog input – Programmable input attenuation/gain to support up to four drive levels – Noiseless Gain compression of up to 16 dB with programmable attack and decay. – Compressor controlled by monitoring estimated THD – Soft mute / un-mute for pop control

● Over-modulation Protection and Current Limiting

– Adaptive pulse injection prevents missing pulses due to over modulation which

maximizes useful output swing.

– Programmable current limiting based on FET VDS

● Modulator

– Optimized for low distortion at low switching frequency (approximation 110KHz) – Dual Clocked PWM modulators for 3 state switching – External gain control / internal integrator components – Controls 4 external FETS with switching optimized for low EMI – Oscillation frequency selectable by I – Anti-pop shunt driver

● DAC

– 18bit, mono

–I

S inputs 38-48KHz, 96KHz, 192 KHz – Hybrid architecture, area optimized for Bass – Full bandwidth supported by off loading the interpolator function – Synchronization with modulator

● Step-Up

– On board STEP-UP step up converter, synchronized to the modulator frequency – Drives external NFET switch – Externally compensated – Soft start and current limiting

● Mode Control

– Critical modes controllable by mode pins for bus-less operation

–I

C provides additional mode control

● Diagnostics / Safety

– Offset, short, open, overcurrent, over temperature

–I

C used to report errors, and for configuration control – Faults pin used to report errors in bus-less environment – Clipping reported at a separate pin – Abnormal supply current detection disables input power for fail safe operation – Output current limiting – Power control – Latching control of an external PMOS power switch for safety related faults. – Power is switched off for safety related faults of abnormal supply current,

excessive internal or external temperature, or persistent output stage over-current that fails to be controlled by the pulse-by-pulse current limiting method

7/64

Interface description TDA7572

2 Interface description

I2C bus and mode control pins are use to control operation. Default values of all the operating modes are deterministic, some of these values are intrinsic to the IC and some are determined by configurations pins. The configuration pins are read at power-up and copied into registers, which may later be modified using the I allows varied operation in an environment where NOI

control and override of pin programmed modes when used with I

Figure 1. Block diagram

CSense

V14

BSTVSource

BSTGate

BSTVSense

VP2.5

V14Sense

VM2.5

WS / CLIP_L

VDIG

DGND

C bus, if one is present. This

C bus is present, while allowing full

SDA / SCR_ENB

SCL / InputLevel1

DACM

PLL / InLeve l0

DACP

MOD1

ISSENP

ISSENM

Mode 0

Automute Voltage Setting

Addr 0 / Fault / CLIP_L

Addr1 / CompEnable

Mode 1

Vs/2 or SVR

C data / attack sel.

C clock

ShuntDrive

Mute

NTC

TestC

Iset

DC/DC Converter

+Vs current

protection

Mode sel.

and

Mute

I2Cbus

Thermal management

Diagnostics

clipdet

Controls and Diagnostics

Oscillators

CLKin -out

Regulators

LOGIC

UVLO

Diff -to-S.E. Compressor

and

Limiter

Channel 1

INP

INM

OscOut

DITH -sel

AOUT

DAC

-1

InvIn

PWM Channel 1

Pulse Inj.

Integrator

Drivers

Prot. & supply

PWM Channel 2

Pulse Inj.

Integrator

Drivers

Protections

VSM1,2,3,4

InvOut

LSD1SourceSensing LSD1GateDrive

LSD1GateSensing

HB1OutFilter

HB1Out

ILimit threshold

HSD1GateSensing

HSD1GateDrive

HSD1SourceSensing

VSP_Pow1

HSD2SourceSensing

HSD2GateDrive

HSD2GateSensing

VSP_Pow2

HB2Out

LSD2OutFilter

LSD2GateSensing

LSD2GateDrive

LSD2SourceSensing

MOD2

AC00014

8/64

TDA7572 Pins description

3 Pins description

Figure 2. Pins connection (top view)

Iset

TestC

LSD2SS

LSD2GD

LSD2GS

HB2OutFilt

HB2Out

HSD2GS

HSD2GD

HSD2SS

VSP_POW2

VSP_POW1

HSD1SS

HSD1GD

HSD1GS

HB1Out

HB1OutFilt

LSD1GS

LSD1GD

LSD1SS

I2CLK

IlimitThresh

21 22 23 24 25

VSM4

ADDR1/CompEnable

ADDR0/Fault/Clip_L

I2CDATA/AttackSel

MUTE_L

AutoMuteVSetting

Mode0

VSM3

57 56 55 54 53

271128 29 30 31 32

Mode1

VP2.5

SVR

VM2.5

VDIG

DGND

NTC

SCL/InLevel1

WS/Clip_L

SDA/SCR_ENB

PLL/InLevel10

ShuntDriver

DITH

CLKIN/Out

OscOut

MOD2

MOD1

InvOut

InvIn

AOUT

INP

INM

BSTGate

BSTSource

CSense

V14Sense

V14

VSM2

AC00013

DAC2

VSM1

BSTVSense

ISSENM

ISSENP

DAC1

9/64

Pins description TDA7572

Table 2. Pin list by argument

Pin # Pin name Description

On/Off Circuitry

11 VSP_POW2

Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two

53 VP2.5 +2.5V analog supply output

51 VM2.5 -2.5 V analog supply output

50 VDIG 5V logic supply decoupling

49 DGND Digital gnd

52 SVR Vs/2 analog reference filter capacitor. Reference for input stage.

55 Mode0 Mode control bit0, selects standby/normal/ I2C/diagnostic operation

54 Mode1 Mode control bit1, selects standby/normal/ I

C/diagnostic operation

57 MUTE_L Mute input and / or timing cap, assertion level low

56 AutoMuteVSetting Auto-mute Voltage Setting

Input/ Gain Compressor

34 INP Non inverting audio input

33 INM Inverting audio input

35 AOUT Compressed Audio Output

Input Stage gain selection – see PLL pin in DAC Section 8

Compressor attack/decay select – see I2C data pin in DAC Section 8

Inverter

36 InvIn Inverter input

37 InvOut Inverter Output

Modulator

64 IlimitThresh Output stage Current Limiting trip voltage set point

32 LVLSFT Gain program pin for SVR to HVCC level shifting

38 MOD1 Modulator1 Inverting / Summing node

20 LSD1SS Lowside1 Source Sensing

19 LSD1GD Lowside1 Gate Drive

18 LSD1GS Lowside1 Gate sense

17 HB1OutFilt Half bridge1 post-LC filter – for diagnostics

16 HB1Out Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense

15 HSD1GS Highside1 Gate sense

14 HSD1GD Highside1 Gate Drive

13 HSD1SS Highside1 Source sense

12 VSP_POW1 Positive supply voltage connection for gate drive circuitry

10/64

TDA7572 Pins description

Table 2. Pin list by argument (continued)

Pin # Pin name Description

39 MOD2 Modulator2 Inverting / Summing node

10 HSD2SS Highside2 Source sense

9 HSD2GD Highside2 Gate Drive

8 HSD2GS Highside2 Gate sense

7 HB2Out Half-bridge2 output, HSD 1 drain sense, LSD1 Drain Sense

6 HB2OutFilt Half bridge2 post-LC filter – for diagnostics

5 LSD2GS Lowside2 Gate sense

4 LSD2GD Lowside2 Gate Drive

3 LSD2SS Lowside2 Source Sense

27 VSM1

26 VSM2

58 VSM3

Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies

59 VSM4

Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies

43 ShuntDriver Shunt Driver

DC-DC

28 BSTVSense Voltage feedback input for Voltage Booster

22 BSTSource Boost Converter NFET Source

21 BSTGate Boost Converter NFET gate drive

23 CSense

Inverting input for Booster Current Sensing and Digital Test Enable (operating when is more then about 3V under the V14 pin level)

24 V14Sense Non-inverting input for Booster Current Sensing

25 V14 Power for Boost converter gate drive and Output LSD’s

Oscillator

41 CLKIN/Out Clock input

42 DITH Dither capacitor

40 OscOut Oscillator output

Diagnostics / Bus

CDATA/AttackSel

63 I

CLK I2C Clock

I2C data (I2C mode) Compressor aggressiveness selection (non-bus mode)

11/64

Pins description TDA7572

Table 2. Pin list by argument (continued)

Pin # Pin name Description

C address set (I2C mode)

61 ADDR0/Fault/Clip_L

60 ADDR1/CompEnable

48 NTC Connection for NTC thermistor

2 TestC Test cap used to generate the slow current pulses

1 ISet Program pin for current level used in Short/Open test

30 ISSENP Supply non-inverting current sense

29 ISSENM Supply inverting current sense

DAC

46 WS / Clip_L I

45 SDA/SCR_ENB I

47 SCL/ InLevel1 I

44 PLL/InLevel0 DAC clock PLL filter/ Input Level selection bit 0 (non-DAC mode)

31 DAC2 DAC output voltage p

Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled)

C address set (I2C mode)

I Compressor Enable/disable (non-bus mode)

S Word select / Clipping indicator, assertion level low (non-DAC mode)

C serial data / SCR ENABLE (non DAC mode)

C serial data bit clock/ Input Level selection bit1 (non-DAC mode)

32 DAC1 DAC output voltage n

Table 3. Pin list by pin

Pin # Pin name Description

1 Iset Program pin for current level used in Short/Open test

2 TestC Test cap used to generate the slow current pulses

3 LSD2SS Lowside2 Source Sense

4 LSD2GD Lowside2 Gate Drive

5 LSD2GS Lowside2 Gate sense

6 HB2OutFilt Half bridge2 post-LC filter – for diagnostics

7 HB2Out Half-bridge2 output, HSD 1 drain sense, LSD1 Drain Sense

8 HSD2GS Highside2 Gate sense

9 HSD2GD Highside2 Gate Drive

10 HSD2SS Highside2 Source sense

11 VSP_POW2

Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two

12 VSP_POW1 Positive supply voltage connection for gate drive circuitry

13 HSD1SS Highside1 Source sense

14 HSD1GD Highside1 Gate Drive

15 HSD1GS Highside1 Gate sense

12/64

TDA7572 Pins description

Table 3. Pin list by pin (continued)

Pin # Pin name Description

16 HB1Out Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense

17 HB1OutFilt Half bridge1 post-LC filter – for diagnostics

18 LSD1GS Lowside1 Gate sense

19 LSD1GD Lowside1 Gate Drive

20 LSD1SS Lowside1 Source Sensing

21 BSTGate Boost Converter NFET gate drive

22 BSTSource Boost Converter NFET Source

23 CSense

Inverting input for Booster Current Sensing and Digital Test Enable (operating when is more then about 3V under the V14 pin level)

24 V14Sense Non-inverting input for Booster Current Sensing

25 V14 Power for Boost converter gate drive and Output LSD’s

26 VSM2

27 VSM1

Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies

28 BSTVSense Voltage feedback input for Voltage Booster

29 ISSENM Supply inverting current sense

30 ISSENP Supply non-inverting current sense

31 DAC2 Half VCC (VSP- VSM)/2 Used for output stage reference.

32 DAC1 Gain program pin for SVR to HVCC level shifting

33 INM Inverting audio input

34 INP Non inverting audio input

35 AOUT Compressed Audio Output

36 InvIn Inverter input

37 InvOut Inverter Output

38 MOD1 Modulator1 Inverting / Summing node

39 MOD2 Modulator2 Inverting / Summing node

40 OscOut Oscillator output

41 CLKIN/Out Clock input

42 DITH Dither capacitor

43 ShuntDriver Shunt Driver

44 PLL/InLevel0 DAC clock PLL filter/ Input Level selection bit 0 (non-DAC mode)

45 SDA/SCR_ENB I

46 WS / Clip_L I

47 SCL/ InLevel1 I

C serial data / SCR ENABLE (non DAC mode)

S Word select / Clipping indicator, assertion level low (non-DAC mode)

C serial data bit clock/ Input Level selection bit1 (non-DAC mode)

48 NTC Connection for NTC thermistor

13/64

Pins description TDA7572

Table 3. Pin list by pin (continued)

Pin # Pin name Description

49 DGND GND logic supply decoupling

50 VDIG 5V logic supply decoupling

51 VM2.5 -2.5 V analog supply output

52 SVR Vs/2 analog reference filter capacitor. Reference for input stage.

53 VP2.5 +2.5 V analog supply output

54 Mode1 Mode control bit1, selects standby/normal/I

55 Mode0 Mode control bit0, selects standby/normal/ I

56 AutoMuteVSetting Auto-mute Voltage Setting

57 MUTE_L Mute input and / or timing cap, assertion level low

58 VSM3

59 VSM4

60 ADDR1/CompEnable

61 ADDR0/Fault/Clip_L

Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies

C address set (I2C mode)

I Compressor Enable/disable (non-bus mode)

C address set (I2C mode) Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled)

C/diagnostic operation

62 I2CDATA/AttackSel

63 I

CLK I2C Clock

I2C data (I2C mode) Compressor aggressiveness selection (non-bus mode)

64 IlimitThresh Output stage Current Limiting trip voltage setpoint

14/64

TDA7572 Electrical specifications

4 Electrical specifications

4.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameters Test Conditions Min. Max. Units

DMAX

peak

DATA

Stg

Supply voltage VSM -0.6 VSM +58 V

Peak supply voltage (VS+ - VS-) time ≤ 50ms 68 V

Data pin voltage w.r.t Dgnd VS—0.6 6V V

Junction temperature -40 150 C

Storage temperature -55 150 C

Power Dissipation

Any operating condition For thermal budgeting

2.5 W

4.2 Thermal data

Table 5. Thermal data

Symbol Parameters Value Units

Th j-case

Thermal resistance junction to case 3 °C/W

4.3 Electrical characteristics

Unless otherwise specified, all ratings below are for -40°C < TJ < 125°C, VSP = 42V, VSM = 0V and the application circuit of Figure 12. Operation of the IC above this junction temperature will continue without audible artifacts until thermal shutdown, but these parameters are not guaranteed to be within the specifications below. F

PWM

=110KHz,

Booster not enabled.

4.3.1 Operating voltage and current

Table 6. Operating voltage and current

Symbol Parameters Test conditions Min. Typ. Max. Units

SP42

SP14

Operating voltage 42V automotive range

Operating voltage 14.4V automotive range

Normal operation without audible defects required

Single ended supply 42V configuration, V

Normal operation without audible defects required

Single ended supply 14V configuration, V

15/64

30 42 58

9 14.4

Electrical specifications TDA7572

Table 6. Operating voltage and current (continued)

Symbol Parameters Test conditions Min. Typ. Max. Units

Normal operation required

SPLIT

stdby

Operating voltage VSP -

split supply rails

Stand-by current

Split supply application

SVR

VSM<V

SVR-4,

configuration,

VSP>V

IC in standby, Mode0, and Mode1

= 42V

low V

848 58 V

50 at = 25°C

10 at

μA

T = 85°C

V14 13 20

VSP 15 25

tristate

Tristate current

Outputs tristated Booster not running,

= nominal

pwm

V14 10

MUTE

Mute mode current MUTE asserted,

VSP 20

4.3.2 Under voltage lockout

Table 7. Under voltage lockout

Symbol Parameters Test conditions Min. Typ. Max. Units

LimAM

VSP UVLO

VPO-

VPO+

AutomuteVSetting pin

voltage limit

Auto-mute supply voltage VSP

Auto-tristate supply voltage VSP negative

slope

Auto-tristate supply voltage VSP positive

slope

Auto-tristate supply

voltage VSP Relative maximum value

Voltage limit respect to the SVR pin Allowed voltage range on Automute

Mute is forced if VSP-VSVR or VSVR-VSM is less than this value

VautomuteVSetting-V

SVR

=VVSVR

The IC is set in tristate if VSP-VSM is less than this value

Vautomute VSetting-V

=VVSVR

SVR

The IC is set out from tristate if VSP-VSM is higher than this value

Vautomute VSetting-V

=VVSVR

SVR

The IC is set in tristate if VSP-VSM is more than this value

Vautomute VSetting-V

=VVSVR

SVR

0.5 2.1 V

-15%

VVSVR*

VVSVR

*12

VVSVR

*13

VVSVR*

+15% V

Auto-tristate supply voltage

VSP Absolute maximum

The IC is set in tristate if VSP-VSM is higher than this value

60 63 66 V

value

16/64

TDA7572 Electrical specifications

Table 7. Under voltage lockout (continued)

Symbol Parameters Test conditions Min. Typ. Max. Units

V14 – UVLO

Auto-tristate supply

V14-

voltage V14 negative

slope

Auto-tristate supply

V14+

voltage V14 positive

slope

V14h

Auto-tristate 14V voltage hysteresis

V14su Step-up tristate

Auto-mute supply

V14mute-

voltage V14 negative

slope

Auto-mute supply

V14mute+

voltage V14 positive

slope

SVR – UVLO

Vsvr-

Vsvr+

Auto-tristate SVR voltage negative slope

Auto-tristate SVR voltage positive slope

Auto-tristate SVR

VPOH

Voltage hysteresis

The IC is kept in tristate if 14V VSM become lower than this value

The IC is goes out from tristate if 14V-VSM become higher than this value

Comparator hysteresis for autotristate threshold

The step-up is in tristate when voltage lower than this threshold

The IC goes in mute if 14V-VSM become lower than this value

The IC goes in play if 14V-VSM become higher than this value

The IC is kept in tristate if VSvr VSM become less than this value

Vautomute VSetting-V

=VVSVR

SVR

The IC is goes out from tristate if Vvr - VSM become higher than this value

Vautomute VSetting-V

=VVSVR

SVR

Comparator hysteresis for autotristate threshold

Vautomute VSetting-V

=VVSVR

SVR

5.5 7 V

6.5 8 V

0.8

58V

V14-

0.7V

V14V+

40mV

V14-

1.2V

V14V+

170mV

-15%

+15% V

VVSVR

-15%

+15% V

VVSVR

0.40 X

VVSVR

1.2V

VVSVR

17/64

Electrical specifications TDA7572

4.3.3 Input stage

Table 8. Input stage

Symbol Parameters Test conditions Min. Typ. Max. Units

Input diff. amp./ gain attenuator

IN,

compress

INLEVEL1=0, INLEVEL0=0 -30% 20 +30%

INLEVEL1=0, INLEVEL0=1 -30% 12 +30%

INLEVEL1=1, INLEVEL0=0 -30% 22 +30%

ion

INLEVEL1=1, INLEVEL0=1 -30% 12 +30%

Input resistance

INLEVEL1=0, INLEVEL0=0 -30% 15.6 +30%

max

INLEVEL1=0, INLEVEL0=1 -30% 12 +30%

compress

ion

INLEVEL1=1, INLEVEL0=0 -30% 16 +30%

INLEVEL1=1, INLEVEL0=1 -30% 12 +30%

INLEVEL1=0, INLEVEL0=0 2 V

INLEVEL1=0, INLEVEL0=1 7 V

INLEVEL1=1, INLEVEL0=0 2.6 V

INLEVEL1=1, INLEVEL0=1 9.5 V

INLEVEL1=1,INLEVEL0=1 Not tested in production

AOUT-VSVR

) / (VInP-VinM)

INLEVEL1=0, INLEVEL0=0,

-10 +10

-4 -3 -2 dB

InMax

IN_0

Input clipping level Voltage level of the input

that trespassed cause clipping in the preamplifier

no compression

KΩ

RMS

IN_2

IN_1

IN_3

outH

outL

AOUT

Input stage gain

AOUT output voltage swing

AOUT output swing

THD

- V

AOUT

) / (VInP-VinM)

SVR

INLEVEL1=0, INLEVEL0=1, no compression

- V

AOUT

) / (VInP-VinM)

SVR

INLEVEL1=1, INLEVEL0=0 no compression

- V

AOUT

) / (VInP-VinM)

SVR

INLEVEL1=1, INLEVEL0=1, no compression

With respect to SVR, 10K loading to a buffered version of SVR

Vin=1Vrms, f=20-20KHz, INLEVEL1=0, INLEVEL0=0, no compression

-15 -14 -13 dB

-6.3 -5.3 -4.3 dB

-17.6 -16.6 -15.6 dB

-2 V

0.01 0.05 %

18/64

TDA7572 Electrical specifications

Table 8. Input stage

Symbol Parameters Test conditions Min. Typ. Max. Units

Vin=1KHz square wave, 2Vpp,

Output slew rate

INLEVEL1=0, INLEVEL0=0, no compression Time to transition from 10% to 90%

8µS

AOUT clip detector

-3dB

CMRR

Frequency response

Common Mode Rejection Ratio

CG Common gain

PSRR

offset

Power Supply Rejection, Vsp supply

Output offset

Eno Noise

Duty cycle of the Clipping signal

TBD % when there is 5% distortion at the output of AOUT, f=1KHz,

=10kOhm

Vin=1Vrms, INLEVEL1=0, INLEVEL0=0

=1V

CMRR= A

@1KHz

RMS

VDIFF/AVCM

INLEVEL1=0, INLEVEL0=0

15 25

20 KHz

47 dB

No compressor

VCM=1V INLEVEL1=0, INLEVEL0=0

RMS

@1KHz

51 dB

No compressor

=1V

INLEVEL1=1, INLEVEL0=0

RMS

@1KHz

51 dB

No compressor

VCM=1V INLEVEL1=0, INLEVEL0=1

RMS

@1KHz

51 dB

No compressor

VCM=1V INLEVEL1=1, INLEVEL0=1

RMS

@1KHz

51 dB

No compressor

freq<10KHz 60 80 dB

with respect to SVR

Offset

Rin=100 ohms, Mute state

-4 0 +4 mV

Noise at output of this stage f = 20-20KHz, R

= 100ohms

input

710µV

A weighting

RMS

Gain compressor

Maximum attenuation

INLEVEL1=0, INLEVEL0=0 -21 -19 -17

INLEVEL1=0, INLEVEL0=1 -30 -28 -26

INLEVEL1=1, INLEVEL0=0 -25 -23 -21

INLEVEL1=1, INLEVEL0=1 -34 -32 -30

19/64

Electrical specifications TDA7572

Table 8. Input stage

Symbol Parameters Test conditions Min. Typ. Max. Units

Mute

0.5+

0.25

0.44+

0.25 dB

0.55+

0.25

0.48+

0.25

Attenuation step size

Gain Change ZC comparator offset

(in the diff. – S.E. block) offset

INLEVEL1=0, INLEVEL0=0 0.5-0.25 0.5

INLEVEL1=0, INLEVEL0=1

INLEVEL1=1, INLEVEL0=0

INLEVEL1=1, INLEVEL0=1

0.44-

0.25

0.55-

0.25

0.48-

0.25

0.44

0.55

0.48

Observed at AOUT pin ZC crossing must be detected

within 50mV of the actual zero

-80 80 mV

crossing,

Gain Change ZC comparator offset

(in the diff. – S.E. block)

Observed at InvOut pin ZC crossing must be detected

-220 +220 mV

offset

Mute attenuation

Mute pin voltage = Dgnd Vin=1Vrms

90 dB

Charge current Mute Pin Voltage(57) = 1.5V -30% 100 +30% µA

Discharge current Mute Pin Voltage(57) = 1.5V -30% 100 +30% µA

Mute threshold

Maximum voltage where we must be in complete mute

1.5 V

Unmute threshold 2.5 V

Mute to unmute transition voltage

Vol

IC in mute mode, FastMute=1 Iout=0

Voh IC in unmute, Iout=0

0.2 0.3 0.42 V

Digital

GND +

0.1

DIGITAL-

0.1

Fast mute Resistance

FASTMUTE=1 Vmutepin=1.5Volts

20/64

420 550 680 Ohm

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