ST TDA7468 User Manual

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TDA7468

TWO BANDS DIGITALLY CONTROLLED

AUDIO PROCESSOR WITH BASS ALC SURROUND

1 FEATURES

 INPUT MULTIPLEXER

– 4 STEREO INPUTS – SELECTABLE INPUT GAIN FOR OPTIMAL

ADAPTATION TO DIFFERENT SOURCES

 ONE STEREO OUTPUT  BASS ALC  TREBLE AND BASS CONTROL IN 2.0dB  STEPS  VOLUME CONTROL IN 1.0dB STEPS  TWO SPEAKER ATTENUATORS:

– TWO INDEPENDENT SPEAKER CONTROL

IN 1.0dB STEPS FOR BALANCE FACILITY

– INDEPENDENT MUTE FUNCTION

 ALL FUNCTION ARE PROGRAMMABLE VIA  SERIAL BUS  EXTERNALLY ADJUSTABLE SURROUND

2 DESCRIPTION

The TDA7468D is a volume tone (bass and treble) balance (Left/Right) processor for quality audio

Figure 2. PIN CONNECTION (Top view)

gure 1. Package

SO28

Table 1. Order Codes

Part Number Package

TDA7468D SO28

TDA7468D13TR Tape & Reel

applications in Hi-Fi systems.

Selectable input gain is provided. Control of all the functions is accomplished by serial bus.

The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers.

Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained

April 2010

MIC

IN1_L

IN2_L

IN3_L IN3_R

IN4_L

MUX_L

IS_L

TREBLE_L

BASSI_L

BASSO_L

OUT_L

DGND

SCL

D99AU1057

GND

CREF

IN1_R

IN2_R

IN4_R23

MUX_R

IS_R

TREBLE_R

BASSI_R

BASSO_R

OUT_R

ALC

SDA

Rev. 4

1/23

TDA7468

Figure 3. BLOCK DIAGRAM

BASSO-R

192021

BASSI-R

TREBLE-R

63dB att.

OUT-R

-24 att. /8dB step

BASS

/2dB step

-14 to +14dB

TREBLE

/2dB step

-14 to +14dB

/1dB step

+ 6dB gain

DGND

SCL

SDA

131215

C BUS DECODER + LATCHES

OUT-L

-24 att.

BASS

-14 to +14dB

TREBLE

-14 to +14dB

63dB att.

/8dB step

/2dB step

/1dB step

+ 6dB gain

SUPPLY V

REF

GND CREFTREBLE-LMUX-L IS-L

BASSO-LBASSI-L

IS-R

MUX-R

IN-R4

50K

inverting

non-inverting

/ 2dB step

buffer gain:

0 to 14dB gain

INPUT

SELECT

IN-R3

50K

MIX

VARIABLE

0dB

6dB

9dB

12dB

IN-R2

50K

IN-R1

BASS_ALC

50K

CONTROL

0dB, 6dB

10dB, 14dB

50K

MIC-MIX

RECTIFIER

HALF_WAVE

ALC

IN-L1

INPUT

50K

inverting

non-inverting

/ 2dB step

buffer gain:

0 to 14dB gain

SELECT

50K

IN-L2

VARIABLE

0dB

MIX

6dB

IN-L3

9dB

12dB

50K

78 9 10 11 2827

50K

D99AU1058A

IN-L4

2/23

TDA7468

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

amb

stg

Operating Supply Voltage 10.5 V

Operating Ambient Temperature 0 to 70 °C

Storage Temperature Range -55 to 150 °C

Table 3. THERMAL DATA

Symbol Parameter Value Unit

th j-pin

Thermal Resistance Junction-pins 85 °C/W

Table 4. QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit

THD

Supply Voltage 5 9 10 V

Max. input signal handling 2 Vrms

Total Harmonic Distortion V

= 1Vrms; f = 1KHz

= 0.1Vrms; f = 1KHz

0.01 % %

0.1 %

S/N

Signal to Noise Ratio V

Channel Separation f = 1KHz 90 dB

= 1Vrms (0dB)

out

100 dB

Input Gain (2dB step) 0 14 dB

Volume Control (1dB step) -87 0 dB

Treble Control (2dB step) -14 +14 dB

Bass Control (2dB step) -14 +14 dB

Mute Attenuation 86 dB

3/23

TDA7468

ELECTRICAL CHARACTERISTICS

(refer to the test circuit T specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY

SVR Ripple Rejection 60 90 dB

INPUT STAGE

inmin

inmax

MIC

MIX

SURROUND

inmin

inmax

ixmax

CrosstalkCrosstalk of Mux Output to 100%

buffer

VOLUME CONTROL

RANGE1

VMAX1

STEP1

Match1 Matching TBD dB

RANGE2

VMAX2

STEP2

Match2 Matching TBD dB

VMAX1

VMAX2

Supply Voltage 5 9 10 V

Supply Current 9 mA

Input Resistance 35 50 65 KΩ

Clipping Level THD = 0.3% 2 2.5

Input Separation 80 100 dB

Minimum Input Gain -1 0 1 dB

Maximum Input Gain 14 dB

Step Resolution 2 dB

step

Input Resistance 35 50 65 KΩ

Mic Input Gain 1 14 dB

mic1

Mic Input Gain 2 10 dB

mic2

Mic Input Gain 3 6 dB

mic3

Mic Input Gain 4 0 dB

min4

Mixing Rate 50 %

mic

Input Resistance 35 50 65 KΩ

Minimum Input Gain -1 0 1 dB

Maximum Input Gain 12 dB

Inverting Gain -1

inV

Minimum Mixing Rate 0 %

ixmin

Maximum Mixing Rate 100 %

Buffer Gain 6dB

Vol 1 Control Range 63 dB

Vol 1 Max. Attenuation 61 63 65 dB

Vol 1 Step Resolution 0.5 1 1.5 dB

Vol 2 Control Range 24 dB

Vol 2 Max. Attenuation 22 24 26 dB

Vol 2 Step Resolution 7 8 9 dB

Vol 1 + Vol 2 Max Attenuation 84 dB

= 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise

amb

40 dB

Vrms

4/23

TDA7468

ELECTRICAL CHARACTERISTICS (continua)

(refer to the test circuit T specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

BASS CONTROL

Gb Control Range Max. Boost/cut ±12.0 ±14.0 ±16.0 dB

STEP

BASS ALC CONTROL

attack1

attack2

attack3

attack4

Thresh1 Threshold 1 700 mVrms

Thresh2 Threshold 2 485 mVrms

Thresh3 Threshold 3 320 mVrms

Thresh4 Threshold 4 170 mVrms

TREBLE CONTROL

Gt Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB

STEP

AUDIO OUTPUTS

GENERAL

S/N Signal to Noise Ratio

BUS INPUT

Step Resolution 1 2 3 dB

Internal Feedback Resistance 33 44 55 KΩ

Attack Time Resistor 1 12.5 KΩ

Attack Time Resistor 2 25 KΩ

Attack Time Resistor 3 50 KΩ

Attack Time Resistor 4 100 KΩ

Step Resolution 1 2 3 dB

Internal Resistance 25 KΩ

Clipping Level THD = 0.3% 2 2.5

OCL

Output Load Resistance 2 KΩ

DC Voltage Level 4.5 V

Output Noise BW = 20Hz to 20KHz;

Channel Separation Left/Right 90 dB

dDistortion A

Channel Separation left/right 90 dB

Total Tracking Error 0 1 dB

Input Low Voltage 1V

Input High Voltage 2.5 V

Input Current VIN = 0.4V -5 5 µA

Output Voltage (ACK) IO = 1.6mA 0.4 0.8 V

= 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise

amb

All gains 0dB;

output muted 5 µV

flat 10 15 µV

All gains 0dB

= 0; VI = 0.1V

= 0; VI = 1V

; V

rms

= 1V

rms

;

rms

; 0.1 %

; 0.01 %

100 dB

Vrms

5/23

TDA7468

Figure 4. TEST CIRCUIT

-24 att.

BASSO-R

18192021

5.6K

100nF 100nF

BASSI-R

-14 to +14dB

OUT-R

/8dB step

BASS

/2dB step

-24 att. /8dB step

/2dB step

-14 to +14dB

SUPPLY

10µF

REF

GND CREFTREBLE-L

BASSO-LBASSI-L

DGND

SCL

SDA

131215

OUT-L

BASS

3.3nF

TREBLE-R

IS-R

MUX-R

50K

63dB att.

buffer gain:

INPUT

SELECT

TREBLE

/2dB step

-14 to +14dB

/1dB step

+ 6dB gain

MIX

VARIABLE

inverting

non-inverting

/ 2dB step

0 to 14dB gain

0dB

6dB

9dB

12dB

C BUS DECODER + LATCHES

0dB, 6dB

10dB, 14dB

HALF_WAVE

CONTROL

BASS_ALC

RECTIFIER

inverting

non-inverting

/ 2dB step

buffer gain:

0 to 14dB gain

INPUT

SELECT

TREBLE

VARIABLE

0dB

/2dB step

-14 to +14dB

63dB att.

/1dB step

+ 6dB gain

MIX

6dB

9dB

12dB

50K

78 9 10 11 2827

MUX-L IS-L

6/23

0.47µF

IN-R4

50K

0.47µF

IN-R3

50K

0.47µF

IN-R2

50K

0.47µF

IN-R1

50K

MIC-MIX

0.47µF

50K

ALC

0.47µF

IN-L1

0.47µF

50K

IN-L2

0.47µF

IN-L3

50K

0.47µF

IN-L4

50K

D99AU1059A

TDA7468

3 APPLICATION SUGGESTIONS

The first and the last stages are volume control blocks. The control range is 0 to -63dB (mute) with 1dB step resolution for this first one, 0 to 24dB (mute) with 8dB step resolution for the last one.

The very high resolution allows the implementation of systems free from any noisy acoustical effect.

The TDA7468D audioprocessor provides 2 bands tones control.

3.1 Bass, Stages

The Bass cell has an internal resistor R

Several filter types can be implemented, connecting external components to the Bass IN and OUT pins.

The fig.5 refers to basic T Type Bandpass Filter R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows:

= 44KΩ typical.

-----------------------------------------------------------------=

2 π R1 R2 C1 C2⋅⋅⋅⋅⋅

R2 C2 R2 C1 Ri C1++

----------------------------------------------------------------=

starting from the filter component values (R1 internal and

R2 C1 R2 C2+

R1 R2 C1 C2⋅⋅⋅

------------------------------------------------- -=

R2 C1 R2 C2+

1–

CRi

Q⋅⋅ ⋅ ⋅

---------------------------------------------------------------------- -=

2 π C1 F

1– Q2–

CAV

C1⋅

----------------------------- -==

1– Q2–

1–()Q⋅⋅ ⋅⋅⋅

Viceversa, once F

, AV, and Ri internal value are fixed, the external components values will be:

----------------------------------------- -

2 π F

3.2 Treble Stage

The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground.

3.3 CREF

The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON.

Figure 5.

Ri internal

OUTIN

D95AU313

7/23

TDA7468

4I2C BUS INTERFACE

Data transmission from microprocessor to the TDA7468D and vice versa takes place through the 2 wires

C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage

must be connected).

4.1 Data Validity

As shown in fig. 6, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

4.2 Start and Stop Conditions

As shown in fig.7 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

4.3 Byte Format

Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.

4.4 Acknowledge

The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.

4). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.

4.5 Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.

SCL

SDA

SCL

START

CBUS

START

CBUS

DATA LINE

STABLE, DATA

VALID

MSB

CHANGE

DATA

ALLOWED

D99AU1032

23789

D99AU1033

D99AU1031

CBUS

STOP

ACKNOWLEDGMENT

FROM RECEIVER

Figure 6. Data Validity on the I

Figure 7. Timing Diagram of I

Figure 8. Acknowledge on the I

SCL

SDA

8/23

5 SOFTWARE SPECIFICATION

Interface Protocol

The interface protocol comprises:

 A start condition (S)  A chip address byte, containing the TDA7468D address  A subaddress bytes



A sequence of data (N byte + acknowledge)

 A stop condition (P)

CHIP ADDRESS

SUBADDRESS DATA 1 to DATA n

TDA7468

MSB

S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P

D96AU420

LSB MSB LSB MSB LSB

DATA

ACK = Acknowledge

S = Start; P = Stop

A = Address

B = Auto Increment

6 EXAMPLES

6.1 No Incremental Bus

The TDA7468D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.

CHIP ADDRESS

MSB

S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P

D96AU421

LSB MSB LSB MSB LSB

6.2 Incremental Bus

The TDA7468D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored.

The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.

SUBADDRESS DATA

D2 D1 D0

CHIP ADDRESS

MSB

S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P

D96AU422

LSB MSB LSB MSB LSB

SUBADDRESS DATA 1 to DATA n

D2 D1 D0

Table 5. POWER ON RESET CONDITION

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1 111111 0

9/23

TDA7468

7 DATA BYTES

Address = (HEX) 10001000.

Table 6. FUNCTION SELECTION: First byte (subaddress)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

X X X B 0 0 0 0 INPUT SELECT & MIC

XXXB0 0 01INPUT GAIN

X X X B 0 0 1 0 SURROUND

XXXB0 0 11VOLUME LEFT

XXXB0 1 00VOLUME RIGHT

X X X B 0 1 0 1 TREBLE & BASS

XXXB0 1 10OUTPUT

X X X B 0 1 1 1 BASS ALC

B = 1: INCREMENTAL BUS; ACTIVE B = 0: NO INCREMENTAL BUS X = INDIFFERENT 0/1

SUBADDRESS

Table 7. INPUT SELECTION & MIC

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

INPUT SELECT

000 IN1

001 IN2

010 IN3

011 IN4

MUTE (IN5)

1 ON (IN5)

0OFF

0 0 Gain: 14dB

0 1 Gain: 10dB

1 0 Gain: 6dB

1 1 Gain: 0dB

1 OFF

0 ON

MIC

10/23

Table 8. INPUT GAIN SELECTION

MSB LSB INPUT GAIN

D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS

0 0 0 0dB

0 0 1 2dB

0 1 0 4dB

0 1 1 6dB

1 0 0 8dB

1 0 1 10dB

1 1 0 12dB

1 1 1 14dB

GAIN = 0 to 30dB

Table 9. SURROUND

MSB LSB SURROUND

D7 D6 D5 D4 D3 D2 D1 D0

SURROUND MODE

1ON

TDA7468

0OFF

GAIN

00 0dB

01 6dB

10 9dB

1 1 12dB

MIXING

0 0 0 inverting : 100%

0 0 1 inverting :50%

0 1 0 inverting : 25%

011 0%

1 0 0 non-inverting : 100%

1 0 1 non-inverting : 75%

1 1 0 non-inverting : 50%

111 mute

BUFFER GAIN

06dB

11/23

TDA7468

Table 10. VOLUME

MSB LSB VOLUME

D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS

0 0 0 0dB

0 0 1 -1dB

0 1 0 -2dB

0 1 1 -3dB

1 0 0 -4dB

1 0 1 -5dB

1 1 0 -6dB

1 1 1 -7dB

8dB STEPS

0 0 0 0dB

0 0 1 -8dB

0 1 0 -16dB

0 1 1 -24dB

1 0 0 -32dB

1 0 1 -40dB

1 1 0 -48dB

1 1 1 -56dB

VOLUME 2

00 0dB

01 -8dB

10 -16dB

11 -24dB

VOLUME = 0 to-87dB

Table 11. VOLUME setting 1

Target Volume (dB) Volume1 1dB step (dB) Volume1 8dB step (dB) Volume2 8dB step (dB)

0000

-1 -1

-2 -2

-3 -3

-4 -4

-5 -5

-6 -6

-7 -7

-80-80

-9 -1

-10 -2

-11 -3

-12 -4

-13 -5

-14 -6

-15 -7

12/23

Table 11. VOLUME setting 1 (continua)

Target Volume (dB) Volume1 1dB step (dB) Volume1 8dB step (dB) Volume2 8dB step (dB)

-160-160

-17 -1

-18 -2

-19 -3

-20 -4

-21 -5

-22 -6

-23 -7

-240-240

-25 -1

-26 -2

-27 -3

-28 -4

-29 -5

-30 -6

-31 -7

-320-320

-33 -1

-34 -2

-35 -3

-36 -4

-37 -5

-38 -6

-39 -7

-400-400

-41 -1

-42 -2

-43 -3

-44 -4

-45 -5

-46 -6

-47 -7

-480-480

-49 -1

-50 -2

-51 -3

-52 -4

-53 -5

-54 -6

-55 -7

Target Volume (dB) Volume1 1dB step (dB) Volume1 8dB step (dB) Volume2 8dB step (dB)

-560-560

-57 -1

TDA7468

13/23

TDA7468

Table 11. VOLUME setting 1 (continua)

-58 -2

-59 -3

-60 -4

-61 -5

-62 -6

-63 -7

-640-568

-65 -1

-66 -2

-67 -3

-68 -4

-69 -5

-70 -6

-71 -7

-72 0 -56 -16

-73 -1

-74 -2

-75 -3

-76 -4

-77 -5

-78 -6

-79 -7

-80 0 -56 -24

-81 -1

-82 -2

-83 -3

-84 -4

-85 -5

-86 -6

-87 -7

Table 12. VOLUME setting 2

Target Volume (dB) Volume1 1dB step (dB) Volume1 8dB step (dB) Volume2 8dB step (dB)

0000

-1 -1

-2 -2

-3 -3

-4 -4

-5 -5

-6 -6

-7 -7

14/23

Table 12. VOLUME setting 2 (continua)

Target Volume (dB) Volume1 1dB step (dB) Volume1 8dB step (dB) Volume2 8dB step (dB)

-80-80

-9 -1

-10 -2

-11 -3

-12 -4

-13 -5

-14 -6

-15 -7

-160-160

-17 -1

-18 -2

-19 -3

-20 -4

-21 -5

-22 -6

-23 -7

-240-16-8

-25 -1

-26 -2

-27 -3

-28 -4

-29 -5

-30 -6

-31 -7

-32 0 -16 -16

-33 -1

-34 -2

-35 -3

-36 -4

-37 -5

-38 -6

-39 -7

-40 0 -16 -24

-41 -1

-42 -2

-43 -3

-44 -4

-45 -5

-46 -6

-47 -7

TDA7468

15/23

TDA7468

Table 12. VOLUME setting 2 (continua)

Target Volume (dB) Volume1 1dB step (dB) Volume1 8dB step (dB) Volume2 8dB step (dB)

-48 0 -24 -24

-49 -1

-50 -2

-51 -3

-52 -4

-53 -5

-54 -6

-55 -7

-56 0 -32 -24

-57 -1

-58 -2

-59 -3

-60 -4

-61 -5

-62 -6

-63 -7

-64 0 -40 -24

-65 -1

-66 -2

-67 -3

-68 -4

-69 -5

-70 -6

-71 -7

-72 0 -48 -24

-73 -1

-74 -2

-75 -3

-76 -4

-77 -5

-78 -6

-79 -7

-80 0 -56 -24

-81 -1

-82 -2

-83 -3

-84 -4

-85 -5

-86 -6

-87 -7

16/23

Table 13. TREBLE & BASS SELECTION

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0 TREBLE

0 0 0 0 -14dB

0 0 0 1 -12dB

0 0 1 0 -10dB

0011 -8dB

0100 -6dB

0101 -4dB

0110 -2dB

0111 0dB

1 0 0 0 14dB

1 0 0 1 12dB

1 0 1 0 10dB

1011 8dB

1100 6dB

1101 4dB

1110 2dB

1111 0dB

BASS (*)

0 0 0 0 -14dB

0 0 0 1 -12dB

0 0 1 0 -10dB

0011 -8dB

0100 -6dB

0101 -4dB

0110 -2dB

0111 0dB

1 0 0 0 14dB

1 0 0 1 12dB

1 0 1 0 10dB

1011 8dB

1100 6dB

1101 4dB

1110 2dB

1111 0dB

TDA7468

(*) When BASS is programmed in the range -14dB/0dB, ALC is automatically switched to "OFF".

Table 14. OUTPUT

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0 MUTE

0ON

1OFF

17/23

TDA7468

Table 15. BASS ALC

MSB LSB BASS ALC

D7 D6 D5 D4 D3 D2 D1 D0

ALC Mode

1ON

0OFF

Detector

1ON

0OFF

Release Current Circuit

1ON

0OFF

Attack Time Resistor

0 0 12.5KΩ

0 1 25KΩ

1 0 50KΩ

1 1 100KΩ

Threshold

0 0 700mVrms

0 1 485mVrms

1 0 320mVrms

1 1 170mVrms

Attack Mode

0 MODE 1: Fixed Resistor

1 MODE 2: Adaptive

Figure 9. BASS ALC : Threshold curve Figure 10. BASS ALC : THD

RMS

0.1

18/23

)

Supply Voltage : 9.0V Frequency : 60Hz Bassfilter : 60Hz/28dB boost Internal release circuit : ON Attack mode : 12.5kohm, mode2(adaptive)

0.01 0.1 1

Threshold3

Threshold4

D00AU1100

Threshold1

Threshold2

VIN(VRMS)

THD

[%]

Supply Voltage : 9.0V Frequency : 60Hz

Bassfilter : 60Hz/28dB boost Internal release circuit : ON Attack mode : 12.5kohm, mode2(adaptive)

0.1

0.01

0.001

Threshold4

Threshold3

Threshold1

Threshold2

0.01 0.1 1VIN(V

D99AU1101

RMS

)

8IC1

TDA7468

Figure 11. PINS: IN1_L, IN1_R, IN2_L, IN2_R,

IN3_L, IN3_R, IN4_L, IN4 _R, IS_L, IS_R, MIC

20µA

50K

GND

Vref

D99AU1092

Figure 12. PINS: OUT_L, OUT_R, IMUX_L,

MUX_R

20µA

10Ω

GND

D99AU1093

Figure 15. PINS: BASSI_L, BASSI_R

20µA

GND

BASSO-L,BASSO-R

45K

D99AU109

Figure 16. PINS: BASSO_L, BASSO_R

20µA

45K

GND

BASSI-L,BASSI-R

D99AU109

Figure 17. PIN: ALC

Figure 13. PINS: TREBLE_L, TREBLE_R

20µA

25K

GND

D99AU109

Figure 14. PINS: SCL, SDA

20µA

GND

D99AU1095

GND

Figure 18. PIN: CREF

GND

20µA

100K

D99AU1098

20µA

25K

D99AU1099

19/23

TDA7468

9 PACKAGE MECHANICAL DATA

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK

is an ST trademark.

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Figure 19. SO28 Mechanical Data & Package Dimensions

TDA7468

DIM.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

(max.)

OUTLINE AND

MECHANICAL DATA

SO-28

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TDA7468

10 REVISION HISTORY

Table 16. Revision History

Date Revision Description of Changes

January 2004 1 First Issue in EDOCS DMS

June 2004 2 Changed the Style-sheet in compliance to the new “Corporate Technical

March 2006 3 Updated figure 19 “SO28 Mechanical Data & Package Dimensions”

30-Apr-2010 4 Updated title and added environmental compliance statement for

Pubblications Design Guide”

package

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TDA7468

Please Read Carefully:

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ST TDA7468 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 FEATURES

2 DESCRIPTION

Figure 2. PIN CONNECTION (Top view)

Table 1. Order Codes

Figure 3. BLOCK DIAGRAM

Table 2. ABSOLUTE MAXIMUM RATINGS

Table 3. THERMAL DATA

Table 4. QUICK REFERENCE DATA

Figure 4. TEST CIRCUIT

3 APPLICATION SUGGESTIONS

3.1 Bass, Stages

3.2 Treble Stage

3.3 CREF

Figure 5.

4I2C BUS INTERFACE

4.1 Data Validity

4.2 Start and Stop Conditions

4.3 Byte Format

4.4 Acknowledge

4.5 Transmission without Acknowledge

5 SOFTWARE SPECIFICATION

6 EXAMPLES

6.1 No Incremental Bus

6.2 Incremental Bus

Table 5. POWER ON RESET CONDITION

7 DATA BYTES

Table 6. FUNCTION SELECTION: First byte (subaddress)

Table 7. INPUT SELECTION & MIC

Table 8. INPUT GAIN SELECTION

Table 9. SURROUND

Table 10. VOLUME

Table 11. VOLUME setting 1

Table 12. VOLUME setting 2

Table 13. TREBLE & BASS SELECTION

Table 14. OUTPUT

Table 15. BASS ALC

Figure 9. BASS ALC : Threshold curve Figure 10. BASS ALC : THD

8IC1

Figure 15. PINS: BASSI_L, BASSI_R

Figure 16. PINS: BASSO_L, BASSO_R

Figure 17. PIN: ALC

Figure 13. PINS: TREBLE_L, TREBLE_R

Figure 14. PINS: SCL, SDA

Figure 18. PIN: CREF

9 PACKAGE MECHANICAL DATA

Figure 19. SO28 Mechanical Data & Package Dimensions

10 REVISION HISTORY

Table 16. Revision History