TDA7440
)
)
)
Fi
TONE CONTROL
DIGITALLY CONTROLLED AUDIO PROCESSOR
1 FEATURES
INPUT MULTIPLEXER
– 4 STEREO INPUTS
– SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
TREBLE AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
– TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
2 DESCRIPTION
The TDA7440D is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in Hi-Fi systems.
Figure 2. Block Diagram
MUXOUTL INL
April 2010
L-IN1
L-IN2
L-IN3
L-IN4
R-IN1
R-IN2
R-IN3
R-IN4
4
100K
5
100K
+ GAIN
G
0/30dB
2dB STEP
G
6
100K
7
100K
3
100K
2
100K
1
100K
28
100K
INPUT MULTIPLEXER
8 9 18 14 15
VOLUME
VOLUME
10 11 19 12 13 23
MUXOUTR INR
gure 1. Package
SO-28
Table 1. Order Codes
Order code Package
TDA7440D SO-28
TDA7440D013TR Tape & Reel
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
BASS
BASS
R
R
B
B
BOUT(L)
BOUT(R
SPKR ATT
LEFT
SPKR ATT
RIGHT
V
REF
SUPPLY
CREF
27
21
22
20
26
24
25
LOUT
SCL
SDA
DIG_GND
ROUT
V
S
AGND
D98AU883
TREBLE(L)
TREBLE
I2CBUS DECODER + LATCHES
TREBLE
TREBLE(R
BIN(L)
BIN(R
REV. 4
1/17
TDA7440
Figure 3. Pin Connection (Top view)
R_IN3
R_IN2
R_IN1
L_IN1
L_IN2 V
L_IN3
L_IN4
MUXOUTL
IN(L)
MUXOUT(R)
IN(R)
BIN(R)
BOUT(R)
BIN(L)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D98AU884
28
27
26
25
24
22
21
20
19
18
17
16
15
R_IN4
LOUT
ROUT
AGND
S
CREF23
SDA
SCL
DIG-GND
TREBLE(R)
TREBLE(L)
N.C.
N.C.
BOUT(L)
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
T
V
amb
stg
Operating Supply Voltage 10.5 V
S
Operating Ambient Temperature 0 to 70 °C
Storage Temperature Range -55 to 150 °C
Table 3. Thermal Data
Symbol Parameter Value Unit
R
th j-pin
Thermal Resistance Junction-pins 85 °C/W
Table 4. Quick Reference Data
Symbol Parameter Min. Typ. Max. Unit
V
V
THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.1 %
S/N Signal to Noise Ratio V
S
Supply Voltage 6 9 10.2 V
S
Max. input signal handling 2 Vrms
CL
= 1Vrms (mode = OFF) 106 dB
out
Channel Separation f = 1KHz 90 dB
C
Input Gain in (2dB step) 0 30 dB
Volume Control (1dB step) -47 0 dB
Treble Control (2dB step) -14 +14 dB
Bass Control (2dB step) -14 +14 dB
Balance Control 1dB step -79 0 dB
Mute Attenuation 100 dB
2/17
TDA7440
Table 5. Electrical Characteristcs
Refer to the test circuit T
otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
V
SVR Ripple Rejection 60 90 dB
INPUT STAGE
R
V
S
G
inmin
G
inman
G
VOLUME CONTROL
C
RANGE
A
VMAX
A
STEP
E
E
V
A
mute
BASS CONTROL (1)
Gb Control Range Max. Boost/cut +12.0 +14.0 +16.0 dB
B
STEP
R
TREBLE CONTROL (1)
Gt Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB
T
STEP
SPEAKER ATTENUATORS
C
RANGE
S
STEP
E
V
A
mute
NOTE1:
1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device.
2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
Supply Voltage 6 9 10.2 V
S
Supply Current 4 7 10 mA
I
S
Input Resistance 70 100 130 KΩ
IN
Clipping Level THD = 0.3% 2 2.5 Vrms
CL
Input Separation The selected input is grounded
IN
Minimum Input Gain -1 0 1 dB
Maximum Input Gain 29 30 31 dB
Step Resolution 1.5 2 2.5 dB
step
Input Resistance 20 33 50 KΩ
R
i
Control Range 45 47 49 dB
Max. Attenuation 45 47 49 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error AV = 0 to -24dB -1.0 0 1.0 dB
A
Tracking Error AV = 0 to -24dB 0 1 dB
T
DC Step adjacent attenuation steps from
DC
Mute Attenuation 80 100 dB
Step Resolution 1 2 3 dB
Internal Feedback Resistance 33 44 55 KΩ
B
Step Resolution 1 2 3 dB
Control Range 70 76 82 dB
Step Resolution 0.5 1 1.5 dB
Attenuation Set Error
A
DC Step adjacent attenuation steps 0 3 mV
DC
Mute Attenuation 80 100 dB
= 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless
amb
80 100 dB
through a 2.2µ capacitor
= -24 to -47dB -1.5 0 1.5 dB
A
V
= -24 to -47dB 0 2 dB
A
V
0
0dB to A
A
V
A
V
max
V
= 0 to -20dB
-1.5 0 1.5 dB
0.5
= -20 to -56dB -2 0 2 dB
3mV
mV
3/17
TDA7440
Table 5. Electrical Characteristcs (continued)
Refer to the test circuit T
otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUTS
V
CLIP
R
R
V
GENERAL
E
S/N Signal to Noise Ratio All gains 0dB; V
S
BUS INPUT
V
V
I
V
Clipping Level d = 0.3% 2.1 2.6 Vrms
Output Load Resistance 2 KΩ
L
Output Impedance 10 30 50 Ω
O
DC Voltage Level 3.5 3.8 4.1 V
DC
Output Noise All gains = 0dB; 5 15 µV
NO
E
Total Tracking Error AV = 0 to -24dB 0 1 dB
t
Channel Separation Left/Right 80 100 dB
C
dDistortion A
Input Low Voltage 1V
IL
Input High Voltage 3 V
IH
Input Current VIN = 0.4V -5 0 5 µA
IN
Output Voltage SDA
O
Acknowledge
= 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless
amb
BW = 20Hz to 20KHz flat
= -24 to -47dB 0 2 dB
A
V
= 1Vrms 95 106 dB
O
= 0; VI = 1Vrms 0.01 0.08 %
V
IO = 1.6mA 0.4 0.8 V
Figure 4. Test Circuit
L-IN1
0.47µF
L-IN2
0.47µF
L-IN3
0.47µF
L-IN4
0.47µF
R-IN1
0.47µF
R-IN2
0.47µF
R-IN3
0.47µF
R-IN4
0.47µF
5.6nF
2.2µF
4
100K
5
100K
6
100K
7
100K
3
100K
2
100K
1
100K
28
100K
INPUT MULTIPLEXER
MUXOUTL INL
G
0/30dB
2dB STEP
G
+ GAIN
MUXOUTR INR
TREBLE(L)
8 9 18 14 15
VOLUME
VOLUME
10 11 19 12 13 23
2.2µF
TREBLE
I2CBUS DECODER + LATCHES
TREBLE
TREBLE(R)
5.6K
100nF 100nF
BIN(L)
R
B
BASS
BASS
R
B
100nF 100nF
5.6K
BOUT(L)
SPKR ATT
SPKR ATT
RIGHT
SUPPLY
BOUT(R)BIN(R)
LEFT
V
27
LOUT
21
SCL
22
SDA
20
DIG_GND
26
ROUT
REF
24
V
S
25
AGND
D98AU885
CREF
10µF5.6nF
4/17
TDA7440
3 APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution
allows the implementation of systems free from any noisy acoustical effect.
The TDA7440D audioprocessor provides 3 bands tones control.
3.1 Bass Stage
Several filter types can be implemented, connecting external components to the Bass IN and OUT pins.
The fig.5 refers to basic T Type Bandpass Filter
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
starting from the filter component values (R1 internal and
F
-----------------------------------------------------------------=
C
2 π R1 R2 C1 C2⋅⋅⋅⋅⋅
R2 C2 R2 C1 R
--------------------------------------------------------------- -=
A
V
Q
R2 C1 R2 C2+
R1 R2 C1 C2⋅⋅⋅
------------------------------------------------- -=
R2 C1 R2 C2+
1
C1++
i
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
2
C1⋅
Q
----------------------------- -
1– Q2–
A
V
R2
A
---------------------------------------------------------------------- -===
2 π C1 F
V
1– Q2–
CAV
1–()Q⋅⋅ ⋅ ⋅ ⋅
----------------------------------------- -
C1
2 π F
A
V
CRi
1–
C2
Q⋅⋅ ⋅ ⋅
Figure 5.
Ri internal
OUTIN
C
1
R
2
D95AU313
C
2
Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground.
Typical responses are reported in Figg. 14 to 17.
CREF
The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application requires faster power ON.
5/17
TDA7440
Figure 6. THD vs. frequency
Figure 7. THD vs. R
LOAD
Figure 9. Bass response
Ω
Ri = 44k
C9 = C10 = 100nF (Bout, Bin)
R3 = 5.6k
Figure 10. Treble responsey
Ω
Figure 8. Channel separation vs. frequency
6/17
TDA7440
4I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7440D and vice versa takes place through the 2 wires
2
I
C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig. 12 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
13). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 11. Data Validity on the I
SDA
SCL
2
CBUS
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 12. Timing Diagram of I2CBUS
SCL
2
I
CBUS
SDA
START
D99AU1032
STOP
Figure 13. Acknowledge on the I2CBUS
SCL
1
23789
SDA
START
MSB
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
7/17
TDA7440
5 SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (S)
A chip address byte, containing the TDA7440D
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
CHIP ADDRESS
MSB
S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P
D96AU420
LSB MSB LSB MSB LSB
SUBADDRESS DATA 1 to DATA n
X
X
B
X
DATA
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
5.1 EXAMPLES
5.1.1 No Incremental Bus
The TDA7440D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-datas (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS
MSB
S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P
D96AU421
LSB MSB LSB MSB LSB
SUBADDRESS DATA
0
X
D3
X
X
D2 D1 D0
5.1.2 Incremental Bus
The TDA7440D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent
in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS
MSB
S 1 0 0 0 1 0 0 0 ACK ACK DATA ACK P
D96AU422
LSB MSB LSB MSB LSB
8/17
SUBADDRESS DATA 1 to DATA n
1
X
D3
X
X
D2 D1 D0
5.2 POWER ON RESET CONDITION
Table 6.
INPUT SELECTION IN2
INPUT GAIN 28dB
VOLUME MUTE
BASS 0dB
TREBLE 2dB
SPEAKER MUTE
5.3 DATA BYTES
Address = 88 HEX (ADDR:OPEN).
Table 7. FUNCTION SELECTION: First byte (subaddress)
MSB LSB SUBADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
X X X B 0 0 0 0 INPUT SELECT
XXXB0 00 1INPUT GAIN
XXXB0 01 0VOLUME
XXXB0 01 1BASS
XXXB0 10 0NOT USED
XXXB0 10 1TREBLE
X X X B 0 1 1 0 SPEAKER ATTENUATE "R"
X X X B 0 1 1 1 SPEAKER ATTENUATE "L"
TDA7440
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
In Incremental Bus Mode, the "not used" function must be addressed in any case. For example to refresh
"Volume = 0dB" and Speaker_R = -40dB", the following bytes must be sent:
Table 8.
SUBADDRESS XXX10010
VOLUME DATA X0000000
BUS DATA XXXX1111
NOT USED DATA XXXX1111
TREBLE DATA XXXX1111
SPEAKER_R DATA X0000010
Table 9. INPUT SELECTION
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXX0 0 IN4
XXXXXX0 1 IN3
XXXXXX1 0 IN2
XXXXXX1 1 IN1
INPUT MULTIPLEXER
9/17
TDA7440
5.3 DATA BYTES (continued)
Table 10. INPUT GAIN SELECTION
MSB LSB INPUT GAIN
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0000 0dB
0001 2dB
0010 4dB
0011 6dB
0100 8dB
0 1 0 1 10dB
0 1 1 0 12dB
0 1 1 1 14dB
1 0 0 0 16dB
1 0 0 1 18dB
1 0 1 0 20dB
1 0 1 1 22dB
1 1 0 0 24dB
1 1 0 1 26dB
1 1 1 0 28dB
1 1 1 1 30dB
GAIN = 0 to 30dB
Table 11. VOLUME SELECTION
MSB LSB VOLUME
D7 D6 D5 D4 D3 D2 D1 D0 1dB STEPS
000 0dB
001 -1dB
010 -2dB
011 -3dB
100 -4dB
101 -5dB
110 -6dB
111 -7dB
0000 0dB
0001 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
X111XXX MUTE
VOLUME = 0 to 47dB/MUTE
10/17
5.3 DATA BYTES (continued)
Table 12. BASS SELECTION
MSB LSB BASS
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0011 -8dB
0100 -6dB
0101 -4dB
0110 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
TDA7440
Table 13. TREBLE SELECTION
MSB LSB TREBLE
D7 D6 D5 D4 D3 D2 D1 D0 2dB STEPS
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0011 -8dB
0100 -6dB
0101 -4dB
0110 -2dB
0111 0dB
1111 0dB
1110 2dB
1101 4dB
1100 6dB
1011 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
11/17
TDA7440
5.3 DATA BYTES (continued)
Table 14. SPEAKER ATTENUATE SELECTION
MSB LSB SPEAKER ATTENUATION
D7 D6 D5 D4 D3 D2 D1 D0 1dB
0 0 0 0dB
0 0 1 -1dB
0 1 0 -2dB
0 1 1 -3dB
1 0 0 -4dB
1 0 1 -5dB
1 1 0 -6dB
1 1 1 -7dB
0000 0dB
0001 -8dB
0 0 1 0 -16dB
0 0 1 1 -24dB
0 1 0 0 -32dB
0 1 0 1 -40dB
0 1 1 0 -48dB
0 1 1 1 -56dB
1 0 0 0 -64dB
1 0 0 1 -72dB
1111XXX MUTE
12/17
TDA7440
Figure 14. PINS: 23
V
S
CREF
Figure 15. PINS: 26, 27
V
S
ROUT
LOUT
24
Figure 17. PINS: 8, 10
V
V
S
S
20K
MIXOUT
V
S
20µA
20K
GND
D96AU430
D96AU426
Figure 18. PINS: 19, 11
V
S
20µA
INL
20µA
D96AU434
Figure 16. PINS: 1, 2, 3, 4, 5, 6, 7, 28
V
S
IN
100K
V
REF
20µA
D96AU425
INR
V
REF
Figure 19. PINS: 12, 14
V
S
BIN(L)
BIN(R)
33K
D96AU427
20µA
44K
D96AU428
13/17
TDA7440
)
Figure 20. PINS: 13, 15
V
S
BOUT(L)
BOUT(R
Figure 21. PINS: 18, 19
V
S
44K
20µA
20µA
Figure 22. PIN: 20
20µA
SCL
D96AU424
D96AU429
Figure 23. PIN 21
20µA
TREBLE(L)
TREBLE(R)
50K
D96AU433
SDA
D96AU423
6 PACKAGE MECHANICAL DATA
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK
®
is an ST trademark.
®
14/17
Figure 24. SO-28 Mechanical Data & Package Dimensions
TDA7440
DIM.
A 2.65 0.104
a1 0.1 0.3 0.004 0.012
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45° (typ.)
D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419
e 1.27 0.050
e3 16.51 0.65
F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050
S8
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
(max.)
°
OUTLINE AND
MECHANICAL DATA
SO-28
15/17
TDA7440
7 REVISION HISTORY
Table 15. Revision History
Date Revision Description of Changes
January 2004 2 First Issue
June 2004 3 Modified the style-sheet in compliance with the last revision of the
30-Apr-2010 4 Updated title and added environmental compliance statement for
“Corporate Technical Pubblications Design Guide”.
package
16/17
TDA7440
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