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N-CHANNEL CLAMPED 12.5mΩ - 62A TO-220
FULLY PROTECTED MESH OVERLAY™ MOSFET
STP62NS04Z
TYPE
V
DSS
R
DS(on)
I
D
STP62NS04Z CLAMPED <0.015 Ω 62 A
■ TYPICAL R
■ 100% AVALANCHE TESTED
■ LOW CAPACITANCE AND GATE CHARGE
o
■ 175
C MAXIMUM JUNCTION
(on) = 0.0125 Ω
DS
TEMPERATURE
DESCRIPTION
This fully clamped M os fe t is p rod uc ed by u sin g th e l ate st
advanced Company’s Mesh Overlay process which is
based on a novel strip layout.
The inheren t ben ef i t s of th e ne w t ec hn ol o gy co up le d wit h
the extra clamping capabilities make this product
particularly suitable for the harshest operation conditions
such as those encountered in the automotive
environment. Any other application requiring extra
ruggedness is also recommended.
APPLICATIONS
■ ABS, SOLENOID DRIVERS
■ POWER TOOLS
2
TO-220
INTERNAL SCHEMATIC DIAGRAM
Ordering Information
STP62NS04Z P62NS04Z TO-220 TUBE
SALES TYPE MARKING PACKAGE PACKAGING
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DG
V
GS
I
D
I
D
I
DG
I
GS
(•)
I
DM
P
tot
dv/dt
E
AS
V
ESD
T
stg
T
j
(•) Pulse width limited by safe operating area. (1) I
.
Drain-source Voltage (VGS = 0)
CLAMPED V
Drain-gate Voltage CLAMPED V
Gate- source Voltage CLAMPED V
Drain Current (conti nuo us ) at TC = 25°C
Drain Current (conti nuo us ) at TC = 100°C
62 A
37.5 A
Drain Gate Current (co nti nu ou s) ± 50 mA
Gate SourceCurrent (continuous) ± 50 mA
Drain Current (pulse d) 248 A
Total Dissipation at TC = 25°C
110 W
Derating Factor 0.74 W/°C
(1)
Peak Diode Recove ry vo ltag e slo pe 8 V/ns
(2)
Single Pulse Avalanche Energy 500 mJ
ESD (HBM - C = 100pF, R=1.5 kΩ)8kV
Storage Temperature
Operating Junction Temperature
≤40A, di/dt ≤100A/µs, VDD ≤ V
SD
(2) Starting Tj = 25 oC, ID = 20A, VDD= 20V
-55 to 175 °C
, Tj ≤ T
(BR)DSS
JMAX
1/8March 2004
STP62NS04Z
THERMAL DATA
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
(for 10 sec., 1.6mm from case)
Max
Max
1.36
62.5
300
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C unless otherwise specified)
case
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GSS
Clamped Voltage
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
Gate-Source
= 0)
I
= 1 mA, VGS = 0
D
= 16 V
V
DS
= ± 10 V
V
GS
I
= 100 µA
GS
33 V
10 µA
10 µA
18 V
Breakdown Voltage
(*)
ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
V
= VGS ID = 250 µA
DS
V
= 10 V ID = 30 A
GS
24V
12.5 15 m
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
= 15 V ID=30A
DS
V
= 25V, f = 1 MHz, VGS = 0
DS
20 S
1330
420
135
Ω
pF
pF
pF
2/8
STP62NS04Z
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charg e
Gate-Drain Charge
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
t
r(Voff)
t
t
f
f
c
Turn-off Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)
Pulse width limited by safe operating area.
Source-drain Curre nt
Source-drain Curre nt (pu lse d)
(•)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
= 20 V ID = 20 A
DD
=4.7 Ω VGS = 10 V
R
G
(Resistive Load, Figu re 3)
V
= 20 V ID= 40 A VGS= 10V
DD
V
= 20 V ID = 20 A
DD
=4.7 Ω VGS = 10 V
R
G
(Resistive Load, Figu re 3)
V
= 30 V ID = 40 A
clamp
=4.7Ω, V
R
G
GS
= 10 V
(Inductive Load, Figu re 5)
I
= 62 A VGS = 0
SD
I
= 40 A di/dt = 100A/µs
SD
= 20 V Tj = 150°C
V
DD
(see test circuit, Figure 5)
13
104
34
10
11.5
41
42
30
54
90
45
65
2.9
47 nC
62
248
1.5 V
ns
ns
nC
nC
ns
ns
ns
ns
ns
A
A
ns
nC
A
Safe Operating Area
Thermal Impedance
3/8
STP62NS04Z
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-so urc e Vol tag e Capacitance Variations
4/8
STP62NS04Z
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics Normalized Breakdown Voltage Temperature.
. .
5/8
STP62NS04Z
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
TO-220 MECHANICAL DATA
STP62NS04Z
DIM.
A 4.4 4.6 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.40 2.70 0.094 0.106
H2 10 10.40 0.393 0.409
L2 16.10 16.40 16.73 0.633 0.645 0.658
L4 13 14 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.20 6.60 0.244 0.260
L9 3.50 3.93 0.137 0.154
DIA 3.75 3.85 0.147 0.151
MIN. TYP. MAX. MIN. TYP. TYP.
mm. inch.
7/8
STP62NS04Z
I
s
o
d
b
ct
t
ot
a
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
f use of such information nor for any infrin gement of patents or other rights of third parties which may resul t from its use. No license is grant e
y implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subje
o change without notice. This publication supersed es and replaces all information previously supplied. STMicroelectronics products are n
uthorized for use as critical components in life support devices or systems without express written approval of ST Microelectronics.
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All other names are the property of their respective owners.
© 2004 STMicroelectronics - All Rights Reserved
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