ST STD5NK60Z, STP5NK60Z, STP5NK60ZFP User Manual

STP5NK60Z

STD5NK60Z

STP5NK60Z - STP5NK60ZFP

N-CHANNEL 650V @Tjmax - 1.2Ω - 5A TO-220/FP/DPAK

Zener-Protected SuperMESH™ MOSFET

Table 1: General Features

Figure 1: Package

TYPE	VDSS@	RDS(on)	Id	PTOT
	TJmax
STP5NK60Z	650 V	< 1.6 Ω	5 A	90 W
STP5NK60ZFP	650 V	< 1.6 Ω	5 A	25 W
STD5NK60Z	650 V	< 1.6 Ω	5 A	90 W

■TYPICAL RDS(on) = 1.2 Ω

■EXTREMELY HIGH dv/dt CAPABILITY

■100% AVALANCHE TESTED

■GATE CHARGE MINIMIZED

■VERY LOW INTRINSIC CAPACITANCES

■VERY GOOD MANUFACTURING REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products.

APPLICATIONS

■HIGH CURRENT, HIGH SPEED SWITCHING

■IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC

■LIGHTING

Table 2: Order Codes

3	3
2	2
1	1
TO-220	TO-220FP
	3
	1

DPAK

Figure 2: Internal Schematic Diagram

SALES TYPE	MARKING	PACKAGE	PACKAGING
STP5NK60Z	P5NK60Z	TO-220	TUBE
STP5NK60ZFP	P5NK60ZFP	TO-220FP	TUBE
STD5NK60ZT4	D5NK60	DPAK	TAPE & REEL

Rev. 7

December 2005

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STP5NK60Z - STP5NK60ZFPSTD5NK60Z

Table 3: Absolute Maximum ratings

	Symbol	Parameter	Value			Unit
			TO-220/DPAK		TO-220FP
	VDS	Drain-source Voltage (VGS = 0)	600			V
	VDGR	Drain-gate Voltage (RGS = 20 kΩ)	600			V
	VGS	Gatesource Voltage	± 30			V
	ID	Drain Current (continuous) at TC = 25°C	5		5 (*)	A
	ID	Drain Current (continuous) at TC = 100°C	3.16		3.16 (*)	A
	IDM (z)	Drain Current (pulsed)	20		20 (*)	A
	PTOT	Total Dissipation at TC = 25°C	90		25	W
		Derating Factor	0.72		0.2	W/°C
	VESD(G-S)	Gate source ESD(HBM-C=100pF, R=1.5KΩ)	3000			V
	dv/dt (1)	Peak Diode Recovery voltage slope	4.5			V/ns
	VISO	Insulation Withstand Voltage (DC)	-		2500	V
	Tj	Operating Junction Temperature	-55 to 150			°C
	Tstg	Storage Temperature
	(z) Pulse width limited by safe operating area
	(1) ISD ≤5A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.
	(*) Limited only by maximum temperature allowed
	Thermal Data
			TO-220/DPAK		TO-220FP
	Rthj-case	Thermal Resistance Junction-case Max	1.39		5	°C/W
	Rthj-amb	Thermal Resistance Junction-ambient Max	62.5			°C/W
	Tl	Maximum Lead Temperature For Soldering Purpose	300			°C

(#) When mounted on 1inch² FR-4, 2 Oz copper board.

Table 4: Avalanche Characteristics

Symbol	Parameter	Max Value	Unit
IAR	Avalanche Current, Repetitive or Not-Repetitive	5	A
	(pulse width limited by Tj max)
EAS	Single Pulse Avalanche Energy	220	mJ
	(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

Table 5: Gate-Source Zener Diode

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
BVGSO	Gate-Source Breakdown	Igs=± 1mA (Open Drain)	30			V
	Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

Table 6: On/Off

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
V(BR)DSS	Drain-source	ID = 1 mA, VGS = 0	600			V
	Breakdown Voltage
IDSS	Zero Gate Voltage	VDS = Max Rating			1	µA
	Drain Current (VGS = 0)	VDS = Max Rating, TC = 125 °C			50	µA
IGSS	Gate-body Leakage	VGS = ± 20V			±10	µA
	Current (VDS = 0)
VGS(th)	Gate Threshold Voltage	VDS = VGS, ID = 50µA	3	3.75	4.5	V
RDS(on)	Static Drain-source On	VGS = 10V, ID = 2.5 A		1.2	1.6	Ω
	Resistance

Table 7: Dynamic

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
gfs (1)	Forward Transconductance	VDS = 8 V, ID = 2.5 A		4		S
Ciss	Input Capacitance	VDS = 25V, f = 1 MHz, VGS = 0		690		pF
Coss	Output Capacitance			90		pF
Crss	Reverse Transfer			20		pF
	Capacitance
Coss eq. (3)	Equivalent Output	VGS = 0V, VDS = 0V to 480V		40		pF
	Capacitance
td(on)	Turn-on Delay Time	VDD = 300 V, ID = 2.5 A		16		ns
tr	Rise Time	RG = 4.7Ω VGS = 10 V		25		ns
td(off)	Turn-off Delay Time	(see Figure 20)		36		ns
tr	Fall Time			25		ns
tr(Voff)	Off-voltage Rise Time	VDD = 480V, ID = 5 A,		12		ns
tf	Fall Time	RG = 4.7Ω, VGS = 10V		10		ns
tc	Cross-over Time	(see Figure 20)		24		ns
Qg	Total Gate Charge	VDD = 400V, ID = 5 A,		26	34	nC
Qgs	Gate-Source Charge	VGS = 10V		6		nC
Qgd	Gate-Drain Charge	(see Figure 23)		20		nC

Table 8: Source Drain Diode

Symbol	Parameter		Test Conditions	Min.	Typ.	Max.	Unit
ISD	Source-drain Current					5	A
ISDM (2)	Source-drain Current (pulsed)					20	A
VSD (1)	Forward On Voltage	ISD = 5	A, VGS = 0			1.6	V
trr	Reverse Recovery Time	ISD = 5	A, di/dt = 100A/µs		485		ns
Qrr	Reverse Recovery Charge	VDD = 30V, Tj = 150°C			2.7		µC
IRRM	Reverse Recovery Current	(see Figure 21)			11		A

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

2.Pulse width limited by safe operating area.

3.Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.

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Figure 3: Safe Operating Area For TO-220/

DPAK

Figure 4: Safe Operating Area For TO-220FP

Figure 5: Output Characteristics

Figure 6: Thermal Impedance For TO-220/

DPAK

Figure 7: Thermal Impedance For TO-220FP

Figure 8: Transfer Characteristics

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Figure 9: Transconductance

Figure 10: Gate Charge vs Gate-source Voltage

Figure 11: Normalized Gate Threshold Voltage vs Temperature

Figure 12: Static Drain-source On Resistance

Figure 13: Capacitance Variations

Figure 14: Normalized On Resistance vs Temperature

Figure 15:

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