ST STMPE812 User Manual
enhanced 4-wire resistive touchscreen controller with PWM
Features
■ 4 GPIOs (8 mA drive, 12 mA sink at 3.3 V)
■ 1 additional, general purpose 12-bit ADC
■ Operating voltage 1.65 - 3.6 V
■ Integrated 4-wire touchscreen controller, pen-
down/real-time mode, fully-autonomous
■ 1 PWM controller
■ Auto-hibernation and low power
– Typ 0.5
– Typ 100
■ Interrupt output pin (optional)
■ Reset input pin (optional)
■ Wake-up feature on each port configured as
GPIO input
2
■ I
C interface
■ 8 kV HBM, 1 kV CDM ESD protection on
X+/X-/Y+/Y-
■ 2 kV HBM, 250 V CDM ESD protection on all
other pins
µA in Hibernation mode
µA in Active mode
STMPE812
S-Touch
Flip-chip CSP12
(2.17 x 1.67 mm)
Description
The STMPE812 is a 4-wire resistive touchscreen
controller with 4-bit port expander integrated.
The touchscreen controller is designed to be fully
autonomous, requiring only minimal CPU
intervention for sampling, filtering and preprocessing operations.
®
Applications
■ Portable media players
■ Game consoles
■ Mobile and smart phones
Table 1. Device summary
Order code Package Packaging
STMPE812BJR Flip-chip CSP12 (2.17 x 1.67 mm) Tape and reel
February 2011 Doc ID 17732 Rev 3 1/51
www.st.com
51
Contents STMPE812
Contents
1 STMPE812 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 STMPE812 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Auto-increment/non auto-increment address . . . . . . . . . . . . . . . . . . . . . . 16
7 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9 ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 Register map for PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2 Interrupt of PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11 Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.1 Touchscreen controller detection sequence . . . . . . . . . . . . . . . . . . . . . . . 30
11.2 3 modes of acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.3 Touchscreen controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.4 Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/51 Doc ID 17732 Rev 3
STMPE812 Contents
12 GPIO port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
14 Package mechanical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 17732 Rev 3 3/51
STMPE812 functional overview STMPE812
1 STMPE812 functional overview
The STMPE812 consists of the following blocks:
2
● I
C interface
● GPIO/PWM controller
● Touchscreen controller (TSC)
● Analog-to-digital converted (ADC)
● Driver and switch control unit
Figure 1. STMPE812 block diagram
Tou ch
VDD
GND
Power
Power
Management
Management
Tou ch
Screen
Screen
Drivers and
Drivers and
Switches
Switches
X+
X+
X-
XY+
Y+
Y-
Y-
SDA
SCL
TSC: Touchscreen controller
ADC: Ana log to
Digital Converter
I2C InterfaceI2C Interface
TSC
TSCTSC
ADC
ADCADC
GPIO/PWM
GPIO/PWM
Controller
Controller
POR
PORPOR
Reset
Reset
System
System
M
U
X
GPIO0/ADC/PWM1
GPIO1/ADC
GPIO2/RESET
GPIO3/INT
!-6
4/51 Doc ID 17732 Rev 3
STMPE812 STMPE812 functional overview
1.1 Pin configuration and functions
Figure 2. Pin configuration (top through view)
8
!
6##
!
0
!
Table 2. Pin assignments
9
"
0
"
0
"
8
#
0
#
3$!
#
9
$
'.$
$
3#,
$
Pin Name Current capacity Function
B3 Y+ 50 mA current limit Y+
C3 X- 50 mA current limit X-
!-6
D3 Y- 50 mA current limit Y-
C2 P1
+8 mA/-12 mA at
3.3 V
Can be > 80 mA
D2 GND
load at touchscreen
and GPIO drive
D1 SCL -4 mA
C1 SDA -4 mA
B1 P3
A1 P2
+8 mA/-12 mA at
3.3 V
+8 mA/-12 mA at
3.3 V
Doc ID 17732 Rev 3 5/51
GPIO-0 / ADC / PWM1 (3.6 V tolerant within V
valid range; VIN_ADC must be less than Vcc))
Ground
2
I
C clock (fail safe, tolerant to 3.6 V regardless of
VCC)
2
C data (fail safe, tolerant to 3.6 V regardless of
I
)
V
CC
GPIO-3 / INT (3.6 V tolerant within V
CC
valid
range)
GPIO-2 / RESET (3.6 V tolerant within V
CC
valid
range)
CC
STMPE812 functional overview STMPE812
Table 2. Pin assignments (continued)
Pin Name Current capacity Function
B2 P0
A2 V
CC
+8 mA/-12 mA at
3.3 V
Can be > 80 mA
load at touchscreen
and GPIO drive
GPIO-1 / ADC (3.6 V tolerant within V
range, VIN_ADC must be less htan V
1.65 - 3.6 V core/IO supply (0.1 µF decoupling
cap)
No low-voltage detection for POR
20 µs POR from power stable
A3 X+ 50 mA current limit X+
Note: All I/O operates on VCC. All I/O tolerant up to 3.6 V, across VCC = 1.65 - 3.6 V.
8 kV HBM ESD on all touchscreen pins (+/- 8 kV vs GND).
0.5 µA max input leakage as input, across V
range (GPIO, SCL/SDA).
CC
4 µs hardware filter on the 4 GPIOs as input.
1.2 Typical application
Figure 3. Typical application
6
CC
CC
valid
)
6##
).40
3#,
3$!
2%3%4
0
34-0%
'.$
0
0
WIRE
RESISTIVE
TOUCHSCREEN
#ANBEUSEDAS!$#07-OR'0)/
!-6
6/51 Doc ID 17732 Rev 3
STMPE812 I2C interface
2 I2C interface
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, there is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Figure 4. I
SDA
SCL
2
C timing diagram
tHD:STAtBUF
SP
tHD:STA
tHIGH
tLOW
tF
tSU:DAT
tHD:DAT
SR
P
AI00589
tR
Table 3. I2C timing
Symbol Parameter Min Typ Max Uni
f
SCL
t
LOW
t
HIGH
t
F
t
HD:STA
t
SU:STA
SCL clock frequency 0 – 400 kHz
Clock low period 1.3 – – µs
Clock high period 600 – – ns
SDA and SCL fall time – – 300 ns
START condition hold time (after this
period the first clock is generated)
START condition setup time (only relevant
for a repeated start period)
600 – – ns
600 – – ns
tSU:STOtSU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
Data setup time 100 – – ns
Data hold time 0 – – µs
STOP condition setup time 600 – – ns
Time the bus must be free before a new
transmission can start
1.3 – – µs
Doc ID 17732 Rev 3 7/51
I2C interface STMPE812
2.1 I2C features
The features that are supported by the I2C interface are listed below:
2
● I
C slave device
● Operates at V
● Compliant to Philips I
● Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
● I2C address in 0x41 (0x82/83 including Rd/Wr bit)
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
2
next I
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
(1.65 V - 3.6 V)
CC
2
C specification version 2.1
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
2.2 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Table 4. Operating modes
Mode Byte Programming sequence
Read ≥1
Start, Device address, R/W
Restart, Device address, R/W
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after
every byte of data being read. For register address that falls within a
non-incremental address range, the address is kept static throughout
the entire read operations. Refer to the memory map table for the
address ranges that are auto and non-increment.
= 0, Register address to be read
= 1, Data Read, Stop
8/51 Doc ID 17732 Rev 3
STMPE812 I2C interface
Table 4. Operating modes
Mode Byte Programming sequence
Start, Device address, R/W
= 0, Register address to be written, Data
Write, Stop
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto-
Write ≥1
increment, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address is kept static
throughout the entire write operation. Refer to the memory map table
for the address ranges that are auto and non-increment.
Figure 5. Read and write modes (random and sequential)
One byte
Read
More than one byte
More than one byte
Read
One byte
Write
Read
Start
Start
Start
Start
Device
Address
Device
Address
Device
Address
Device
Address
R/W=0
R/W=0
R/W=0
R/W=0
Ack
Ack
Ack
Ack
Reg
Address
Reg
Address
Reg
Address
Reg
Address
Ack
Ack
Device
Address
Device
Address
Restart
R/W=1
R/W=1
Data
Ack
Read
Data
Ack
Read
Stop
No Ack
Ack
Read + 1
Data
to be
written
Ack
Stop
Ack
Ack
Data to
Write
Ack
Write + 1
Data to
Ack
Write + 2
Data to
Data
Ack
Stop
Ack
Data
Read + 2
Stop
No Ack
Master
Slave
AM04175V1
Doc ID 17732 Rev 3 9/51
I2C interface STMPE812
2.3 Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read comes from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
2.4 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
10/51 Doc ID 17732 Rev 3
STMPE812 Power supply
3 Power supply
The STMPE812 GPIO operates from a supply pin VCC. For better resolution and noise
immunity, V
Power up reset
The STMPE812 is equipped with an internal POR circuit that holds the device in reset state,
until the V
above 2.8 V is recommended.
CC
supply input is valid. The internal POR is tied to the VCC supply pin.
CC
Doc ID 17732 Rev 3 11/51
Charge pump STMPE812
4 Charge pump
The STMPE812 is integrated with an internal charge-pump. The charge pump is required for
any ADC/TSC operations when V
Activating the charge pump when V
device.
is less than 2.5 V.
CC
> 2.5 V may result in permanent damage of the
CC
12/51 Doc ID 17732 Rev 3
STMPE812 Power modes
5 Power modes
The STMPE812 operates in a 2 states: active and hibernate.
Active:
– Whenever PEN-DOWN is detected, the device remains in active mode
– Whenever PWM is active, the device remains in active mode
– Whenever ADC is active, the device remains in ACTIVE MODE
Hibernate:
-PWM/ADC must be “off” (clock disable bit SET)
-Any GPIO input, with interrupt enabled cause a transition to “active” state, if an input
change is detected.
-Pen down even causes transition to “active” state if the touchscreen controller is enabled.
Table 5. Power mode
Power mode Active Hibernate
Current consumption 280 µA (max)
GPIO hotkey Yes Yes
(1)
1.0 µA (max.)
Touchscreen Yes Yes
2
Interface (I
1. At Vcc=1.8V, TCS running at 100sets of X/Y per second, MAV disabled.
C) Yes Yes
Doc ID 17732 Rev 3 13/51
Power modes STMPE812
Figure 6. Power modes state diagram
ACTIVE
No activity
(about 33 μs)
STMPE812 is in
active mode if PWM
is running
Soft -Reset, Reset input
I2C activity,
Touch, Hotkey
AUTO -
HIBERNATE
POR
Reset Input
On power up reset, the device goes to active state. However, as all the functional blocks are
2
clocked off by default, no touch/hotkey activity is possible. If there are no I
C activities,
device goes into auto-hibernate mode automatically.
The auto-hibernate feature of STMPE812 is always enabled. Whenever there is a period of
inactivity, the device enters this mode to reduce power consumption. On detection a touch,
correctly addressed I
2
C data, GPIO activity, the device wakes up immediately.
As the device is able to wake up very quickly, there is no loss of touch data.
14/51 Doc ID 17732 Rev 3
STMPE812 STMPE812 registers
6 STMPE812 registers
This section lists and describes the registers of the STMPE812 device, starting with a
register map and then provides detailed descriptions of register types.
Table 6. Register summary map table
Address Register name Bit Type Reset value Function
Registers from 0x00 - 0x0F are always accessible.
0x00 - 01 CHIP_ID 16 R 0x0812 Device identification
0x02 ID_VER 8 R 0x10
0x03 SYS_CTRL 8 R/W 0x0F System control register
0x04
0x06 - 07 SCRATCH_PAD 16 R/W 0x00
0x08 INT_CTRL 8 R/W 0x00 Interrupt control register
0x09 INT_EN 8 R/W 0x00 interrupt enable register
0x0A INT_STA 8 R 0x00 Interrupt status register
Registers from 0x10 - 0x1F are accessible only if “GPIO_OFF” bit in SYS_CTRL is set to “0”.
0x10 GPIO_SET_PIN 8 R/W 0x00 GPIO set pin register
0x11 GPIO_CLR_PIN 8 R/W 0x00 GPIO clear pin register
0x12 GPIO_MP_STA 8 R/W 0x00
0x13 GPIO_DIR 8 R/W 0x00
0x14 GPIO_ED 8 R/W 0x00
PORT_FUNCTI
ON
8 R/W 0x00 Port function control register
Revision number
0x10 for engineering sample
General purpose storage
register
GPIO monitor pin state
register
GPIO falling edge register
GPIO rising edge register
Registers from 0x20 - 0x2F are accessible only if “ADC_OFF” bit in SYS_CTRL is set to “0”.
0x20 ADC_CTRL 8 R/W 0x32 ADC control
0x21 - 22 ADC_DATA 16 R 0x0000 ADC data
Registers from 0x40 - 0x4F are accessible only if “TSC_OFF” bit in SYS_CTRL is set to “0”.
0x40 TSC_CTRL 8 R/W 0x00
0x41
0x42
0x43
TSC_DET_CFG
1
TSC_DET_CFG
2
TSC_SAMPLIN
G_RATE
8R/W 0xA4
8R/W 0xB0
8R/W 0x0A
Doc ID 17732 Rev 3 15/51
4-wire touchscreen
controller setup
Touchscreen controller
configuration 1
Touchscreen controller
configuration 2
Touchscreen controller
sampling rate register
STMPE812 registers STMPE812
Table 6. Register summary map table (continued)
Address Register name Bit Type Reset value Function
0x44 TSC_DATA 8 R - Non auto-increment address
Registers from 0x50 - 0x5F are accessible only if “PWM_OFF” bit in SYS_CTRL is set to “0”.
0x50
PWM_CLOCK_
DIV
8 R/W 0x00 PWM clock divider
0x51 PWM_CTRL1 8 R/W 0x00
6.1 Auto-increment/non auto-increment address
The STMPE812 supports auto-increment accesses on all, except for TSC data register
(0x44). While accessing auto-increment register location, consecutive read/write access
data from the consecutive registers. Note that for register accesses started on autoincremental addresses, the address 0x44 is skipped.
For example:
Write register address (0x40)
Read data (data of 0x40)
Read data (data of 0x41)
Read data (data of 0x42)
Read data (data of 0x43)
Read data (data of 0x45) <= 0x44 is skipped.
Master control of PWM
channel 1
16/51 Doc ID 17732 Rev 3
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