enhanced 4-wire resistive touchscreen controller with PWM
Features
■ 4 GPIOs (8 mA drive, 12 mA sink at 3.3 V)
■ 1 additional, general purpose 12-bit ADC
■ Operating voltage 1.65 - 3.6 V
■ Integrated 4-wire touchscreen controller, pen-
down/real-time mode, fully-autonomous
■ 1 PWM controller
■ Auto-hibernation and low power
– Typ 0.5
– Typ 100
■ Interrupt output pin (optional)
■ Reset input pin (optional)
■ Wake-up feature on each port configured as
GPIO input
2
■ I
C interface
■ 8 kV HBM, 1 kV CDM ESD protection on
X+/X-/Y+/Y-
■ 2 kV HBM, 250 V CDM ESD protection on all
other pins
µA in Hibernation mode
µA in Active mode
STMPE812
S-Touch
Flip-chip CSP12
(2.17 x 1.67 mm)
Description
The STMPE812 is a 4-wire resistive touchscreen
controller with 4-bit port expander integrated.
The touchscreen controller is designed to be fully
autonomous, requiring only minimal CPU
intervention for sampling, filtering and preprocessing operations.
®
Applications
■ Portable media players
■ Game consoles
■ Mobile and smart phones
Table 1. Device summary
Order code Package Packaging
STMPE812BJR Flip-chip CSP12 (2.17 x 1.67 mm) Tape and reel
February 2011 Doc ID 17732 Rev 3 1/51
www.st.com
51
Contents STMPE812
Contents
1 STMPE812 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 STMPE812 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Auto-increment/non auto-increment address . . . . . . . . . . . . . . . . . . . . . . 16
7 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9 ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 Register map for PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2 Interrupt of PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11 Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11.1 Touchscreen controller detection sequence . . . . . . . . . . . . . . . . . . . . . . . 30
11.2 3 modes of acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.3 Touchscreen controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.4 Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/51 Doc ID 17732 Rev 3
STMPE812 Contents
12 GPIO port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
14 Package mechanical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 17732 Rev 3 3/51
STMPE812 functional overview STMPE812
1 STMPE812 functional overview
The STMPE812 consists of the following blocks:
2
● I
C interface
● GPIO/PWM controller
● Touchscreen controller (TSC)
● Analog-to-digital converted (ADC)
● Driver and switch control unit
Figure 1. STMPE812 block diagram
Tou ch
VDD
GND
Power
Power
Management
Management
Tou ch
Screen
Screen
Drivers and
Drivers and
Switches
Switches
X+
X+
X-
XY+
Y+
Y-
Y-
SDA
SCL
TSC: Touchscreen controller
ADC: Ana log to
Digital Converter
I2C InterfaceI2C Interface
TSC
TSCTSC
ADC
ADCADC
GPIO/PWM
GPIO/PWM
Controller
Controller
POR
PORPOR
Reset
Reset
System
System
M
U
X
GPIO0/ADC/PWM1
GPIO1/ADC
GPIO2/RESET
GPIO3/INT
!-6
4/51 Doc ID 17732 Rev 3
STMPE812 STMPE812 functional overview
1.1 Pin configuration and functions
Figure 2. Pin configuration (top through view)
8
!
6##
!
0
!
Table 2. Pin assignments
9
"
0
"
0
"
8
#
0
#
3$!
#
9
$
'.$
$
3#,
$
Pin Name Current capacity Function
B3 Y+ 50 mA current limit Y+
C3 X- 50 mA current limit X-
!-6
D3 Y- 50 mA current limit Y-
C2 P1
+8 mA/-12 mA at
3.3 V
Can be > 80 mA
D2 GND
load at touchscreen
and GPIO drive
D1 SCL -4 mA
C1 SDA -4 mA
B1 P3
A1 P2
+8 mA/-12 mA at
3.3 V
+8 mA/-12 mA at
3.3 V
Doc ID 17732 Rev 3 5/51
GPIO-0 / ADC / PWM1 (3.6 V tolerant within V
valid range; VIN_ADC must be less than Vcc))
Ground
2
I
C clock (fail safe, tolerant to 3.6 V regardless of
VCC)
2
C data (fail safe, tolerant to 3.6 V regardless of
I
)
V
CC
GPIO-3 / INT (3.6 V tolerant within V
CC
valid
range)
GPIO-2 / RESET (3.6 V tolerant within V
CC
valid
range)
CC
STMPE812 functional overview STMPE812
Table 2. Pin assignments (continued)
Pin Name Current capacity Function
B2 P0
A2 V
CC
+8 mA/-12 mA at
3.3 V
Can be > 80 mA
load at touchscreen
and GPIO drive
GPIO-1 / ADC (3.6 V tolerant within V
range, VIN_ADC must be less htan V
1.65 - 3.6 V core/IO supply (0.1 µF decoupling
cap)
No low-voltage detection for POR
20 µs POR from power stable
A3 X+ 50 mA current limit X+
Note: All I/O operates on VCC. All I/O tolerant up to 3.6 V, across VCC = 1.65 - 3.6 V.
8 kV HBM ESD on all touchscreen pins (+/- 8 kV vs GND).
0.5 µA max input leakage as input, across V
range (GPIO, SCL/SDA).
CC
4 µs hardware filter on the 4 GPIOs as input.
1.2 Typical application
Figure 3. Typical application
6
CC
CC
valid
)
6##
).40
3#,
3$!
2%3%4
0
34-0%
'.$
0
0
WIRE
RESISTIVE
TOUCHSCREEN
#ANBEUSEDAS!$#07-OR'0)/
!-6
6/51 Doc ID 17732 Rev 3
STMPE812 I2C interface
2 I2C interface
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, there is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Figure 4. I
SDA
SCL
2
C timing diagram
tHD:STAtBUF
SP
tHD:STA
tHIGH
tLOW
tF
tSU:DAT
tHD:DAT
SR
P
AI00589
tR
Table 3. I2C timing
Symbol Parameter Min Typ Max Uni
f
SCL
t
LOW
t
HIGH
t
F
t
HD:STA
t
SU:STA
SCL clock frequency 0 – 400 kHz
Clock low period 1.3 – – µs
Clock high period 600 – – ns
SDA and SCL fall time – – 300 ns
START condition hold time (after this
period the first clock is generated)
START condition setup time (only relevant
for a repeated start period)
600 – – ns
600 – – ns
tSU:STOtSU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
Data setup time 100 – – ns
Data hold time 0 – – µs
STOP condition setup time 600 – – ns
Time the bus must be free before a new
transmission can start
1.3 – – µs
Doc ID 17732 Rev 3 7/51
I2C interface STMPE812
2.1 I2C features
The features that are supported by the I2C interface are listed below:
2
● I
C slave device
● Operates at V
● Compliant to Philips I
● Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
● I2C address in 0x41 (0x82/83 including Rd/Wr bit)
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
2
next I
C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
(1.65 V - 3.6 V)
CC
2
C specification version 2.1
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
2.2 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Table 4. Operating modes
Mode Byte Programming sequence
Read ≥1
Start, Device address, R/W
Restart, Device address, R/W
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address autoincrement, then the register address auto-increments internally after
every byte of data being read. For register address that falls within a
non-incremental address range, the address is kept static throughout
the entire read operations. Refer to the memory map table for the
address ranges that are auto and non-increment.
= 0, Register address to be read
= 1, Data Read, Stop
8/51 Doc ID 17732 Rev 3
STMPE812 I2C interface
Table 4. Operating modes
Mode Byte Programming sequence
Start, Device address, R/W
= 0, Register address to be written, Data
Write, Stop
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto-
Write ≥1
increment, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address is kept static
throughout the entire write operation. Refer to the memory map table
for the address ranges that are auto and non-increment.
Figure 5. Read and write modes (random and sequential)
One byte
Read
More than one byte
More than one byte
Read
One byte
Write
Read
Start
Start
Start
Start
Device
Address
Device
Address
Device
Address
Device
Address
R/W=0
R/W=0
R/W=0
R/W=0
Ack
Ack
Ack
Ack
Reg
Address
Reg
Address
Reg
Address
Reg
Address
Ack
Ack
Device
Address
Device
Address
Restart
R/W=1
R/W=1
Data
Ack
Read
Data
Ack
Read
Stop
No Ack
Ack
Read + 1
Data
to be
written
Ack
Stop
Ack
Ack
Data to
Write
Ack
Write + 1
Data to
Ack
Write + 2
Data to
Data
Ack
Stop
Ack
Data
Read + 2
Stop
No Ack
Master
Slave
AM04175V1
Doc ID 17732 Rev 3 9/51
I2C interface STMPE812
2.3 Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read comes from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
2.4 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
10/51 Doc ID 17732 Rev 3
STMPE812 Power supply
3 Power supply
The STMPE812 GPIO operates from a supply pin VCC. For better resolution and noise
immunity, V
Power up reset
The STMPE812 is equipped with an internal POR circuit that holds the device in reset state,
until the V
above 2.8 V is recommended.
CC
supply input is valid. The internal POR is tied to the VCC supply pin.
CC
Doc ID 17732 Rev 3 11/51
Charge pump STMPE812
4 Charge pump
The STMPE812 is integrated with an internal charge-pump. The charge pump is required for
any ADC/TSC operations when V
Activating the charge pump when V
device.
is less than 2.5 V.
CC
> 2.5 V may result in permanent damage of the
CC
12/51 Doc ID 17732 Rev 3
STMPE812 Power modes
5 Power modes
The STMPE812 operates in a 2 states: active and hibernate.
Active:
– Whenever PEN-DOWN is detected, the device remains in active mode
– Whenever PWM is active, the device remains in active mode
– Whenever ADC is active, the device remains in ACTIVE MODE
Hibernate:
-PWM/ADC must be “off” (clock disable bit SET)
-Any GPIO input, with interrupt enabled cause a transition to “active” state, if an input
change is detected.
-Pen down even causes transition to “active” state if the touchscreen controller is enabled.
Table 5. Power mode
Power mode Active Hibernate
Current consumption 280 µA (max)
GPIO hotkey Yes Yes
(1)
1.0 µA (max.)
Touchscreen Yes Yes
2
Interface (I
1. At Vcc=1.8V, TCS running at 100sets of X/Y per second, MAV disabled.
C) Yes Yes
Doc ID 17732 Rev 3 13/51
Power modes STMPE812
Figure 6. Power modes state diagram
ACTIVE
No activity
(about 33 μs)
STMPE812 is in
active mode if PWM
is running
Soft -Reset, Reset input
I2C activity,
Touch, Hotkey
AUTO -
HIBERNATE
POR
Reset Input
On power up reset, the device goes to active state. However, as all the functional blocks are
2
clocked off by default, no touch/hotkey activity is possible. If there are no I
C activities,
device goes into auto-hibernate mode automatically.
The auto-hibernate feature of STMPE812 is always enabled. Whenever there is a period of
inactivity, the device enters this mode to reduce power consumption. On detection a touch,
correctly addressed I
2
C data, GPIO activity, the device wakes up immediately.
As the device is able to wake up very quickly, there is no loss of touch data.
14/51 Doc ID 17732 Rev 3
STMPE812 STMPE812 registers
6 STMPE812 registers
This section lists and describes the registers of the STMPE812 device, starting with a
register map and then provides detailed descriptions of register types.
Table 6. Register summary map table
Address Register name Bit Type Reset value Function
Registers from 0x00 - 0x0F are always accessible.
0x00 - 01 CHIP_ID 16 R 0x0812 Device identification
0x02 ID_VER 8 R 0x10
0x03 SYS_CTRL 8 R/W 0x0F System control register
0x04
0x06 - 07 SCRATCH_PAD 16 R/W 0x00
0x08 INT_CTRL 8 R/W 0x00 Interrupt control register
0x09 INT_EN 8 R/W 0x00 interrupt enable register
0x0A INT_STA 8 R 0x00 Interrupt status register
Registers from 0x10 - 0x1F are accessible only if “GPIO_OFF” bit in SYS_CTRL is set to “0”.
0x10 GPIO_SET_PIN 8 R/W 0x00 GPIO set pin register
0x11 GPIO_CLR_PIN 8 R/W 0x00 GPIO clear pin register
0x12 GPIO_MP_STA 8 R/W 0x00
0x13 GPIO_DIR 8 R/W 0x00
0x14 GPIO_ED 8 R/W 0x00
PORT_FUNCTI
ON
8 R/W 0x00 Port function control register
Revision number
0x10 for engineering sample
General purpose storage
register
GPIO monitor pin state
register
GPIO falling edge register
GPIO rising edge register
Registers from 0x20 - 0x2F are accessible only if “ADC_OFF” bit in SYS_CTRL is set to “0”.
0x20 ADC_CTRL 8 R/W 0x32 ADC control
0x21 - 22 ADC_DATA 16 R 0x0000 ADC data
Registers from 0x40 - 0x4F are accessible only if “TSC_OFF” bit in SYS_CTRL is set to “0”.
0x40 TSC_CTRL 8 R/W 0x00
0x41
0x42
0x43
TSC_DET_CFG
1
TSC_DET_CFG
2
TSC_SAMPLIN
G_RATE
8R/W 0xA4
8R/W 0xB0
8R/W 0x0A
Doc ID 17732 Rev 3 15/51
4-wire touchscreen
controller setup
Touchscreen controller
configuration 1
Touchscreen controller
configuration 2
Touchscreen controller
sampling rate register
STMPE812 registers STMPE812
Table 6. Register summary map table (continued)
Address Register name Bit Type Reset value Function
0x44 TSC_DATA 8 R - Non auto-increment address
Registers from 0x50 - 0x5F are accessible only if “PWM_OFF” bit in SYS_CTRL is set to “0”.
0x50
PWM_CLOCK_
DIV
8 R/W 0x00 PWM clock divider
0x51 PWM_CTRL1 8 R/W 0x00
6.1 Auto-increment/non auto-increment address
The STMPE812 supports auto-increment accesses on all, except for TSC data register
(0x44). While accessing auto-increment register location, consecutive read/write access
data from the consecutive registers. Note that for register accesses started on autoincremental addresses, the address 0x44 is skipped.
For example:
Write register address (0x40)
Read data (data of 0x40)
Read data (data of 0x41)
Read data (data of 0x42)
Read data (data of 0x43)
Read data (data of 0x45) <= 0x44 is skipped.
Master control of PWM
channel 1
16/51 Doc ID 17732 Rev 3
STMPE812 System and identification registers
7 System and identification registers
Table 7. System and identification registers map
Address Register name Bit Type Reset Function
0x00 - 01 CHIP_ID 16 R 0x0812 Device identification
0x02 ID_VER 8 R 0x10
0x03 SYS_CTRL 8 R/W 0x0F System control register
0x04 PORT_FUNCTION 8 R/W 0x00 Port function control register
0x06 - 07 SCRATCH_PAD 16 R/W 0x00
Revision number
0x10 for engineering sample
General purpose storage
register
SYS_CTRL System control register
76543 2 1 0
RESERVED SOFT_RESET TSC_EN RESERVED PWM_OFF GPIO_OFF TSC_OFF ADC_OFF
00001 1 1 1
Address: 0x03
Typ e: R/W
Reset: 0x0F
Description: System control register.
[7] RESERVED
[6] SOFT_RESET
Reset the 812 using serial communication
ALL REGISTER VALUES ARE RESETTED. State machines all back to POR states.
[5] TSC_EN
Write ‘1’ to enable operation of TSC. Write ‘0’ to disable it.
[4] RESERVED
[3] PWM_OFF
Writing ‘1’ switches OFF the clock supply to PWM
[2] GPIO_OFF
Writing ‘1’ switches OFF the clock supply to GPIO
[1] TSC_OFF
Writing ‘1’ switches OFF the clock supply to touchscreen controller
[0] ADC_OFF
Writing ‘1’ switches OFF the clock supply to ADC
If the clock supply to a particular functional block is turned off, the registers of these
modules are not accessible.
Doc ID 17732 Rev 3 17/51
System and identification registers STMPE812
PORT_FUNCTION Port function control register
76543 2 1 0
PORT 3 FUNCTION PORT 2 FUNCTION PORT 1 FUNCTION PORT 0 FUNCTION
00000 0 0 0
Address: 0x04
Typ e: R/W
Reset: 0x00
Description: Port function control register.
[7:6] PORT 3 FUNCTION
[5:4] PORT 2 FUNCTION
[3:2] PORT 1 FUNCTION
[1:0] PORT 0 FUNCTION
Port function:
'00' - GPIO input
'01' - GPIO output
'10' - ADC input (P0/P1 only)
'11' - Special function
Special function for:
P0 - NONE
P1 - PWM
P2 - RESET input (low pulse > 4
µs triggers a hard-reset)
P3 - INT output
SCRATCH_PAD Scratch pad register
76543 2 1 0
SCRATCHPAD
00000 0 0 0
Address: 0x06 - 07
Typ e: R/W
Reset: 0x00
Description: General purpose scratch pad register. Could be used for testing of serial interface
reliability.
[15:0] SCRATCHPAD
18/51 Doc ID 17732 Rev 3
STMPE812 Interrupt system
8 Interrupt system
The STMPE812 uses a 2-tier interrupt structure. In normal mode, interrupts from the GPIO
and touchscreen controller assert the INT pin and are available in the Interrupt Status
register (ISR).
In pen down mode, the INT pin is asserted as long as pen down is detected.
Since the INT pin is a OR function of the pen down and all other enabled interrupts, in order
for INT pin to provide the exclusive indication of pen down (INT=Low) and pen up
(INT=High), as such benefit from minimal I
down mode when the GPIO/PWM/ADC functions are not required or the GPIO/PWM/ADC
interrupts are disabled.
Figure 7. Interrupt system diagram
0%.$/7.-/$%
2
C transactions, it is recommended to use pen
4OUCHSCREENSTATUS
07-'0)/ACTIVITY
0%.$/7.
)NTERRUPT
STATUS
)
NTERRUPT
ENABLE
!.$
!.$
).4PIN
/2
!-6
Doc ID 17732 Rev 3 19/51
Interrupt system STMPE812
INT_CTRL Interrupt control register
76543 2 1 0
INT_MODE RESERVED INT_POLARITY INT_TYPE GLOBAL_INT
0 0 000
Address: 0x08
Typ e: R/W
Reset: 0x00
Description: This register is used to enable the interruption from a system related interrupt source
to the host.
[7] INT_MODE:
‘0’ for Pen-Down INT mode (INT pin asserted as long as pen down detected). Nothing can deassert the INT pin as long as PEN is down. TSC_TOUCH in INT_EN register must be enabled
for PEN_DOWN interrupt to operate.
If any other interrupt sources are enabled, the INT output is:
PEN_STATUS OR OTHER_INT
INT_E setting is not required for PEN-DOWN mode. It is recommended Pen-Down INT mode
enabled in applications where GPIO/ADC/PWM functions or interrupts are not in used, such
that the INT pin signal provides the exclusive indication for pen down and pen up.
‘1’ for normal INT mode (INT pin asserted if any bit in INT STATUS REGISTER is set)
When INT_MODE is changed, all interrupt status are cleared. Pending INT output (if any) is
cleared too.
[6:3] RESERVED
[2] INT_ POLARITY:
‘1’ for active high/rising edge
‘0’ for active low/falling edge
Interrupt pin should be pulled to V
if “active low” polarity is used, and pulled to GND if “active
CC
high” polarity is used.
[1] INT_TYPE:
‘1’ for edge interrupt (pulse width = 50-150 µs)
‘0’ for level interrupt
Edge interrupt does not work in PEN_DOWN INT mode
This bit is ignored in PEN_DOWN INT mode.
[0] GLOBAL_INT:
‘1’ allows global interrupt
‘0’ stops all interrupt
This bit overwrites INT_MODE: If global_int is stop (in pen down INT_MODE), even pen down
does not generate an interrupt.
20/51 Doc ID 17732 Rev 3
STMPE812 Interrupt system
INT_EN Interrupt enable register
7 6 543 2 1 0
TSC_ERR TSC_RELEASE P3 P2 P1 P0 TSC_DATA TSC_TOUCH
0 0 000 0 0 0
Address: 0x09
Typ e: R/W
Reset: 0x00
Description: This register is used to enable the interruption from a system related interrupt source
to the host.
[7] TSC_ERR
Error encountered in coordinate calculation in touchscreen controller
[6] TSC_RELEASE:
Release of TSC is detected
[5] P3
Port 3 activity (GPIO)
[4] P2
Port 2 activity (GPIO)
[3] P1
Port 1 activity (GPIO/ADC/PWM)
[2] P0
Port 0 activity (GPIO/ADC)
[1] TSC_DATA
Touch data available
[0] TSC_TOUCH
Touch is detected
Note: Hotkey interrupt should have respond time of <5 µs in active mode and less than 1 ms in
hibernate mode.
Doc ID 17732 Rev 3 21/51
Interrupt system STMPE812
ISR Interrupt status register
7 6 543 2 1 0
TSC_ERR TSC_RELEASE P3 P2 P1 P0 TSC_DATA TSC_TOUCH
0 0 000 0 0 0
Address: 0x0A
Type: R
Reset: 0x00
Description: ISR register monitors the status of the interruption from a particular interrupt source
to the host. Regardless whether the INT_EN bits are enabled, the ISR bits are still
updated.
Writing to this register has no effect. Reading the register clears any asserted bit
Implementation: A shadow register MUST be used to ensure that Read+Clear action
DOES NOT clear up any bit that is not READ.
Note: Reading the Interrupt Enable Register also clears the ISR. It is recommended that no read operation on IER
to be executed during normal operation. IER should only be accessed during initialization.
[7] TSC_ERR
Error encountered in coordinate calculation in TSC, or touch detect not valid after sampling
[6] TSC_RELEASE:
Release of touch is detected
[5] P3
Port 3 activity (GPIO)
[4] P2
Port 2 activity (GPIO)
[3] P1
Port 1 activity (GPIO/ADC/PWM)
[2] P0
Port 0 activity (GPIO/ADC)
[1] TSC_DATA
Touch data available. In internal timer and host-read controlled mode, this bit can only be
cleared after the data has been read by the host. In ACQ mode, this bit is cleared after the data
or the ISR is read by the host.
[0] TSC_TOUCH
Touch is detected.
(In PEN-DOWN interrupt mode, this bit is never cleared until pen is removed)
In PEN_DOWN interrupt mode, this status register is still updated with event interrupt status
data, and cleared on read. However no interrupt is issued based on this status register.
22/51 Doc ID 17732 Rev 3
STMPE812 ADC controller
9 ADC controller
A 12-bit ADC is integrated in the STMPE812. The ADC could be used as generic analogdigital converter, or a touchscreen controller capable of controlling a 4-wire resistive
touchscreen.
The ADC works ONLY with internal reference (equal to V
Table 8. ADC controller register
Address Register name Bit Type Reset Description
0x20 ADC control 8 R/W 0x32 ADC control
0x21-0x22 ADC data 16 R 0x0000 ADC data access (P0/P1)
), always 12 bit.
CC
Doc ID 17732 Rev 3 23/51
ADC controller STMPE812
ADC control register ADC control
76543 2 1 0
ADC_MODE ADC_CAP ADC_FREQ CP_ARM CP_Lock[1:0] ADC_PORT
00110 0 1 0
Address: 0x20
Type: R/W
Reset: 0x32
Description: This register is used to configure the ADC operations.
[7] ADC_MODE: ADC capture mode
‘0’ – Continuous capture according to sampling rate specified by ADC_FREQ register. New
data over-writes old data in ADC_DATA register.
‘1’ – One-shot capture. One sample is taken every time system writes ‘1’ to ADC_CAP bit
[6] ADC_CAP: ADC channel data capture
In one-shot mode:
Write ‘1’ to initiate data acquisition for the corresponding channel. Writing ‘0’ has no effect.
Reads ‘1’ if conversion is in progress.Reads ‘0’ if conversion is completed.
One-shot mode ADC generates interrupt in corresponding interrupt status bit on completion of
conversion
In continuous capture mode:
Write ‘1’ to initiate data acquisition for the corresponding channel. Writing ‘0’ to stop capturing.
[5:4] ADC_FREQ: ADC sampling frequency based on 1MHz RC (minimum 880 KHz)
00 – 10 K samples/sec
01 – 12.5 K samples/sec
10 – 15 K samples/sec
11 – 20 K samples/sec
NOTE: As the ADC is also used for TSC operation. This setting affects the maximum sampling
rate possible with TSC.
[3] CP_Arm: Writing ‘1’ arms the charge-pump for unlocking
Writing ‘0’ un-arms it
Charge-pump is required for ADC/TSC operation when Vcc is less than 2.5V. Activating the
charge pump when Vcc is more than 2.5V may result in permanent damage of the
device.
Charge-pump can be activated by unlocking CP_Lock after it is armed.
[2:1] CP_Lock[1:0]: Only effective if CP_Arm is set to ‘1’.
Always reads ‘00’.
Writing ‘01’ when CP_Arm is ‘1’ activates the charge pump.
Writing ‘00’, ‘10’ and ‘11’ does NOT activate the charge-pump, and clears the CP_Arm bit.
CP_Arm MUST BE set before writing to CP_Lock. Accesses to CP_Lock is ignored, if CP_Arm
is ‘0’.
Note: NOTE: CP_Arm and CP_Lock CANNOT be accessed in a single I
System must first ARM the CP with 1 I
2
C transaction, and unlocks it in the next.
CP_LOCK reads “00” if charge pump is activated
CP_LOCK reads “01” if charge pump is not activated
2
C transaction.
24/51 Doc ID 17732 Rev 3
STMPE812 ADC controller
[0] ADC_PORT: selects one of the port as ADC input.
00- Port 0
01- Port 1
ADC data ADC data register
76543 2 1 0
ADC_DATA_7 ADC_DATA_6 ADC_DATA_5 ADC_DATA_4 ADC_DATA_3 ADC_DATA_2 ADC_DATA_1 ADC_DATA_0
00000 0 0 0
Address: 0x21-0x22
Type: R
Reset: 0x0000
Address: ADC data register.
[7:0] ADC_DATAx
Note: When the I
guaranteed (Once access starts, content is updated only after BOTH bytes has been read,
2
OR I
C master accesses other register address):
- 0x21 is LSB
- 0x22 is MSB
2
C master accesses the data register, upper/lower byte consistency must be
Doc ID 17732 Rev 3 25/51
PWM controller STMPE812
10 PWM controller
The PWM allows the brightness control of a LED/motor driver.
The PWM uses base clock that is ½ of the OSC frequency (typically 600 kHz). The base
clock is divided by a programmable DIV[4:0], which scales it to 18.75-600 kHz. This clock
goes into PWM controller and outputs a signal that is pulse-width modulated (16 steps), with
a frequency 16 times smaller.
10.1 Register map for PWM function
Table 9. PWM function registers
Address Register name Bit Type Reset Description
0x50 PWM_ClockDiv 8 R/W 0x00 PWM clock divider
0x51 PWM_Control_1 8 R/W 0x00
Master control of PWM channel 1
Output at port 0
PWM clock div register PWM clock divider register
76543 2 1 0
BurstLength [1:0] DIV[4:0]
00000 0 0 0
Address: 0x50
Type: R/W
Reset: 0x00
Description: PWM clock divider register.
[7:5] BurstLength[2:0]
Burst length of PWM output
‘000’ – 8 ms
‘001’ – 16 ms
‘010’ – 32 ms
‘011’ – 64 ms
‘100’ – 128 ms
‘101’ – 256 ms
‘110’ – 512 ms
‘111’ – 1024 ms
[4:0] Div[4:0]
PWM controller is based on 600 kHz clock divided by (Div[4:0] + 1).
Effectively, PWM clock is:
600 kKz (msx.)
600 kHz/32 = 18.75 kHz (min.)
26/51 Doc ID 17732 Rev 3
STMPE812 PWM controller
PWM control1 register PWM control1 register
76543 2 1 0
Brightness BurstMultiplier Off_State Enable
0000
Address: 0x51
Type: R/W
Reset: 0x00
Description: PWM control1 register.
[7:4] This defines the of the PWM channel output which in turn determines the brightness level of
the LED that the PWM output drives. Note that this is assuming LED is connected in SINKING
MODE. System host should program the brightness in a reverse way if sourcing configuration
were to be used.
0000: duty cycle ratio 1:15 (6.25%, minimum brightness)
0001: duty cycle ratio 2:14 (12.50%)
0010: duty cycle ratio 3:13 (18.75%)
0011: duty cycle ratio 4:12 (25.00%)
0100: duty cycle ratio 5:11 (31.25%)
0101: duty cycle ratio 6:10 (37.50%)
0110: duty cycle ratio 7: 9 (43.75%)
0111: duty cycle ratio 8: 8 (50.00%)
1000: duty cycle ratio 9: 7 (56.25%)
1001: duty cycle ratio 10: 6 (62.50%)
1010: duty cycle ratio 11: 5 (68.75%)
1011: duty cycle ratio 12: 4 (75.00%)
1100: duty cycle ratio 13: 3 (81.25%)
1101: duty cycle ratio 14: 2 (87.50%)
1110: duty cycle ratio 15: 1 (93.75%)
1111: duty cycle ratio 16: 0 (100.00%, maximum brightness)
[3:2] BurstMultiplier
PWM output continues for time = BurstLength * BurstMultiplier
*If BurstMultiplier = 0, PWM output indefinitely (until PWM is turned OFF)
1 Off_State
‘0’: PWM Output “HI” when PWM not running
‘1’: PWM Output “LOW” when PWM not running
0Enable
Writing ‘1’ to this bit starts the PWM controller sequence
Writing ‘0’ has stops it
Reads ‘1’ when PWM is running.
Doc ID 17732 Rev 3 27/51
PWM controller STMPE812
10.2 Interrupt of PWM controller
When non-infinite sequence is used, the completion of PWM sequence causes the P0 bit in
interrupt status register to be asserted.
28/51 Doc ID 17732 Rev 3
STMPE812 Touchscreen controller
11 Touchscreen controller
The STMPE812 is integrated with a hard-wired touchscreen controller for 4-wire resistive
type touchscreen. The touchscreen controller is able to operate completely autonomously,
and would interrupt the connected CPU only when pre-defined event occurs.
The TSC is based on an internal 20Ksamples/sec ADC, running off a 1 MHz (Minimum
880 kHz) RC OSC.
Sampling time = Touch Detect Delay*2 + (Settling Time + (ADC Conversion Time*MAV)) *3
Table 10. Sampling time/frequency calculation
ADC
Oscillator speed
conversion
time
880kHz 50µs 40µs 40µs None
Touch
detect
delay
Settling
time
Median
averag
e
(complete X/Y/Z sample
40*2 + 3*(40+(50*1)) = 350 µs
(2.8K sample sets/sec)
40*2 + 3*(40+
880kHz 50µs 40µs 40µs 10-2
(50*10))=1700 µs (588 sample
sets/sec)
640*2 + 3*(640+ (50*20))
880 kHz 50 µs 640 µs 640 µs 20-4
=6200 µs (161 sample
sets/sec)
Figure 8. Touchscreen controller internal RC OSC connection
-(Z
MINIMUM+
2#/3#
BITCH!$#
MAX
+SAMPLESSAT-(Z
Sampling time/freq
sets)
43#TIMINGGENERATOR
43#SAMPLINGRATE
MSMS
!-6
Doc ID 17732 Rev 3 29/51
Touchscreen controller STMPE812
11.1 Touchscreen controller detection sequence
Following is the sequence of detection in the STMPE812 touchscreen controller for X, Y and
Z:
1. Touch Detect
2. Drive Y
3. Wait for settling time
4. Measure Y
5. Stop drive
6. Drive Z
7. Wait for settling time
8. Measure Z
9. Stop drive
10. Drive X
11. Wait for settling time
12. Measure X
13. Stop drive
14. Touch Detect
11.2 3 modes of acquisition
1. Data acquisition timed by internal timer:
The host system selects a “sampling period” with, based on internal timer, the touchscreen
controller takes a complete set of samples on every period. The host system may choose to
read the data by:
– Waiting for the INT
– Polling for INT_STATUS register for TOUCH DATA
– Reading the TSC_DATA at approximately the same timing. (Use “Data Valid Status
Read” option in this mode)
2. Data acquisition triggered by a write to “ACQ” bit:
As and when sampling is desired, host writes to the ACQ bit and:
– Poll the ACQ to wait for completion
– Wait for INT for Touch Data access
– Poll the FIFO after approximate time required for sampling. (Use “Data Valid
Status Read” option in this mode)
3. Data acquisition using host-controlled sampling rate control
The host sets the internal timer for the desired data-rate. On staring the touchscreen
controller in this mode, a complete set of sample is taken immediately. The touchscreen
controller enters in hibernate mode (clock is turned OFF, only monitors the PEN-DOWN
status). When system host reads the Touch Data available in FIFO, another set of data is
taken immediately.
30/51 Doc ID 17732 Rev 3
STMPE812 Touchscreen controller
11.3 Touchscreen controller registers
Table 11. Touchscreen controller registers
Address Register name Bit Type Reset Function
0x40 TSC_CTRL 8 R/W 0x00 Touchscreen control
0x41 TSC_DET_CFG1 8 R/W 0xA4 Touchscreen detection config 1
0x42 TSC_DET_CFG2 8 R/W 0xB0 Touchscreen detection config 2
0x43
0x44 TSC_DATA 8 R – Touchscreen data
TSC_SAMPLING
_RATE
8 R/W 0x0A Touchscreen sampling rate
Doc ID 17732 Rev 3 31/51
Touchscreen controller STMPE812
TSC CTRL TSC control register
76543 2 1 0
MAV_MODE[2:0] ACQ Precharge[1:0] Current Limit [1:0]
000 0
Address: 0x40
Type: R/W
Reset: 0x00
Description: Touchscreen control register.
[7:5] MAV_MODE[2:0]
‘000’ – MAV Filter Disabled
‘001’ – 6 remove 2
‘010’ – 8 remove 4
‘011’ – 10 remove 2
‘100’ – 12 remove 4
‘101’ – 20 remove 4
‘110’ – 4 remove none (Equal to 4x oversampling)
‘111’ – 8 remove none (Equal to 8x oversampling)
[4] ACQ
Only valid in acquisition mode ‘01’ (acquisition initiated by system host writing to ACQ bit)
Writing ‘1’ to this bit initiates a TSC data acquisition
Writing ‘0’ has no effect
Reads ‘1’ if data acquisition is in progress
Reads ‘0’ if data is ready
If Data is already available in buffer and not read by system host, setting this bit to ‘1’ renders
the data in buffer “invalid”. DATA available bit in Interrupt Status register is reset by hardware
automatically. Pending interrupt due to DATA available (if any) is cleared.
Data pointer in multi-byte read operation is reset when this bit is written to.
[3:2] Precharge[1:0]
Pre-charge driver for touch detection
‘00’ – no pre-charge
‘01’ – 2 µs pre-charge
‘10’ – 4 µs pre-charge
‘11’ – 8 µs pre-charge
[1:0] Current Limit [1:0]
Current limit of touchscreen driver
‘00’ – 5 mA
‘01’ – 10 mA
‘10’ – 20 mA
‘11’ – 30 mA
32/51 Doc ID 17732 Rev 3
STMPE812 Touchscreen controller
TSC detect config TSC detection configuration 1 register
76543 2 1 0
PenStrength[1:0] TDetDly[2:0] Settling[2:0]
10100 1 0 0
Address: 0x41
Type: R/W
Reset: 0xA4
Description: Touchscreen controller detection configuration 1 register.
[7:6] PenStrength[1:0]
Pen detect strength threshold
‘00’ – least sensitive (50 K pull-up)
‘01’ – sensitive (40 K pull-up)
‘10’ – more sensitive (30 K pull-up) - Default
‘11’ – most sensitive (20 K pull-up)
[5:3] TDetDly[2:0]
Touch detect delay
‘000’ = 40 µs
‘001’ = 80 µs
‘010’ = 160 µs
‘011’ = 320 µs
‘100’ = 640 µs - Default
‘101’ = 1.28 ms
‘110’ = 2.56 ms
‘111’ = 5.12 ms
[2:0] Settling[2:0]
Panel driver settling time
‘000’ = 40 µs
‘001’ = 80 µs
‘010’ = 160 µs
‘011’ = 320 µs/ns
‘100’ = 640 µs - Default
‘101’ = 1.28 ms
‘110’ = 2.56 ms
‘111’ = 5.12 ms
For large panels (> 6 inches), a capacitor of 10 nF is recommended at the touchscreen
terminals for noise filtering. In this case, settling time of 1 ms or more is recommended.
Doc ID 17732 Rev 3 33/51
Touchscreen controller STMPE812
TSC_DET_CFG2 TSC detection configuration 2 register
76543 2 1 0
Acq_Mode StatusRead OpMode Z-Divider[3:0]
10110 0 0 0
Address: 0x42
Type: R/W
Reset: 0xB0
Description: Touchscreen controller detection configuration 2 register.
[7:6] Acq_Mode
‘00’ – Data acquisition timed by internal timer
‘01’ – Data acquisition triggered by a write to “ACQ” bit
‘10’ – Data acquisition using Host-Controlled Sampling Rate Control. (Default)
‘11’ – Reserved
In mode ‘10’, device sample a complete data set every time host accesses the buffer. After
completion of sampling, device enters hibernate mode, until data is accessed again. (Or PENUP causing interrupt to de-assert)
[5] StatusRead
‘1’ will insert data valid (data available) status read in data port.
Reading data port in this mode will clear the ISR register
‘0’ – no data valid (data available) status access by data port
[4] OpMode
TSC operating mode
‘0’ for 12-bit X,12-bit Y,8-bit Z acquisition
‘1’ for 12-bit X, 12-bit Y only (Default)
This field cannot be written on, when EN=1
[3:0] Z-Divider[3:0]
Pen-Pressure is internally calculated as a 16-bit integer. As 16-bit resolution is typically not
required for touchscreen operation, STMPE812 right-shifts the value internally by ZDivider[3:0].
Z-value read through the TSC Data register is the lowest 8-bit of the shifted value.
34/51 Doc ID 17732 Rev 3
STMPE812 Touchscreen controller
TSC sampling rate TSC sampling rate register
76543 2 1 0
SAMPLING
00001 0 1 0
Address: 0x43
Type: R/W
Reset: 0x0A
Description: Touchscreen controller sampling rate control register.
[7:0] Sampling[7:0]
Sets the sampling rate of touchscreen controller.
Sampling Time = (sampling[7:0]+1) in ms
Clock cycle = 1 µs (1 MHz RC OSC)
Sampling time = 1 ms – 256 ms
NOTE:
This is used as “TSC regular initiator signal’. As long as there remains a valid touch, every
interval of this timing, the touchscreen controller executes a complete drive/settling/multisample/MAV/data calculation. It is the user’s responsibility to choose a sampling time that is
enough, based on ADC_FREQ, settling time and filter.
TSC_data Touchscreen data register
76543 2 1 0
TSC_DATA_7 TSC_DATA_6 TSC_DATA_5 TSC_DATA_4 TSC_DATA_3 TSC_DATA_2 TSC_DATA_1 TSC_DATA_0
00000 0 0 0
Address: 0x42
Type: R/W
Reset: 0xB0
Description: The data format of the touchscreen controller data register depends on the setting of
“OpMode” field in the touchscreen detection configuration 2 register. The samples
acquired are accessed in “packed samples”. The size of each “packed sample”
depends on which mode the touchscreen controller is operating in.
[7:0] TSC_DATA_x: Data byte from touchscreen controller.
Note: In order to preserve the integrity of the data, it is mandatory to ensure the following:
- System host to read exactly the number of bytes according to the programmed operating
mode
- I2C host to insert a STOP condition after each data read command
Data pointer in this 1-level buffer could be reset by:
-User issued ACQ in user initiated acquisition mode. In mode ‘10’, every time sampling is
completed, it will overwrite the buffer, and reset the data pointer
Doc ID 17732 Rev 3 35/51
Touchscreen controller STMPE812
Table 12. Touchscreen controller data register
TSCDetectConfig2
OpMode StatusRead
0 0 4 [11:4] of X
1 0 3 [11:4] of X
01 5
11 4
Number of
bytes to
read from
TSCData
Byte0 Byte1 Byte2 Byte3 Byte4
Data Valid
Status
Data Valid
Status
[3:0] of X
[11:8] of Y
[3:0] of X
[11:8] of Y
[11:4] of X
[11:4] of X
[7:0] of Y [7:0] of Z
[7:0] of Y -
[3:0] of X
[11:8] of Y
[3:0] of X
[11:8] of Y
[7:0] of Y [7:0] of Z
[7:0] of Y -
Table 13. Data valid status byte structure
76543210
RESERVED DATA VALID RESERVED
[7:2]Bit[0]: Reserved
“1’ Touch data available/ valid
[1]
‘0’ Touch data not available/ not valid
Bit reset upon read.
Data Valid Status Read in data port is useful together with Pen Down mode whereby
accessing the ISR is not needed so as to achieve the best I
minimal I
2
C transactions).
Note: Reading the Data valid Status byte also clears the ISR.
2
C bandwidth efficiency (i.e.
36/51 Doc ID 17732 Rev 3
STMPE812 Touchscreen controller
11.4 Programming model
Below are steps to configure the Touchscreen controller in 3 different acquisition modes.
A. Autonomous touchscreen controller, 100 Hz, lowest power possible
1. Initialize the touchscreen controller (choose ACQ_Mode ‘00’ - data acquisition timed by
internal timer)
2. Initialize Interrupt (With TSC_Data enabled, normal interrupt mode)
3. Wait for Interrupt
4. On interrupt: Read interrupt status (this clears the set bits too)
5. If data is available, read data.
Note: If one set of data is available in buffer, and not accessed by the I
timer is up for the next data, the STMPE812 samples the next data as scheduled.
If old data is still NOT accessed when new data is ready to be written to the buffer, it is overwritten.
If old data is IN PROGRESS of being accessed, new data is DISCARDED.
2
If I
C host accessed PART OF the data, and moved on to read ANY OTHER REGISTER
LOCATION, the existing data is CONSIDERED READ, and new data ready to be written into
buffer
B. Non-autonomous touchscreen controller style-interrupt, 100Hz, lowest
power possible:
1. Initialize TSC (Choose ACQ_Mode ‘01’ - Data acquisition triggered by a write to “ACQ”
bit)
2. Initialize Interrupt (With TSC_Data, TSC_Touch enabled, PEN_DOWN interrupt mode)
3. Wait for Interrupt
4. On Interrupt: Read Interrupt Status (this clears the set bits too)
5. If PEN_DOWN, start SYSTEM_TIMER (10 ms typically)
6. On TIMEOUT, write ACQ bit to start acquisition
7. Poll interrupt status register or ACQ bit to check for acquisition status
8. ON issuing ACQ, 812 may assume that data in buffer is already accessed by I2C host,
and reset the relevant pointers.
2
C host, yet the sampling
C. Host-controlled sampling rate (lowest bus utilization)
1. Initialize TSC (choose ACQ_Mode ‘10’ - Data acquisition using host-controlled
sampling rate control)
2. Initialize interrupt (with TSC_Data, TSC_Touch enabled, PEN_DOWN interrupt mode)
3. Wait for Interrupt
4. On interrupt: Read Interrupt Status (this clears the set bits too)
5. If PEN_DOWN, start SYSTEM_TIMER (10 ms typically)
6. On TIMEOUT, read data
Doc ID 17732 Rev 3 37/51
Touchscreen controller STMPE812
The STMPE812 samples a new data set immediately after every complete read.
If the host does not complete a data-set read, no further samples are taken.
For each data point (4 bytes), number of I2C transaction required is:
A: Read “Data valid status”(1 byte), read data (4 bytes)
B: Write ACQ (1 byte), read ACQ (1 byte), read data (4 bytes)
C: Read (4 bytes)
38/51 Doc ID 17732 Rev 3
STMPE812 GPIO port controller
12 GPIO port controller
A total of 4/6 configurable ports are available in the STMPE812 port expander device.
If configured as GPIO input/output, they are controlled by the GPIO registers.
Table 14. GPIO registers
Address Register Bit Type Reset Function
0x10 GPIO_SET_PIN 8 R/W 0x00 Set pin state
0x11 GPIO_CLR_PIN 8 R/W 0x00 Clear pin state
0x12 GPIO_MP_STA 8 R/W 0x00 Monitor pin state
0x13 GPIO_DIR 8 R/W 0x00
0x14 GPIO_ED 8 R/W 0x00
All GPIO registers are named as GPxx, where:
Xxx represents the functional group
Falling edge
detection enable
Rising edge
detection enable
Bit 76543210
GPxx IO-3 IO-2 IO-1 IO-0
The function of each bit is shown in Tab l e 1 5:
Table 15. GPIO registers
Register name Function
GPIO monitor pin state Reading this bit yields the current state of the bit. Writing has no effect.
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘1’ state.
GPIO set pin state
GPIO clear pin state
GPIO falling edge detection
enable
GPIO rising edge detection
enable
Writing ‘0’ to this bit has no effect
Reading this register always yield 0x00
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘0’ state.
Writing ‘0’ to this bit has no effect
Reading this register always yield 0x00
Writing ‘1’ to this bit allows interrupt generation when there is a falling
edge at the corresponding GPIO
Writing ‘0’ disables the interrupt generation on falling edge detection
Writing ‘1’ to this bit allows interrupt generation when there is a rising
edge at the corresponding GPIO
Writing ‘0’ disables the interrupt generation on rising edge detection
If both GPFE and GPRE are not set, state transition on a GPIO does not cause an interrupt.
On power-up reset, all GPIO are set as input.
Doc ID 17732 Rev 3 39/51
Electrical specification STMPE812
13 Electrical specification
Table 16. Absolute maximum rating
Symbol Ratings Maximum value Unit
V
CC
Supply voltage 4.5 V
Vi-i2c Input voltage at SDA/SCL 4.5 V
Vi-io Input voltage at P0-P5 4.5 V
On all touchscreen and GPIO pins (HBM) ±8 kV
ESD
On all other pins (HBM) ±2 kV
Table 17. Thermal data
Symbol Parameter Value Unit
T
J
T Operating temperature -40°C-85°C °C
T
STG
Table 18. Power consumption (T
Symbol Parameter Test conditions Min Typ Max Unit
V
CC
ICC max Operating current
max Operating current
I
CC
Thermal resistance junction-ambient
(Flip-chip12)
68 °C / W
Storage temperature -65°C-125°C °C
= -40 °C to 85 °C)
amb
Core supply voltage 1.65 – 3.6 V
V
=1.8V
CC
TSC running at 100 sets
of X/Y per second
– 100 120
MAV disabled
Vcc=1.8V
TSC Running at 100 sets
of X/Y per second
– 230 280
MAV 6 remove 2
V
=3.3V
CC
TSC running at 100 sets
of X/Y/Z per second
– 670 810
MAV 10 remove 2
Vcc=1.8 V
TSC running at 100 sets
of X/Y/Z per second
– 470 570
MAV 10 remove 2
µA
µA
40/51 Doc ID 17732 Rev 3
STMPE812 Electrical specification
Table 18. Power consumption (T
amb
Symbol Parameter Test conditions Min Typ Max Unit
VCC=1.8V
ICC max Operating current
TSC running at 100 sets
of X/Y/Z per second
MAV 20 remove 4
VCC=3.3V
I
max Operating current
CC
TSC running at 100 sets
of X/Y/Z per second
MAV 20 remove 4
I
CC
suspend
Suspend current
No I2C/ADC activity
V
CC
*operating current excludes current driving the touchscreen.
13.1 DC electrical characteristics
(-40 °C to 85 °C. All GPIO complies to JEDEC standard JESD-8-7)
Table 19. DC electrical characteristics
= -40 °C to 85 °C) (continued)
– 870 1050 µA
– 1190 1430 µA
= 1.8 V - 3.3 V
–0.5 1µA
Symbol Parameter Test conditions Min Typ Max Unit
V
V
V
V
OH
Input voltage low state VCC= 1.65 - 3.3 V -0.3 –
IL
IH
OL
Input voltage high
Output voltage low
Output voltage high
state
state
state
= 1.65 - 3.3 V 0.80 V
V
CC
V
CC
IOL=12mA
V
CC
IOH=8 mA
All input pins except for
I
leakage
touchscreen I/O and
= 1.65 V, VIN3.6 V – 0.1 0.5 µA
V
CC
P0/P1
13.2 AC electrical characteristics
Table 20. AC electrical characteristics (-40 °C to 85 °C)
Symbol Parameter Test conditions Min Typ Max Unit
Max
ClkI2C
MaxClkI2
C
I2C maximum SCLK V
I2C maximum SCLK V
CC
CC
0.20 V
C
V
=3.3V,
=1.65 V,
CC
-0.3 –
0.85 V
CC
C
–VCC+0.3 V
0.45 V
–VCC+0.3 V
=1.8-3.3V – – 400 KHz
= 1.8 - 3.3 V – – 120 KHz
Doc ID 17732 Rev 3 41/51
Electrical specification STMPE812
Table 20. AC electrical characteristics (-40 °C to 85 °C)
Symbol Parameter Test conditions Min Typ Max Unit
Tr e se t
Minimum RESET pulse
width
4– –µs
Minimum INPUT width
Tin
required for GPIO state
4– –µs
transition
F
osc
F
osc
Table 21. ADC specification
Internal RC OSC
frequency
Internal RC OSC
frequency
V
= 1.8 V 900 1200 1500 kHz
CC
= 3.3 V 900 1200 1500 kHz
V
CC
Parameter Test conditions Min Typ Max Unit
Full-scale input span 0 – V
Absolute input range -0.2 –
CC
+0.
V
CC
2
Input capacitance – 25 – pF
Leakage current – 0.1 – µA
Resolution – 12 – Bits
No missing codes 11 – – Bits
Integral linearity error – ±4 – LSB
Offset error – ±5 ±5 LSB
V
V
Gain error – ±14 ±18 LSB
Noise
Including internal
Vref
–50– uVrms
Power supply rejection ratio – 50 – dB
Throughput rate – 180 – Ksamples/s
Table 22. Switch drivers specification
Parameter Test conditions Min Typ Max Unit
=1.65-
V
ON resistance X+, Y+
ON resistance X-, Y-
Drive current (at 5 mA limit)
CC
3.6 V
V
=1.65-
CC
3.6 V
= 1.65 -3.6 V
V
CC
X+/X- or Y+/Yshorted together
externally
–7 15OHM
–7 15OHM
–– 10mA
42/51 Doc ID 17732 Rev 3
STMPE812 Electrical specification
Table 22. Switch drivers specification (continued)
Parameter Test conditions Min Typ Max Unit
VCC=1.65 -3.6 V
Drive current (at 10 mA
limit)
Drive current (at 20 mA
limit)
Drive current (at 30 mA
limit)
X+/X- or Y+/Y-
shorted together
externally
=1.65 -3.6 V
V
CC
X+/X- or Y+/Y-
shorted together
externally
=1.65 -3.6V
V
CC
X+/X- or Y+/Y-
shorted together
externally
–– 20mA
–– 40mA
–– 60mA
Doc ID 17732 Rev 3 43/51
Package mechanical section STMPE812
14 Package mechanical section
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
Figure 9. Package outline for Flip-chip CSP 12
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
44/51 Doc ID 17732 Rev 3
STMPE812 Package mechanical section
Table 23. Flip-chip CSP 12 mechanical data
Symbol
Millimeters
Min Typ Max
A 0.585 0.650 0.715
A1 0.21 0.25 0.29
A2–0.35–
b 0.265 0.315 0.365
D 2.122.172.22
D1 – 1.5 –
E 1.621.671.72
E1 – 1.0 –
e0.450.50.55
fD – 0.335 –
fE – 0.335 –
SD–0.25–
ccc – 0.08 –
$ – 0.05 –
Figure 10. Footprint recommendation
Doc ID 17732 Rev 3 45/51
Package mechanical section STMPE812
Figure 11. Tape information
Table 24. Tape specifications
Symbol
Min Typ Max
Ao 1.78 1.83 1.88
Bo 2.34 2.29 2.34
Millimeters
Ko 0.68 0.73 0.78
F 3.453.503.55
E 1.651.751.85
W7.908.008.30
P2 1.95 2.00 2.05
Po 3.90 4.00 4.10
10Po 39.80 40.00 40.20
Do 1.50 1.55 1.60
T 0.185 0.200 0.215
P 3.904.004.10
46/51 Doc ID 17732 Rev 3
STMPE812 Package mechanical section
Figure 12. Tape orientation
User direction of feed
AM00745V1
1. Pin A1 is at the top left corner based on above tape orientation.
Figure 13. Device marking
)DENTIFICATIONFOR
DEVICEFRONTEND
ANDBACKENDPLANT
6,6
977
'
)DENTIFICATIONFOR
(ALOGENFREE
)DENTIFICATIONFOR
TRACEABLEDATECODE
!-6
Doc ID 17732 Rev 3 47/51
Package mechanical section STMPE812
Figure 14. Reel drawing (front)
Figure 15. Reel drawing (back)
48/51 Doc ID 17732 Rev 3
STMPE812 Package mechanical section
Table 25. Tape width (millimeters)
A N W1 W2 W3
Tape width
max min max max min max
8 180 60 8,4 14.4 7.9 10.9
Doc ID 17732 Rev 3 49/51
Revision history STMPE812
15 Revision history
Table 26. Document revision history
Date Revision Changes
20-Jul-2010 1 Initial release.
Modified: Title. Package silhouette and name , Figure 11: Tape
information, Figure 14: Reel drawing (front), Section 10.1: Register
map for PWM function,Section 11.3: Touchscreen controller registers
16-Nov-2010 2
25-Feb-2011 3 Document status promoted from preliminary data to datasheet.
and Figure 14: Reel drawing (front).
Added: Figure 1: Pin A1 is at the top left corner based on above tape
orientation., Table 24: Tape specifications and Table 25: Tape width
(millimeters)
50/51 Doc ID 17732 Rev 3
STMPE812
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