ST STMPE2403 User Manual

STMPE2403

24-bit Enhanced port expander with Keypad and PWM controller

Xpander logic

Features

■ 24 GPIOs

■ Operating voltage 1.8V

■ Hardware key pad controller (8*12 matrix ma x)

■ 8 Special Function Key support

■ 3 PWM (8 bit) output for LED brightness control

and blinking

■ Interrupt output (open drain) pin

■ Configurable hotkey feature on each GPIO

■ Ul tr a-l ow St an db y- mo de cu rr ent

■ Package TFBGA - 36 pins 3.6x3.6mm, pitch

0.5mm

Description

TFBGA

The STMPE2403 is a GPIO (General Purpose
Input / Output) port expander able to interface a
Main Digital ASIC via the two-line bidirectional

2

bus (I

C); separate GPIO Expander IC is often
used in Mobile-Multimedia platforms to solve the
problems of the limited amounts of GPIOs usually
available on the Digital Engine.

The STMPE2403 offers great flexibility as each
I/Os is configurable as input, output or specific
functions; it's able to scan a keyboard, also
provides PWM outputs for brightness control in
backlight, rotator decoder interface and GPIO.
This device has been designed very low
quiescent current, and is including a wake up
feature for each I/O, to optimize the power
consumption of the IC.

Potential application of the STMPE2403 includes
portable media player, game console, mobile
phone, smart phone

Table 1. Device summary

Part Number Package Packaging

STMPE2403TBR TFBGA36 Tape and reel

June 2007 Rev 1 1/63

www.st.com

63

Contents STMPE2403

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 GPIO Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Pin mapping to TFBGA ( bottom view, balls up) . . . . . . . . . . . . . . . . . . . . . 9

3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 I/O DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.5 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.7 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.8 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/63

STMPE2403 Contents

7 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 System control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5 Autosleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.6 Keypress detect in the hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 Power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.1 Register map of interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3 Interrupt Enable Mask Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.4 Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.5 Interrupt Enable GPIO Mask Register (IEGPIOR) . . . . . . . . . . . . . . . . . . 29

9.6 Interrupt Status GPIO Register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . 30

9.7 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.1 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2 GPIO Alternate Function Register (GPAFR) . . . . . . . . . . . . . . . . . . . . . . 35

10.3 Hot key feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.1 Programming sequence for Hot Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.3.2 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.4 MUX Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.5 STMPE2401 Pin Compatibility Register (COMPAT2401) . . . . . . . . . . . . . 39

3/63

Contents STMPE2403

11 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.1 Registers in the PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.2 PWM Control and Status Register (PWMCS) . . . . . . . . . . . . . . . . . . . . . 42

11.3 PWM Instruction Channel x (PWMICx) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

11.4 PWM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.1 Keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12.2 Registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12.3 KPC_col register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12.4 KPC_row_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12.5 KPC_row_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.6 KPC_ctrl_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.7 KPC_ctrl_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.8 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.8.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.8.2 Using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.8.3 Ghost Key Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.8.4 Priority of Key detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

12.8.5 Keypad Wake-Up from sleep and hibernate modes . . . . . . . . . . . . . . . 55

13 Rotator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

14.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

14.2 Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

14.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

14.4 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4/63

STMPE2403 Block diagram

1 Block diagram

Figure 1. Block diagram

Keypad

Keypad

INT

INT

Keypad

Controller

Controller

Controller

GPIO

GPIO

GPIO

0-7

0-7

0-7

Main FSM

Main FSM

Main FSM

+ PWM

+ PWM

+ PWM
+ Rotator Control

+ Rotator Control

+ Rotator Control
+ GPIO Control

+ GPIO Control

+ GPIO Control

Keypad

Keypad

Keypad

Inputs

Inputs

Inputs

Keypad

Keypad

Keypad

Outputs

Outputs

Outputs

Function

Function

Function
Select

Select

Select

Function

Function

Function
Select

Select

Select
&

&

&
MUX 1, 2

MUX 1, 2

MUX 1, 2
Control

Control

Control

Keypad Input 0-7 /

Keypad Input 0-7 /

Keypad Input 0-7 /
GPIO 0-7

GPIO 0-7

GPIO 0-7

Keypad Output 0-11

Keypad Output 0-11

Keypad Output 0-11
/ GPIO 8-14, 16-20

/ GPIO 8-14, 16-20

/ GPIO 8-14, 16-20
/ Digital MUX 1, 2

/ Digital MUX 1, 2

/ Digital MUX 1, 2
/ Rotator

/ Rotator

/ Rotator

SCLK

SCLK

SDAT

SDAT

I2C

I2C

I2C

Interface

Interface

Interface

A0

A0

A0

A1

A1

A1

GPIO

GPIO

GPIO

15

15

15

PWM

PWM

PWM

O/P

O/P

O/P

POR

POR

POR

RC OSC

RC OSC

RC OSC

Clock

Clock

Clock

Controller

Controller

Controller

XTAL2OUTXTAL1INGND

XTAL2OUTXTAL1INGND

XTAL2OUTXTAL1INGND

GPIO 15

GPIO 15

GPIO 15
ADDR0

ADDR0

ADDR0
Trigger I/O

Trigger I/O

Trigger I/O

PWM1,2,3

PWM1,2,3

PWM1,2,3
/ ADDR1

/ ADDR1

/ ADDR1
/ GPIO 21-23

/ GPIO 21-23

/ GPIO 21-23

Reset_N

Reset_N

Reset_N

VCC1

VCC1

VCC1

VCC2

VCC2

VCC2

5/63

Pin settings STMPE2403

2 Pin settings

2.1 Pin connection

Figure 2. Pin connection

TFBGA

2.2 Pin assignment and TFBGA ball location

Table 2. Pin assignment

Ball Name Type Description

C3 GND1 -

A6 KP_X0 IO GPIO

C1 Reset_N I External reset input, active LOW

A5 KP_X1 IO GPIO

F1 KP_X2 IO GPIO

F2 KP_X3 IO GPIO

A2 KP_X4 IO GPIO

B3 KP_X5 IO GPIO

A3 KP_X6 IO GPIO

D3 GND2 -

A4 VCC1 - 1.8V Input

6/63

STMPE2403 Pin settings

Table 2. Pin assignment (continued)

Ball Name Type Description

B4 KP_X7 IO GPIO

A1 KP_Y5 IO GPIO

B2 KP_Y4 IO GPIO

B5 KP_Y3 IO GPIO

B6 KP_Y2 IO GPIO

C5 KP_Y1 IO GPIO

C6 KP_Y0 IO GPIO

C4 GND3 -

D6 ADDR0 IO GPIO and I2C ADDR 0 (in reset)

D5 KP_Y9 A/IO GPIO/MUX

E6 KP_Y10 A/IO GPIO/MUX

F6 KP_Y11 A/IO GPIO/MUX

E5 PWM3 A/IO GPIO and I2C ADDR 1 (in reset) /MUX

F5 PWM2 A/IO GPIO/MUX

E4 PWM1 A/IO GPIO/MUX

F4 VCC2 - 1.8V Input

D4 GND4 -

F3 INT O Open drain interrupt output pin

E3 KP_Y8 IO GPIO

C2 KP_Y7 IO GPIO

B1 KP_Y6 IO GPIO

E2 SDATA A I2C DATA

E1 SCLK A I2C Clock

D2 XTALIN A XTAL Oscillator or External 32KHz input.

be left floating.

D1 XTALOUT A XTAL Oscillator

7/63

Pin settings STMPE2403

2.3 GPIO Pin functions

Table 3. GPIO Pin functions

Name Primary Function Alternate Function 1 Alternate Function 2 Alternate Function 3

KP_X0 GPIO 0 Keypad input 0

KP_X1 GPIO 1 Keypad input 1

KP_X2 GPIO 2 Keypad input 2

KP_X3 GPIO 3 Keypad input 3

KP_X4 GPIO 4 Keypad input 4

KP_X5 GPIO 5 Keypad input 5

KP_X6 GPIO 6 Keypad input 6

KP_X7 GPIO 7 Keypad input 7

KP_Y5 GPIO 13 Keypad Output 5

KP_Y4 GPIO 12 Keypad Output 4

KP_Y3 GPIO 11 Keypad Output 3

KP_Y2 GPIO 10 Keypad Output 2

KP_Y1 GPIO 9 Keypad Output 1

KP_Y0 GPIO 8 Keypad Output 0

ADDR0 GPIO 15

KP_Y9 GPIO 18 Keypad Output 9 Rotator 0 Mux1_In_1

KP_Y10 GPIO 19 Keypad Output 10 Rotator 1 Mux1_In_2

KP_Y11 GPIO 20 Keypad Output 11 Rotator 2 Mux1_Out

PWM3 GPIO 23 Mux2_Out

PWM2 GPIO 22 Mux2_In_2

PWM1 GPIO 21 Mux2_In_1

KP_Y8 GPIO 17 Keypad Output 8 ClkOut

KP_Y7 GPIO 16 Keypad Output 7

KP_Y6 GPIO 14 Keypad Output 6

8/63

STMPE2403 Pin settings

2.4 Pin mapping to TFBGA ( bottom view, balls up)

Table 4. Pin mapping to TFBGA ( bottom view, balls up)

ABCDEF

1 KP_Y5 KP_Y6 RESET XTALOUT SCLK KP_X2

2 KP_X4 KP_Y4 KP_Y7 XTALIN SDATA KP_X3

3 KP_X6 KP_X5 GND1 GND2 KP_Y8 INT

4 VCC1 KP_X7 GND3 GND4 PWM-1 VCC2

5 KP_X1 KP_Y3 KP_Y1 KP_Y9 PWM-3 PWM-2

6 KP_X0 KP_Y2 KP_Y0 ADDR0 KP_Y10 KP_Y11

9/63

Maximum rating STMPE2403

3 Maximum rating

Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.

3.1 Absolute maximum rating

Table 5. Absolute maximum rating

Symbol Parameter Value Unit

V

CC

V

Input voltage on GPIO pin 2.5 V

IN

V

I2C Input voltage on I2C pin 4.5 V

IN

VESD (HBM) ESD protection on each GPIO pin 2 KV

Supply voltage 2.5 V

3.2 Thermal data

Table 6. Thermal data

Symbol Parameter Min Typ Max Unit

R

thJA

T

A

T

J

Thermal resistance junction-ambient 100 °C/W

Operating ambient temperature -40 25 85 °C

Operating junction temperature -40 25 125 °C

10/63

STMPE2403 Electrical specification

4 Electrical specification

4.1 DC electrical characteristics

Table 7. DC electrical characteristics

Symbol Parameter Test conditions

VCC1,2 Supply voltage 1.65 1.8 1.95 V

I

HIBERNATE1

HIBERNATE mode
current

XTALIN not floating

Min. Typ. Max.

Val ue

Unit

15 20 uA

I

HIBERNATE2

I

SLEEP1

I

SLEEP2

Icc

INT

HIBERNATE mode
current

SLEEP mode current

SLEEP mode current

Operating current
(FSM working – No
peripheral activity)

Open drain output
current

XTALIN floating

XTALIN not floating

XTALIN floating

4.2 I/O DC electrical characteristics

The 1.8V I/O complies to the EIA/JEDEC standard JESD8-7.

Table 8. I/O DC electrical characteristic

Symbol Parameter

Vil Low level input voltage

Vih High level input voltage

35 40 uA

55 100 uA

75 120 uA

1.2 1.6 mA

4mA

Val u e

Min. Typ. Max.

0.35*Vcc

0.65*Vcc
= 1.17

= 0.63

Unit

V

V

Vhyst Schmitt trigger hysteresis 0.10 V

11/63

Electrical specification STMPE2403

4.3 DC input specification

(1.55V < VDD < 1.95V)

Table 9. DC input specification

Symbol Parameter Test conditions

Min. Typ. Max.

Vol Low level output voltage Iol = 4mA 0.45 V

Val ue

Unit

Voh High level output voltage Ioh = 4mA

Vol_PWM Low level output voltage Iol = 16mA 0.45 V

Voh_PWM High level output voltage Ioh = 16mA

4.4 DC output specification

(1.55V < vdd < 1.95V)

Table 10. DC output specification

Symbol Parameter

Ipu Pull-up current Vi = 0V 15 35 65 uA

Ipd Pull-down current Vi = vdd 14 35 60 uA

Rup Equivalent pull-up resistance Vi = 0V 30 50 103.3 KΩ

Rpd Equivalent pull-down resistance Vi = vdd 32.5 50 110.7 KΩ

Ron_1 Ron when the MUX is ON Vsignal = 0V 5 10 Ω

Ron_2 Ron when the MUX is ON Vsignal = 0.9V 5 20 Ω

Ron_3 Ron when the MUX is ON Vsignal = 1.8V 10 10 Ω

Test

conditions

Vcc - 0.45

= 1.35

Vcc - 0.45

= 1.35

Val ue

Min. Typ. Max.

V

V

Unit

Ron Ron when the MUX is ON Vsignal < 1.8V 20 35 Ω

Note: Pull-up and Pull-down characteristics

4.5 AC characteristics

Table 11. AC characteristics

Symbol Parameter

Int_32KHz Internally generated 32KHz clock 22 28 41.6 KHz

12/63

Val ue

Unit

Min. Typ. Max.

STMPE2403 Register map

5 Register map

All registers have the size of 8-bit. For each of the module, their registers are residing within
the given address range.

Table 12. Register map

Address Module registers Description

0x00 – 0x07
0x80 – 0x81

0x10 – 0x1F

0x30 – 0x37 PWM controller module PWM Controller register range Yes

0x38 – 0x3F PWM Controller register range No

Clock and power
Manager module

Interrupt controller
module

Clock and Power Manager register
range.

Interrupt Controller register range Yes

Auto-Increment

(during read/write)

Ye s

0x60 – 0x6F

0x70 – 0x77

0x82 – 0xBF GPIO Controller Module GPIO Controller register range Yes

Keypad controller
module

Rotator controller
module

Keypad Controller register range Yes

Rotator Controller register range Yes

13/63

I2C Interface STMPE2403

6 I2C Interface

The features that are supported by the I2C interface are as below:

2

● I

C Slave device

● Operates at 1.8V

● Compliant to Philip I

● Supports Standard (up to 100kbps) and Fast (up to 400kbps) modes.

● 7-bit and 10-bit device addressing modes

● General Call

● Start/Restart/Stop

● Address up to 4 STMPE2403 devices via I

The address is selected by the state of two pins. The state of the pins will be read upon
reset and then the pins can be configured for normal operation. The pins will have a pull-up
or down to set the address. The I
access the registers in the STMPE2403.

6.1 Start condition

2

C specification version 2.1

2

C

2

C interface module allows the connected host system to

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.

6.2 Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

2

next I

C transaction. A Stop condition at the end of a write command stops the write

operation to registers.

6.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.

6.4 Data input

The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.

14/63

STMPE2403 I2C Interface

6.5 Slave device address

The slave device address is a 7 or 10-bit address, where the least significant 2-bit are
programmable. These 2-bit values will be loaded in once upon reset and after that these 2
pins no longer be needed with the exception during General Call. Up to 4 STMPE2403
devices can be connected on a single I

2

C bus.

Table 13. Slave device address

ADDR 1 ADDR 0 Address

0 0 0x84

0 1 0x86

1 0 0x88

11 0x8A

6.6 Memory addressing

For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write
operation.

bit (R/W). The bit is set to 1 for Read and 0 for Write

If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9

th

bit time. If there is no match, it deselects itself

from the bus by not responding to the transaction.

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I2C Interface STMPE2403

R

W

0

k
A

k

k
N

A

k

S

R

W

0

k
A

k

k
A

kAck
R

W

0

k
A

k
A

k
S

M

R

W

0

k
A

k
A

kAckAck
S

Da

ad

2

6.7 Operation modes

Table 14. Operation modes

Mode Bytes Programming Sequence

Read ≥1 START, Device Address, R/W

reSTART, Device Address, R/W

If no STOP is issued, the Data Read can be continuously preformed. If
the register address falls within the range that allows address auto­increment, then register address auto-increments internally after every
byte of data being read. For register address that falls within a non­incremental address range, the address will be kept static throughout
the entire read operations. Refer to the Memory Map table for the
address ranges that are auto and non-increment. An example of such
a non-increment address is FIFO.

Write ≥1 START, Device Address, R/W

Write, STOP

If no STOP is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto­increment, then register address auto-increments internally after every
byte of data being written in. For register address that falls within a
non-incremental address range, the address will be kept static
throughout the entire write operations. Refer to the Memory Map table
for the address ranges that are auto and non-increment. An example of
a non-increment address is Data Port for initializing the PWM
commands.

Figure 3. Master/slave operation modes

One Byte
Read

Dev

Addr

Start

=
n

Reg

Addr

Ac

= 0, Register Address to be read

= 1, Data Read, STOP

= 0, Register Address to be written, Data

c

Dev

Addr

reStart

RnW=1Ac

Dat a

Read

c
o

top

Mor e t han
One Byte
Read

One Byte
Write

or e than
One Byte
Write

Dev

Addr

Start

Dev

Addr

Start

Dev

Addr

Start

=
n

=
n

=
n

Reg

Addr

Ac

Reg

Addr

Ac

Reg

Addr

Ac

Mast er

16/63

c

c

c

Dev

Addr

reStart

Dat a to

be

Written

Dat a to

Write

RnW=1Ac

c

top

Dat a to

c

Write + 1

Dat a

Read

c

Dat a to

Write +

Dat a

Read + 1

Re

top

STMPE2403 I2C Interface

6.8 General call address

A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a
general call address is made, STMPE2403 responds to this transaction with an
acknowledgement and behaves as a slave-receiver mode. The meaning of a general call
address is defined in the second byte sent by the master-transmitter.

Table 15.

R/W Second byte value Definition

0 0x06 2-byte transaction in which the second byte tells the slave device to

reset and write (or latch in) the 2-bit programmable part of the slave
address.

0 0x04 2-byte transaction in which the second byte tells the slave device not

to reset and write (or latch in) the 2-bit programmable part of the
slave address.

0 0x00 Not allowed as second byte.

Note: All other second byte value will be ignored.

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System controller STMPE2403

7 System controller

The system controller is the heart of the STMPE2403. It contains the registers for power
control, and the registers for chip identification.

The system registers are:

Table 16. System controller

Address Register_Name

0x00 Reserved (Reads 0x00)

0x01 Reserved (Reads 0x00)

0x02 SYSCON

0x03 SYSCON2

0x80 CHIP_ID

0x81 VERSION_ID

0x82 Reserved (Reads 0x00)

7.1 Identification register

Table 17. CHIP_ID

Bit 76543210

Read/Write(IIC) RRRRRRRR

Reset Value 00000001

Table 18. VERSION_ID

Bit 76543210

Read/Write(IIC) R R R R R R R R

Reset Value 00000010

8-bit LSB of Chip ID

8-bit Version ID

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STMPE2403 System controller

7.2 System control register

Table 19. System control register

Bit 7 6 5 4 3 2 1 0

Soft_Reset Clock_Source Disable_32KHz Sleep Enable_GPIO Enable_PWM Enable_KPC Enable_ROT

Read/

Write (IIC)

Reset

Val ue

WRW RWRWRW RWRWRW

00 001 1 11

Table 20. System control register writing

Bits Name Description

0 Enable_ROT Writing a ‘0’ to this bit will gate off the clock to the Rotator module, thus

stopping its operation

1 Enable_KPC Writing a ‘0’ to this bit will gate off the clock to the Keypad Controller module,

thus stopping its operation

2 Enable_PWM Writing a ‘0’ to this bit will gate off the clock to the PWM module, thus

stopping its operation

3 Enable_GPIO Writing a ‘0’ to this bit will gate off the clock to the GPIO module, thus

stopping its operation

4 Sleep Writing a ‘1’ to this bit will put the device in sleep mode. When in sleep

mode, all the units will work on 32KHz (typical) clock frequency.

5 Disable_32KHz Set this bit to disable the 32KHz OSC, thus putting the device in hibernate

mode. Only a Reset or a wakeup on IIC will reset this bit

6 Clock_Source Set to ‘1’ if external 32KHz clock were to be used. ‘0’ by default.

7 Soft_Reset Writing a ‘1’ to this bit will do a soft reset of the device. Once the reset is

done, this bit will be cleared to ‘0’ by the HW.

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