ST STMPE1601 User Manual

STMPE1601

16-bit enhanced port expander with keypad and PWM controller

Xpander Logic™

Features

■ 16 GPIOs

(8 operate at core supply V
supply V

■ Operating voltage 1.8 −3.3 V

■ Hardware keypad controller (8*8 matrix with 4

IO

)

optional dedicated keys max)

■ Keypad controller capable of detecting key-

press in hibernation mode

■ 4 basic PWM controllers for LED brightness

control

■ Interrupt output (open drain) pin

■ Optional 32 kHz clock input

■ 8-channel programmable level translator

■ Advanced power management system

■ Ultra-l ow st an db y- mo de cu rr en t

■ Package TFBGA25 (3 x 3 mm)

, 8 operate at IO

CC

TFBGA25

Description

The STMPE1601 is a GPIO (general purpose
input/output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus

2

(I

C). A separate GPIO expander IC is often used
in mobile multimedia platforms to solve the
problems of the limited number of GPIOs typically
available on the digital engine.

The STMPE1601 offers great flexibility, as each
I/O can be configured as input, output or specific
functions. The device is able to scan a keyboard,
also provides PWM outputs for brightness control
in backlight, and GPIO function. This device has
been designed to include very low quiescent
current, and a wake-up feature for each I/O, to
optimize the power consumption of the IC.

Potential applications of the STMPE1601 include
portable media players, game consoles, mobile
and smart phones.

Table 1. Device summary

Order code Package Packaging

STMPE1601TBR TFBGA25 Tape and reel

February 2010 Doc ID 14318 Rev 6 1/62

www.st.com

62

Contents STMPE1601

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Ball mapping to TFBGA (top through view) . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 GPIO pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Input/Output DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.1 Minimizing current drain on I2C address lines . . . . . . . . . . . . . . . . . . . . . 13

6.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.6 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.7 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.8 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.9 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.1 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2 Autosleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3 Keypress detect in the hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/62 Doc ID 14318 Rev 6

STMPE1601 Contents

8 Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2 Power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1 Interrupt system register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1.1 Interrupt latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.2 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10.1 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.2 GPIO alternate function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3 Hotkey feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3.1 Programming sequence for Hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.3.2 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.4 Level translator feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11 Basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.1 Interrupt on basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11.2 Trigger feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12.1 Keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.2 Keypad controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14 Keypad combination key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Doc ID 14318 Rev 6 3/62

Block diagram STMPE1601

1 Block diagram

Figure 1. STMPE1601 block diagram

2ESET?.

#,+?).

3#,+

3$!4

).4

+EYPADCONTROLLER

-AIN&3­07-

'0)/CONTROL

!
!



) #

!

)NTERFACE

0/2

-58

-58

+EYPADINPUTCOLUMNXX
'0)/
07-

0OWEREDBY6##

+EYPADOUTPUTROWYY
!$$2
'0)/ 

0OWEREDBY6 

'.$
'.$

6

##

6

)/

)/

#3

4/62 Doc ID 14318 Rev 6

STMPE1601 Pin settings

2 Pin settings

2.1 Pin connection

Figure 2. Pin connection (top-through view)

12 3 45

GPIO_9 GPIO_8 GPIO_7 GPIO_5 GPIO_4

A

GPIO_11 GPIO_10 GPIO_6 CLK_IN INT

B

C

D

E

VIO GND GND GPIO_3 VCC

GPIO_12 GPIO_13 GPIO_1 GPIO_2

GPIO_14 GPIO_15

SCLK

SDATA RESET_N GPIO_0

TFBGA25

2.2 Pin assignment and TFBGA ball location

Table 2. Pin assignment

Ball name Name Type Domain Description

E5 GPIO_0 I/O V

D4 GPIO_1 I/O V

D5 GPIO_2 I/O V

C4 GPIO_3 I/O V

A5 GPIO_4 I/O V

A4 GPIO_5 I/O V

B3 GPIO_6 I/O V

A3 GPIO_7 I/O V

A2 GPIO_8 I/O V

A1 GPIO_9 I/O V

B2 GPIO_10 I/O V

CC

CC

CC

CC

CC

CC

CC

CC

IO

IO

IO

AM00757V1

GPIO 0/ KP_X0/ PWM_0

GPIO 1/ KP_X1/ PWM_1

GPIO 2/ KP_X2/ PWM_2

GPIO 3/ KP_X3/ PWM_3

GPIO 4/ KP_X4

GPIO 5/ KP_X5

GPIO 6/ KP_X6

GPIO 7/ KP_X7

GPIO 8/ KP_Y0

GPIO 9/ KP_Y1

GPIO 10/ KP_Y2

Doc ID 14318 Rev 6 5/62

Pin settings STMPE1601

Table 2. Pin assignment (continued)

Ball Name Name Type Domain Description

B1 GPIO_11 IO V

D1 GPIO_12 IO V

D2 GPIO_13 IO V

E1 GPIO_14 IO V

E2 GPIO_15 IO V

GPIO 11/ KP_Y3

IO

GPIO 12/ KP_Y4

IO

GPIO 13/ KP_Y5/ ADDR0

IO

GPIO 14/ KP_Y6/ ADDR1

IO

GPIO 15/ KP_Y7/ ADDR2

IO

Open drain interrupt output pin.
INT pin to be externally pulled

B5 INT O V

up to V

CC

pulled down to GND, depending
on polarity of interrupt (must not
be left floating).

External reset input, active

E4 Reset_N I V

LOW. Reset_N pulse width

CC

must be
internally pulled up to VCC.

E3 SDATA A V

D3 SCLK A V

I2C DATA (tolerant to 3.6 V)

CC

I2C clock (tolerant to 3.6 V)

CC

32 kHz input. To be pulled-up to

with 10 k resistor if clock is

V

B4 CLK_IN A V

CC

CC

not used. This pin is internally
pulled to VCC.

1.8

C5 VCC – –

C1 VIO – –

−3.3 V input for I

and digital core

−3.3 V input for GPIO. The

1.8
VIO must be

C2 GND – – Ground

C3 GND – – Ground

(or > VCC, < 3.6 V), or

CC

≥ 20 μs. This pin is

2

C module

≥ V

.

CC

2.3 Ball mapping to TFBGA (top through view)

Table 3. Pin mapping

12345

A GPIO_9 GPIO_8 GPIO_7 GPIO_5 GPIO_4

B GPIO_11 GPIO_10 GPIO_6 CLK_IN INT

C VIO GND GND GPIO_3 VCC

D GPIO_12 GPIO_13 SCLK GPIO_1 GPIO_2

E GPIO_14 GPIO_15 SDATA RESET_N GPIO_0

6/62 Doc ID 14318 Rev 6

STMPE1601 Pin settings

2.4 GPIO pin functions

Table 4. GPIO pin functions

Name

GPIO_0 GPIO Keypad PWM –

GPIO_1 GPIO Keypad PWM –

GPIO_2 GPIO Keypad PWM –

GPIO_3 GPIO Keypad PWM –

GPIO_4 GPIO Keypad – –

GPIO_5 GPIO Keypad – –

GPIO_6 GPIO Keypad – –

GPIO_7 GPIO Keypad – –

GPIO_8 GPIO Keypad – –

GPIO_9 GPIO Keypad – –

GPIO_10 GPIO Keypad – –

GPIO_11 GPIO Keypad – –

GPIO_12 GPIO Keypad – –

GPIO_13 GPIO Keypad – I

GPIO_14 GPIO Keypad – I

GPIO_15 GPIO Keypad – I

Primary

function

Alternate

function 1

Alternate

function 2

Note

2

C ADDR during RESET

2

C ADDR during RESET

2

C ADDR during RESET

Doc ID 14318 Rev 6 7/62

Maximum ratings STMPE1601

3 Maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

3.1 Absolute maximum ratings

Table 5. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

Input voltage on GPIO pin 4.5 V

V

IN

VESD (HBM) ESD protection on each GPIO pin 2 kV

Supply voltage 4.5 V

3.2 Thermal data

Table 6. Thermal data

Symbol Parameter Min Typ Max Unit

R

thJA

T

A

T

J

Thermal resistance junction-ambient - 100 – °C/W

Operating ambient temperature -40 25 85 °C

Operating junction temperature -40 25 125 °C

8/62 Doc ID 14318 Rev 6

STMPE1601 Electrical specification

4 Electrical specification

4.1 DC electrical characteristics

Table 7. DC electrical characteristics

Val ue

Symbol Parameter Test conditions

Min Typ Max

Unit

V

CC

V

IO

I

CC

I

SLEEP

I

HIBERNATE

I

CC

I

SLEEP

I

HIBERNATE

I

CC

I

SLEEP

I

HIBERNATE

I

CC

I

SLEEP

I

HIBERNATE

INT

1. If only the basic GPIO function is required, the STMPE1601 can be designed to work mostly in hibernate
mode. Active mode is used only when there are changes in the I/O status.

1.8 V supply voltage 1.65

IO supply voltage 1.65

Active current

IO VCC

=1.8V

Sleep current – 18 25 µA

V
T= 25 °C

–1.21.6mA

−

−

Hibernate current – 0.5 1.5 µA

Active current

Sleep current – 50 60 µA

Hibernate current

(1)

V
T= 25 °C

IO VCC

=3.3V

Active current

IO VCC

=1.8V

Sleep current – – 32 µA

V
T= 85 °C

–3.03.8mA

–1.23µA

––2mA

Hibernate current – – 2 µA

Active current

Sleep current – – 75 µA

Hibernate current

(1)

V
T= 85 °C

IO VCC

=3.3V

Open drain output
current

––4.8mA

––5µA

–4–mA

3.6 V

3.6 V

Doc ID 14318 Rev 6 9/62

Electrical specification STMPE1601

4.2 Input/Output DC electrical characteristics

The 1.8 V I/O complies to the EIA/JEDEC standard JESD8-7.

Table 8. I/O DC electrical characteristic

Val ue

Symbol Parameter

Min Typ Max

Unit

V

il

V

ih

V

hyst

V

il

V

ih

V

hyst

Table 9. DC input specification (1.55 V < VCC<1.95V)

Symbol Parameter

V

ol

V

oh

V

ol

V

oh

Low level input voltage VIO= 1.8 V – – 0.63 V

High level input voltage VIO=1.8V 1.17 – – V

Schmitt trigger hysteresis VIO=1.8V – 0.10 – V

Low level input voltage VIO= 3.3 V – – 1.15 V

High level input voltage VIO=3.3V 2.14 – – V

Schmitt trigger hysteresis VIO=3.3V – 0.20 – V

Tes t

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

conditions

Iol=4mA

=1.8V

V

IO

Ioh=4mA

=1.8V

V

IO

Iol=4mA

=3.3V

V

IO

Ioh=4mA

=3.3V

V

IO

Min Typ Max

– – 0.45 V

1.35 – – V

– – 0.83 V

2.48 – – V

Val ue

Unit

Table 10. DC output specification (1.55 V < VCC < 1.95 V)

Symbol Parameter Test conditions

I

pu

R

up

R

up

1. Applicable to GPIO_0 to GPIO_7.

2. Applicable to GPIO_8 to GPIO_15.

10/62 Doc ID 14318 Rev 6

Pull-up current VI=0V 15 35 65 μA

=3.3V 30 60 90 kΩ

V

Equivalent pull-up

(1)

resistance

Equivalent pull-up

(2)

resistance

CC

= 1.8 V 50 100 150 kΩ

V

CC

=3.3V 30 60 90 kΩ

V

IO

= 1.8 V 50 100 150 kΩ

V

IO

Val ue

Unit

Min Typ Max

STMPE1601 Register map

5 Register map

All the registers have the size of 8-bit. For each of the module, their registers are residing
within the given address range.

Table 11. Register map summary table

Address Module register Description

0x00 – 0x07
0x80 – 0x81

0x10 – 0x1F

0x40 – 0x5F PWM controller module PWM controller register range Yes

0x60 – 0x6F

0x70 – 0x77

0x80 – 0xBF GPIO controller module GPIO controller register range Yes

Clock and power
manager module

Interrupt controller
module

Keypad controller
module

Rotator controller
module

Clock and power manager register
range

Interrupt controller register range Yes

Keypad controller register range Yes

Rotator controller register range Yes

Auto-increment

(during read/write)

Ye s

Doc ID 14318 Rev 6 11/62

I2C interface STMPE1601

6 I2C interface

The features supported by the I2C interface are listed below:

2

● I

C slave device

● Operates at V

● Compliant to Philips I

● Supports standard (up to 100kbps) and fast (up to 400 kbps) modes

● 7-bit and 10-bit device addressing modes

● General Call

● Start/Restart/Stop

● Address up to 8 STMPE1601 devices via the I

The address is selected by the state of 3 pins. The state of the pins is read upon reset and
then the pins can be configured for normal operation. The pins have a pull-up or pull-down
to set the address. The I
the registers in the STMPE1601.

(1.8 - 3.3 V)

CC

2

C specification version 2.1

2

C interface

2

C interface module allows the connected host system to access

Table 12. I

A2 A1 A0 7-bit address

00040h

00141h

01042h

01143h

10044h

10145h

11046h

11147h

2

C addresses

12/62 Doc ID 14318 Rev 6

STMPE1601 I2C interface

6.1 Minimizing current drain on I2C address lines

The GPIOs 13-15 are used as I2C address input during POR. Pull-up/down resistor of
500 kΩ - 1.5 MΩ is recommended for these address lines. In the case that these pins are
driven to an opposite logic level during device operation, there would be a current drain of
V

/R. This amounts to a significant current drain for portable devices.

IO

To minimize the current drain on I

1. If maximum keypad size is not required, these shared lines should not be used for

keypad operation.

2. If the maximum keypad size is required, choose I

address lines to be pulled to ground, minimizing the current drain in the keypad
operation. In this mode of operation, the recommended pull up/down resistors on the

2

I

C lines are listed in Ta bl e 1 3 .

A reset circuit with longer RC is used to ensure enough time for the address lines to
settle to the final values.

3. In system-controlled idle state, all the keypad pins are to be configured as hotkey with

interrupt function enabled. If any key is pressed, the system initiates the keypad
controller for scanning operation.

2

C lines, two methods are recommended:

2

C address 0x40, as this requires all 3

Table 13. Recommended pull up/down resistors on the I

V

Pull up/down

resistor

RPU/R

PD

RPU/R

PD

RPU/R

PD

1. Recommended values are chosen to minimize leakage current.

1.8V 2.5V 3.3V

1.5 MΩ 1.2 MΩ 1MΩ

1.0 MΩ 800 kΩ 660 kΩ

500 kΩ 400 kΩ 330 kΩ

IO

or pulse width

270 kΩ/0.47 µF

180 kΩ/0.47 µF

2

C lines

Reset RC

120 ms

80 ms

90kΩ/0.47 µF

40 ms

(1)

All 3 address
lines are
used for
keypad
controller

2 address
lines are
used for
keypad
controller

1 address
line is used
for keypad
controller

Note

Doc ID 14318 Rev 6 13/62

I2C interface STMPE1601

6.2 Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.

6.3 Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates the communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

2

next I

C transaction. A Stop condition at the end of a write command stops the write

operation to the registers.

6.4 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.

6.5 Data input

The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.

6.6 Slave device address

The slave device address is a 7 or 10-bit address, where the least significant 3-bit are
programmable. These 3-bit values will be loaded in once upon reset and after that these 3
pins no longer be needed with the exception during General Call. Up to 8 STMPE1601
devices can be connected on a single I

6.7 Memory addressing

For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write
operation.

If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9
from the bus by not responding to the transaction.

2

C bus.

bit (R/W). The bit is set to 1 for Read and 0 for Write

th

bit time. If there is no match, it deselects itself

14/62 Doc ID 14318 Rev 6

STMPE1601 I2C interface

6.8 Operating modes

Table 14. Operating modes

Mode Bytes Programming sequence

START, Device address, R/W

reSTART, Device address, R/W

If no STOP is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows address auto-

Read ≥1

increment, then register address auto-increments internally after every
byte of data being read. For register address that falls within a non­incremental address range, the address will be kept static throughout
the entire read operations. Refer to the Table 11: Register map

summary table on page 11 for the address ranges that are auto and

non-increment. An example of such a non-increment address is FIFO.

START, Device address, R/W
Write, STOP.

If no STOP is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto-

Write ≥1

increment, then register address auto-increments internally after every
byte of data being written. For those register addresses that fall within
a non-incremental address range, the address will be kept static
throughout the all write operations. Refer to the memory map table for
the address ranges that are auto and non-increment. An example of a
non-increment address is Data Port for initializing the PWM
commands.

Figure 3. I2C transaction

= 0, Register address to be read

= 1, Data Read, STOP

= 0, Register address to be written, Data

One byte

Read

More than one byte

Read

One byte

Write

More than one byte

Read

Start

Start

Start

Start

Device

Address

Device

Address

Device

Address

Device

Address

Master

Slave

R/W=0

R/W=0

R/W=0

R/W=0

Ack

Ack

Ack

Ack

Reg

Address

Reg

Address

Reg

Address

Reg

Address

Device

Ack

Address

Restart

Device

Ack

Address

Restart

Data

to be

Ack

Restart

written

Data to

Ack

Write

Restart

R/W=1

R/W=1

Ack

Data to

Ack

Write + 1

Ack

Ack

Stop

Data

Read

Data

Read

Ack

Write + 2

No Ack

Ack

Data to

Stop

Data

Read + 1

Data

Ack

Read + 2

Ack

Stop

Doc ID 14318 Rev 6 15/62

Stop

No Ack

I2C interface STMPE1601

6.9 General call address

A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a
general call address is made, the STMPE1601 responds to this transaction with an
acknowledgement and behaves as a slave-receiver mode. The meaning of a general call
address is defined in the second byte sent by the master-transmitter.

Table 15. General call address

R/W Second byte value Definition

A 2-byte transaction in which the second byte tells the slave

0 0x06

0 0x04

0 0x00 Not allowed as second byte.

Note: All other second byte values will be ignored.

device to reset and write (or latch in) the 2-bit programmable part
of the slave address.

A 2-byte transaction in which the second byte tells the slave
device not to reset and write (or latch in) the 2-bit programmable
part of the slave address.

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STMPE1601 System controller

7 System controller

The system controller is the heart of the STMPE1601. It contains the registers for power
control and chip identification.

The system registers are:

Table 16. System registers

Address Register name

0x80 CHIP_ID

0x81 VERSION_ID

0x02 SYS_CTRL

0x03 SYS_CTRL_2

CHIP_ID Chip identification register

76543210

8-bit CHIP_ID

RRRRRRRR

00000010

VERSION_ID Version identification register

76543210

8-bit VERSION_ID

RRRRRRRR

00010010

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System controller STMPE1601

SYS_CTRL System control register

7 6543210

SOFT_RESET

W RWRWRWRW R RWRW

0 0001111

Address: 0x02

Type: R/W

CLOCK

SOURCE

DIS_32KHz SLEEP EN_GPIO RESERVED EN_KPC EN_SPWM

Reset: 0x0

F

Description: System control register.

[7] SOFT_RESET

Writing a ‘1’ to this bit will do a soft reset of the device. Once the reset is done, this bit will be
cleared to ‘0’ by the HW.

[6] CLOCK_SOURCE

Set to ‘1’ if external 32 kHz clock were to be used. ‘0’ by default.

[5] DIS_32 kHz:

Set this bit to disable the 32 kHz OSC, thus putting the device in hibernate mode.

[4] SLEEP:

Writing a ‘1’ to this bit will put the device in sleep mode. On going to sleep mode, this mode is
reset internally. When in sleep mode, the internal RC oscillator will output a slower sleep clock
which will be used in the device.

[3] EN_GPIO:

Writing a ‘0’ to this bit will gate off the clock to the GPIO module, thus stopping its operation

[2] RESERVED

[1] EN_KPC:

Writing a ‘0’ to this bit will gate off the clock to the keypad controller module, thus stopping its
operation

[0] EN_SPWM

Writing a ‘0’ to this bit will gate off the clock to the simple PWM controller module, thus
stopping its operation

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STMPE1601 System controller

SYS_CTRL_2 System control register 2

76543210

RESERVED VIO_OFF AUTOSLEEP_EN SLEEP_2 SLEEP_1 SLEEP_0

R R RW RW RW RW

0 00000

Address: 0x03

Type: R/W

Reset: 0x00

Description: System control register.

[7] RESERVED

[6] RESERVED

[5] RESERVED

[4] VIO_OFF:

Writing a ‘1’ to this bit is mandatory before shutting off the V

supply.

V

CC

This ensure that the level shifters for GPIOs 15-8 are properly powered down so as not to
induce high current and also not to affect the integrity of any external signals that are on the
bus where these GPIOs are connected.

[3] AUTOSLEEP_EN:

“1” to enable auto-sleep feature. “0” to disable auto-sleep.

[2:0] SLEEP:

000 for 4 ms delay
001 for 16 ms delay
010 for 32 ms delay
011: for 64 ms delay
100: for 128 ms delay
101: for 256 ms delay
110: for 512 ms delay
111: for 1024 ms delay

supply while maintaining the

IO

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