ST STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A, STM8AF5289 User Manual

STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax

LQFP80 14x14

LQFP48 7x7

LQFP32 7x7

VFQFPN32 5x5

LQFP64 10x10

Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,

10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V

Datasheet − production data

Features

■ Core

–Max f
– Advanced STM8A core with Harvard

architecture and 3-stage pipeline

– Average 1.6 cycles/instruction resulting in

10 MIPS at 16 MHz f
standard benchmark

■ Memories

– Program memory: 32 to 128 Kbytes Flash

program; data retention 20 years at 55 °C

– Data memory: up to 2 Kbytes true data

EEPROM; endurance 300 kcycles

– RAM: 2 Kbytes to 6 Kbytes

■ Clock management

– Low-power crystal resonator oscillator with

external clock input

– Internal, user-trimmable 16 MHz RC and

low-power 128 kHz RC oscillators

– Clock security system with clock monitor

■ Reset and supply management

– Wait/auto-wakeup/Halt low-power modes

with user definable clock gating

– Low consumption power-on and power-

down reset

■ Interrupt management

– Nested interrupt controller with 32 vectors
– Up to 37 external interrupts on 5 vectors

■ Timers

– 2 general purpose 16-bit timers with up to 3

CAPCOM channels each (IC, OC, PWM)

– Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
– Window and independent watchdog timers

■ I/Os

– Up to 68 user pins (11 high sink I/Os)
– Highly robust I/O design, immune against

current injection

CPU

: 24 MHz

for industry

CPU

■ Communication interfaces

– High speed 1 Mbit/s CAN 2.0B interface
– USART with clock output for synchronous

operation - LIN master mode

– LINUART LIN 2.1 compliant, master/slave

modes with automatic resynchronization

– SPI interface up to 10 Mbit/s or f

2

–I

C interface up to 400 Kbit/s

■ Analog to digital converter (ADC)

MASTER

– 10-bit resolution, 2 LSB TUE, 1 LSB

linearity and up to 16 multiplexed channels

■ Operating temperature up to 150 °C

■ Qualification conforms to AEC-Q100 rev G

Table 1. Device summary

Part numbers: STM8AF52xx (with CAN)

STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A,
STM8AF5289, STM8AF5288, STM8AF5269, STM8AF5268

Part numbers: STM8AF6269/8x/Ax

STM8AF62AA, STM8AF62A9, STM8AF62A8, STM8AF628A,
STM8AF6289, STM8AF6288, STM8AF6286, STM8AF6269,
STM8AF62A6,

Part numbers: STM8AF51xx

STM8AF51AA, STM8AF51A9, STM8AF51A8, STM8AF519A,
STM8AF5199, STM8AF5198, STM8AF518A, STM8AF5189,
STM8AF5188, STM8AF5179, STM8AF5178, STM8AF5169,
STM8AF5168

Part numbers: STM8AF6169/7x/8x/9x/Ax

STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,
STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,
STM8AF6188, STM8AF6186, STM8AF6179, STM8AF6178,
STM8AF6176, STM8AF6169

In the order code, ‘F’ applies to devices with Flash program

1.

memory and data EEPROM while ‘H’ refers to devices with
Flash program memory only. ‘F’ is replaced by ‘P’ for devices
with FASTROM (see Tables 2, 3, 4, and 5, and Figure 52).

2. Not recommended for new design.

(with CAN)

(1)

(2)

(2)

/2

July 2012 Doc ID 14395 Rev 9 1/110

This is information on a product in full production.

www.st.com

1

Contents STM8AF52/62xx, STM8AF51/61xx

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.3 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 16

5.2.1 SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.2 Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4.2 Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4.3 Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4.4 Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5.2 16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 18

5.5.3 128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 19

5.5.4 24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . 19

5.5.5 External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.6 Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.7 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7.1 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7.2 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7.3 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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5.7.4 Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 21

5.7.5 Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.8 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.9 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.9.1 Universal synchronous/asynchronous receiver transmitter (USART) . . 23

5.9.2 Universal asynchronous receiver/transmitter with LIN support

(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.9.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.9.4 Inter integrated circuit (I

5.9.5 Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 27

2

C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8 Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65

10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67

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10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 77

10.3.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.3.10 I

10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

2

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 88

11 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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STM8AF52/62xx, STM8AF51/61xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM8AF52xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. STM8AF62xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. STM8AF/H/P51xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. STM8AF/H/P61xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13. STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 15. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 16. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 17. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 18. Temporary memory unprotection registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 19. STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 20. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 21. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 22. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 23. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 24. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 25. Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 26. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 27. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 28. Total current consumption in Run, Wait and Slow mode. General conditions

for V

Table 29. Total current consumption in Halt and Active-halt modes. General conditions for V

applied. TA = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 30. Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 31. Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 32. Typical peripheral current consumption V

Table 33. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 34. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 35. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 36. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 37. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 38. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 39. Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 40. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 41. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 42. TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 43. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 44. I

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 46. ADC accuracy for V

apply, TA = -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

DD

DD

= 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DD

= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

DDA

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Table 47. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 48. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 49. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 50. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 51. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 52. LQFP 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 90

Table 53. LQFP 64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 91

Table 54. LQFP 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 93

Table 55. LQFP 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 95

Table 56. VFQFPN 32-lead very thin fine pitch quad flat no-lead package

mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 57. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx List of figures

List of figures

Figure 1. STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 4. LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 5. LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 6. LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 7. Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 10. f

CPUmax

Figure 11. External capacitor C
Figure 12. Typ. I
Figure 13. Typ. I
Figure 14. Typ. I
Figure 15. Typ. I
Figure 16. Typ. I
Figure 17. Typ. I

Figure 18. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 19. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 20. Typical HSI frequency vs V
Figure 21. Typical LSI frequency vs V
Figure 22. Typical V
Figure 23. Typical pull-up resistance R
Figure 24. Typical pull-up current I
Figure 25. Typ. V
Figure 26. Typ. V
Figure 27. Typ. V
Figure 28. Typ. V
Figure 29. Typ. V
Figure 30. Typ. V
Figure 31. Typ. V
Figure 32. Typ. V
Figure 33. Typ. V
Figure 34. Typ. V
Figure 35. Typical NRST V
Figure 36. Typical NRST pull-up resistance R
Figure 37. Typical NRST pull-up current I

Figure 38. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 39. SPI timing diagram in slave mode and with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 40. SPI timing diagram in slave mode and with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 41. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 42. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 43. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 44. LQFP 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 45. LQFP 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 46. LQFP 64-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 47. LQFP 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 48. LQFP 48-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

versus V

DD(RUN)HSE

DD(RUN)HSE

DD(RUN)HSI

DD(WFI)HSE

DD(WFI)HSE

DD(WFI)HSI

IL

@ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

OL

@ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

OL

@ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

OL

@ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

OL

@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

@ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OL

- V

DD

- V

DD

- VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DD

- V

DD

DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

vs. VDD @f

vs. f
vs. VDD @ f
vs. VDD @ f
vs. f

vs. VDD @ f

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EXT

@ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 64

CPU

@ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 64

CPU

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 64

CPU

= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 64

CPU

= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 64

CPU

= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 64

CPU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

DD

and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 72

PU

vs VDD @ four temperatures

pu

@ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OH

@ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OH

@ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

OH

and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 75

IL

pu

vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PU

vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . 73

Doc ID 14395 Rev 9 7/110

List of figures STM8AF52/62xx, STM8AF51/61xx

Figure 49. LQFP 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 50. LQFP 32-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5). . . . . . . . . . . . . . . 97

Figure 52. Ordering information scheme

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

8/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Introduction

1 Introduction

This datasheet refers to the STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx
products with 32 to 128 Kbytes of program memory.

In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM, ‘H’
to product versions with Flash only, and ‘P’ to product versions with FASTROM. The
identifiers ‘F’, ‘H’, and ‘P’ do not coexist in a given order code.

The datasheet contains the description of family features, pinout, electrical characteristics,
mechanical data and ordering information.

● For complete information on the STM8A microcontroller memory, registers and

peripherals, please refer to STM8S and STM8A microcontroller families reference
manual (RM0016).

● For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8S and STM8A Flash programming manual (PM0051).

● For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

● For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

Doc ID 14395 Rev 9 9/110

Description STM8AF52/62xx, STM8AF51/61xx

2 Description

The STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx automotive 8-bit
microcontrollers described in this datasheet offer from 32 Kbytes to 128 Kbytes of non
volatile memory and integrated true data EEPROM. They are referred to as high density
STM8A devices in the STM8S and STM8A microcontroller families reference manual
(RM0016).

The STM8AF51xx and STM8AF52xx series feature a CAN interface.

All devices of the STM8A product line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.

Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular
peripherals. Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8A family thanks to their advanced core which is
made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V
operating supply.

All STM8A and ST7 microcontrollers are supported by the same tools including
STVD/STVP development environment, the STice emulator and a low-cost, third party in­circuit debugging tool.

10/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Product line-up

3 Product line-up

Table 2. STM8AF52xx product line-up with CAN

..

High

Order code Package

density

Flash

program

memory

RAM

(bytes)

Data

EEPROM

(bytes)

(bytes)

STM8AF/P52AA

STM8AF/P528A 64 K

LQFP80

(14x14)

128 K

2 K

STM8AF/P52A9

128 K

LQFP64

(10x10)

6 K

STM8AF/P5269 32 K 1 K

STM8AF/P52A8

LQFP48

128 K

2 K

(7x7)

STM8AF/P5268 32 K 1K

Table 3. STM8AF62xx product line-up without CAN

High

Order code Package

density

Flash

program

memory

RAM

(bytes)

Data

EEPROM

(bytes)

(bytes)

10-bit

A/D

chan.

16

10 38/35STM8AF/P5288 64 K

10-bit

A/D

chan.

Timers

(IC/OC/PWM)

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

Timers

(IC/OC/PWM)

Serial

interfaces

CAN,

LIN(UART)

, SPI,

USART,

I²C

Serial

interfaces

I/0

wakeup

pins

68/37

52/36STM8AF/P5289 64 K

I/0

wakeup

pins

STM8AF/P62AA

STM8AF/P628A 64 K

LQFP80

(14x14)

STM8AF/P62A9

128 K

2 K

128 K

LQFP64

(10x10)

STM8AF/P6269 32 K 1 K

STM8AF/P62A8

STM8AF/P6288

STM8AF/P6286

STM8AF/P62A6

LQFP48

(7x7)

LQFP32

(7x7)

VFQFPN32

(5x5)

128 K

64 K

128 K

6 K

2 K

Doc ID 14395 Rev 9 11/110

68/37

16

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

LIN(UART),

SPI,

USART, I²C

52/36STM8AF/P6289 64 K 2 K

10 38/35

1x8-bit: TIM4

3x16-bit: TIM1,

7

TIM2, TIM3

LIN(UART),

SPI, I²C

25/23

(8/8/8)

Product line-up STM8AF52/62xx, STM8AF51/61xx

.

Table 4. STM8AF/H/P51xx product line-up with CAN

High

Order code Package

density

Flash
program
memory

(bytes)

RAM

(bytes)

Data

EEPROM

(bytes)

10-bit

A/D

chan.

Timers

(IC/OC/PWM)

Serial

interfaces

I/0

wakeup

pins

STM8AF/H/P51AA

128 K

LQFP80

(14x14)

STM8AF/H/P518A 64 K

STM8AF/H/P51A9

128 K

6 K 2 K

STM8AF/H/P5199 96 K

STM8AF/H/P5189 64 K 4 K

LQFP64

(10x10)

1.5 K

STM8AF/H/P5179 48 K 3 K

STM8AF/H/P5169 32 K 2 K 1 K

STM8AF/H/P51A8

128 K

6 K 2 K

STM8AF/H/P5198 96 K

STM8AF/H/P5188 64 K 4 K

LQFP48

(7x7)

1.5 K

STM8AF/H/P5178 48 K 3 K

STM8AF/H/P5168 32 K 2 K 1K

68/37STM8AF/H/P519A 96 K

16

1x8-bit: TIM4

3x16-bit: TIM1,

TIM2, TIM3

(9/9/9)

CAN,

LIN(UART)

, SPI,

USART,

I²C

52/36

10 38/35

12/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Product line-up

²

Table 5. STM8AF/H/P61xx product line-up without CAN

High

Order code Package

density

Flash
program
memory

(bytes)

RAM

(bytes)

Data

EEPROM

(bytes)

10-bit

A/D

chan.

Timers

(IC/OC/PWM)

Serial

interfaces

I/0

wakeup

pins

STM8AF/H/P61AA

128 K

LQFP80

(14x14)

STM8AF/H/P618A 64 K

STM8AF/H/P61A9

128 K

6 K 2 K

STM8AF/H/P6199 96 K

STM8AF/H/P6189 64 K 4 K

LQFP64

(10x10)

1.5 K

STM8AF/H/P6179 48 K 3 K

STM8AF/H/P6169 32 K 2 K 1 K

STM8AF/H/P61A8

128 K

6 K 2 K

STM8AF/H/P6198 96 K

STM8AF/H/P6188 64 K 4 K

LQFP48

(7x7)

STM8AF/H/P6178 48 K 3 K

STM8AF/H/P6186

64 K 4 K

1.5 K

LQFP32

STM8AF/H/P6176 48 K 3 K

(7x7)/

68/37STM8AF/H/P619A 96 K

16

1x8-bit: TIM4

3x16-bit:

TIM1, TIM2,

TIM3

LIN(UART),

SPI,

USART, I²C

52/36

(9/9/9)

10 38/35

1x8-bit: TIM4

7

3x16-bit:

TIM1, TIM2,

LIN(UART),

SPI, I²C

25/23

TIM3 (8/8/8)

Doc ID 14395 Rev 9 13/110

Block diagram STM8AF52/62xx, STM8AF51/61xx

XTAL 1-24 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8A CORE

Debug/SWIM

I

2

C

SPI

USART

LINUART

16-bit general purpose

AWU tim er

Reset block

Reset

Clock controller

Detector

Clock to peripherals and core

10 Mbit/s

LIN master

Up to

Window WDG

IWDG

Up to 128 Kbyte

Up to 2 Kbytes

Up to 6 Kbytes

Boot ROM

10-bit ADC

beCAN

9 CAPCOM

Reset

400 Kbit/s

1 Mbit/s

Master/slave

Single wire

automatic

debug interf.

SPI emul.

channels

high density program

Flash

16-bit advanced control

timer (TIM1)

(TIM2, TIM3)

8-bit AR timer

(TIM4)

data EEPROM

RAM

Up to

Address and data bus

16 channels

resynchronization

POR

BOR

4 Block diagram

Figure 1. STM8A block diagram

1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent window watchdog
LINUART: Local interconnect network universal asynchronous receiver transmitter
POR: Power on reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter

14/110 Doc ID 14395 Rev 9

Window WDG: Window watchdog

STM8AF52/62xx, STM8AF51/61xx Product overview

5 Product overview

This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.

For more detailed information on each feature please refer to the STM8S and STM8A
microcontroller families reference manual (RM0016).

5.1 STM8A central processing unit (CPU)

The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each execution
context), 20 addressing modes including indexed indirect and relative addressing and 80
instructions.

5.1.1 Architecture and registers

● Harvard architecture

● 3-stage pipeline

● 32-bit wide program memory bus with single cycle fetching for most instructions

● X and Y 16-bit index registers, enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

● 8-bit accumulator

● 24-bit program counter with 16-Mbyte linear memory space

● 16-bit stack pointer with access to a 64 Kbyte stack

● 8-bit condition code register with seven condition flags for the result of the last

instruction.

5.1.2 Addressing

● 20 addressing modes

● Indexed indirect addressing mode for look-up tables located anywhere in the address

space

● Stack pointer relative addressing mode for efficient implementation of local variables

and parameter passing

5.1.3 Instruction set

● 80 instructions with 2-byte average instruction size

● Standard data movement and logic/arithmetic functions

● 8-bit by 8-bit multiplication

● 16-bit by 8-bit and 16-bit by 16-bit division

● Bit manipulation

● Data transfer between stack and accumulator (push/pop) with direct stack access

● Data transfer using the X and Y registers or direct memory-to-memory transfers

Doc ID 14395 Rev 9 15/110

Product overview STM8AF52/62xx, STM8AF51/61xx

5.2 Single wire interface module (SWIM) and debug module (DM)

5.2.1 SWIM

The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming. The interface
can be activated in all device operation modes and can be connected to a running device
(hot plugging).The maximum data transmission speed is 145 bytes/ms.

5.2.2 Debug module

The non-intrusive debugging module features a performance close to a full-flavored
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.

● R/W of RAM and peripheral registers in real-time

● R/W for all resources when the application is stopped

● Breakpoints on all program-memory instructions (software breakpoints), except the

interrupt vector table

● Two advanced breakpoints and 23 predefined breakpoint configurations

5.3 Interrupt controller

● Nested interrupts with three software priority levels

● 24 interrupt vectors with hardware priority

● Five vectors for external interrupts (up to 37 depending on the package)

● Trap and reset interrupts

5.4 Flash program and data EEPROM

● 32 Kbytes to 128 Kbytes of high density single voltage Flash program memory

● Up to 2 Kbytes true (not emulated) data EEPROM

● Read while write: writing in the data memory is possible while executing code in the

Flash program memory.

The whole Flash program memory and data EEPROM are factory programmed with 0x00.

5.4.1 Architecture

● The memory is organized in blocks of 128 bytes each

● Read granularity: 1 word = 4 bytes

● Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel

● Writing, erasing, word and block management is handled automatically by the memory

interface.

16/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Product overview

Programmable area from 1 Kbyte

Data

UBC area

Program memory area

Data memory area

(first two pages) up to program memory

EEPROM

Remains write protected during IAP

memory

Write access possible for IAP

Option bytes

end - maximum 128 Kbytes

Flash
program

memory

5.4.2 Write protection (WP)

Write protection in application mode is intended to avoid unintentional overwriting of the
memory. The write protection can be removed temporarily by executing a specific sequence
in the user software.

5.4.3 Protection of user boot code (UBC)

If the user chooses to update the Flash program memory using a specific boot code to
perform in application programming (IAP), this boot code needs to be protected against
unwanted modification.

In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user
option level. Other than the standard write protection, the UBC protection can exclusively be
modified via the debug interface, the user software cannot modify the UBC protection status.

The UBC memory area contains the reset and interrupt vectors and its size can be adjusted
in increments of 512 bytes by programming the UBC and NUBC option bytes
(see Section 9: Option bytes on page 51).

Figure 2. Flash memory organization of STM8A products

5.4.4 Read-out protection (ROP)

The STM8A provides a read-out protection of the code and data memory which can be
activated by an option byte setting (see the ROP option byte in section 10).

The read-out protection prevents reading and writing Flash program memory, data memory
and option bytes via the debug module and SWIM interface. This protection is active in all
device operation modes. Any attempt to remove the protection by overwriting the ROP
option byte triggers a global erase of the program and data memory.

The ROP circuit may provide a temporary access for debugging or failure analysis. The
temporary read access is protected by a user defined, 8-byte keyword stored in the option
byte area. This keyword must be entered via the SWIM interface to temporarily unlock the
device.

Doc ID 14395 Rev 9 17/110

Product overview STM8AF52/62xx, STM8AF51/61xx

If desired, the temporary unlock mechanism can be permanently disabled by the user
through OPT6/NOPT6 option bytes.

5.5 Clock controller

The clock controller distributes the system clock coming from different oscillators to the core
and the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness.

5.5.1 Features

● Clock sources

– 16 MHz high-speed internal RC oscillator (HSI)

– 128 kHz low-speed internal RC (LSI)

– 1-24 MHz high-speed external crystal (HSE)

– Up to 24 MHz high-speed user-external clock (HSE user-ext)

● Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock

(16 MHz/8). The clock source and speed can be changed by the application program
as soon as the code execution starts.

● Safe clock switching: Clock sources can be changed safely on the fly in Run mode

through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.

● Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

● Wakeup: In case the device wakes up from low-power modes, the internal RC

oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device
switches to the clock source that was selected before Halt mode was entered.

● Clock security system (CSS): The CSS permits monitoring of external clock sources

and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.

● Configurable main clock output (CCO): This feature permits to outputs a clock signal

for use by the application.

5.5.2 16 MHz high-speed internal RC oscillator (HSI)

● Default clock after reset 2 MHz (16 MHz/8)

● Fast wakeup time

User trimming

The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign
permits frequency tuning by the application program. The adjustment range covers all
possible frequency variations versus supply voltage and temperature. This trimming does
not change the initial production setting.

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STM8AF52/62xx, STM8AF51/61xx Product overview

5.5.3 128 kHz low-speed internal RC oscillator (LSI)

The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the independent watchdog or the AWU wakeup timer.

In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3/OPT3N, bit LSI_EN).

5.5.4 24 MHz high-speed external crystal oscillator (HSE)

The external high-speed crystal oscillator can be selected to deliver the main clock in
normal Run mode. It operates with quartz crystals and ceramic resonators.

● Frequency range: 1 MHz to 24 MHz

● Crystal oscillation mode: preferred fundamental

● I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT

5.5.5 External clock input

An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 24 MHz.

5.5.6 Clock security system (CSS)

The clock security system protects against a system stall in case of an external crystal clock
failure.

In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8).

Table 6. Peripheral clock gating bits (CLK_PCKENR1)

Control bit Peripheral

PCKEN17 TIM1

PCKEN16 TIM3

PCKEN15 TIM2

PCKEN14 TIM4

PCKEN13 LINUART

PCKEN12 USART

PCKEN11 SPI

PCKEN10 I

2

C

Doc ID 14395 Rev 9 19/110

Product overview STM8AF52/62xx, STM8AF51/61xx

Table 7. Peripheral clock gating bits (CLK_PCKENR2)

Control bit Peripheral

PCKEN27 CAN

PCKEN26 Reserved

PCKEN25 Reserved

PCKEN24 Reserved

PCKEN23 ADC

PCKEN22 AWU

PCKEN21 Reserved

PCKEN20 Reserved

5.6 Low-power operating modes

For efficient power management, the application can be put in one of four different low­power modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.

● Wait mode

In this mode, the CPU is stopped but peripherals are kept running. The wakeup is
performed by an internal or external interrupt or reset.

● Active-halt mode with regulator on

In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is
generated at programmable intervals by the auto wake up unit (AWU). The main
voltage regulator is kept powered on, so current consumption is higher than in Active­halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the
internal AWU interrupt, external interrupt or reset.

● Active-halt mode with regulator off

This mode is the same as Active-halt with regulator on, except that the main voltage
regulator is powered off, so the wake up time is slower.

● Halt mode

CPU and peripheral clocks are stopped, the main voltage regulator is powered off.
Wakeup is triggered by external event or reset.

In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.

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5.7 Timers

5.7.1 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
option bytes. Once the watchdog is activated, it cannot be disabled by the user program
without going through reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window. If the counter is refreshed outside this time window, a reset is
issued.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
option bits, the watchdog is automatically enabled at power-on, and generates a reset
unless the key register is written by software before the counter reaches the end of count.

5.7.2 Auto-wakeup counter

This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by
the internal 128 kHz internal low-frequency RC oscillator or external clock.

LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.

5.7.3 Beeper

This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be
output on a pin. This is useful when audible sounds without interference need to be
generated for use in the application.

5.7.4 Advanced control and general purpose timers

STM8A devices described in this datasheet, contain up to three 16-bit advanced control and
general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can
be used either as input compare, output compare or PWM channel. These timers are
named TIM1, TIM2 and TIM3.

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Product overview STM8AF52/62xx, STM8AF51/61xx

Table 8. Advanced control and general purpose timers

Timer

Counter

width

Counter

type

Prescaler

factor

Channels

Inverted
outputs

Repetition

counter

trigger

unit

External

trigger

TIM1 16-bit Up/down 1 to 65536 4 3 Yes Yes Yes Yes

n

TIM2 16-bit Up

TIM3 16-bit Up

2

n = 0 to 15

n

2

n = 0 to 15

3 None No No No No

2 None No No No No

TIM1 - advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and bridge driver.

● 16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.

● Four independent CAPCOM channels configurable as input capture, output compare,

PWM generation (edge and center aligned mode) and single pulse mode output

● Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In

the present implementation it is possible to trigger the ADC upon a timer event.

● External trigger to change the timer behavior depending on external signals

● Break input to force the timer outputs into a defined state

● Three complementary outputs with adjustable dead time

● Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break

Break

input

TIM2, TIM3 - 16-bit general purpose timers

● 16-bit auto-reload up-counter

● 15-bit prescaler adjustable to fixed power of two ratios 1…32768

● Timers with three or two individually configurable CAPCOM channels

● Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

5.7.5 Basic timer

The typical usage of this timer (TIM4) is the generation of a clock tick.

Table 9. TIM4

Timer

TIM4 8-bit Up

Counter

width

● 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128

● Clock source: master clock

● Interrupt source: 1 x overflow/update

Counter

type

Prescaler

factor

n

2

n = 0 to 7

Channels

Inverted
outputs

Repetition

counter

trigger

unit

External

trigger

0 None No No No No

Break

input

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5.8 Analog to digital converter (ADC)

The STM8A products described in this datasheet contain a 10-bit successive approximation
ADC with up to 16 multiplexed input channels, depending on the package.

The ADC name differs between the datasheet and the STM8A/S reference manual (see

Ta bl e 10).

Table 10. ADC naming

Peripheral name in datasheet

ADC ADC2

ADC features

● 10-bit resolution

● Single and continuous conversion modes

● Programmable prescaler: f

● Conversion trigger on timer events, and external events

● Interrupt generation at end of conversion

● Selectable alignment of 10-bit data in 2 x 8 bit result registers

● Shadow registers for data consistency

● ADC input range: V

●

Schmitt-trigger on analog inputs can be disabled to reduce power consumption

SSA

MASTER

≤ VIN ≤ V

DDA

5.9 Communication interfaces

The following sections give a brief overview of the communication peripheral. Some
peripheral names differ between the datasheet and the STM8A/S reference manual (see

Ta bl e 11).

Table 11. Communication peripheral naming correspondence

Peripheral name in reference manual

(RM0016)

divided by 2 to 18

Peripheral name in datasheet

USART UART1

LINUART UART3

Peripheral name in reference manual

(RM0016)

5.9.1 Universal synchronous/asynchronous receiver transmitter (USART)

The devices covered by this datasheet contain one USART interface. The USART can
operate in standard SCI mode (serial communication interface, asynchronous) or in SPI
emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master
support.

Doc ID 14395 Rev 9 23/110

Product overview STM8AF52/62xx, STM8AF51/61xx

Detailed feature list:

● Full duplex, asynchronous communications

● NRZ standard format (mark/space)

● High-precision baud rate generator system

– Common programmable transmit and receive baud rates up to f

● Programmable data word length (8 or 9 bits)

● Configurable stop bits: Support for 1 or 2 stop bits

● LIN master mode:

MASTER

/16

– LIN break and delimiter generation

– LIN break and delimiter detection with separate flag and interrupt source for

readback checking.

● Transmitter clock output for synchronous communication

● Separate enable bits for transmitter and receiver

● Transfer detection flags:

– Receive buffer full

– Transmit buffer empty

– End of transmission flags

● Parity control:

– Transmits parity bit

– Checks parity of received data byte

● Four error detection flags:

– Overrun error

– Noise error

–Frame error

– Parity error

● Six interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Parity error

– LIN break and delimiter detection

● Two interrupt vectors:

– Transmitter interrupt

– Receiver interrupt

● Reduced power consumption mode

● Wakeup from mute mode (by idle line detection or address mark detection)

● Two receiver wakeup modes:

– Address bit (MSB)

– Idle line

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STM8AF52/62xx, STM8AF51/61xx Product overview

5.9.2 Universal asynchronous receiver/transmitter with LIN support (LINUART)

The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
communication interface which supports extensive LIN functions tailored for LIN slave
applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.

Detailed feature list:

LIN mode

Master mode

● LIN break and delimiter generation

● LIN break and delimiter detection with separate flag and interrupt source for read back

checking.

Slave mode

● Autonomous header handling – one single interrupt per valid header

● Mute mode to filter responses

● Identifier parity error checking

● LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)

clock source

● Break detection at any time, even during a byte reception

● Header errors detection:

– Delimiter too short

– Synch field error

– Deviation error (if automatic resynchronization is enabled)

– Framing error in synch field or identifier field

– Header time-out

UART mode

● Full duplex, asynchronous communications - NRZ standard format (mark/space)

● High-precision baud rate generator

– A common programmable transmit and receive baud rates up to f

● Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control

● Separate enable bits for transmitter and receiver

● Error detection flags

● Reduced power consumption mode

● Multi-processor communication - enter mute mode if address match does not occur

● Wakeup from mute mode (by idle line detection or address mark detection)

● Two receiver wakeup modes:

MASTER

– Address bit (MSB)

– Idle line

Doc ID 14395 Rev 9 25/110

/16

Product overview STM8AF52/62xx, STM8AF51/61xx

5.9.3 Serial peripheral interface (SPI)

The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.

● Maximum speed: 8 Mbit/s or f

● Full duplex synchronous transfers

● Simplex synchronous transfers on two lines with a possible bidirectional data line

● Master or slave operation - selectable by hardware or software

● CRC calculation

● 1 byte Tx and Rx buffer

● Slave mode/master mode management by hardware or software for both master and

MASTER

slave

● Programmable clock polarity and phase

● Programmable data order with MSB-first or LSB-first shifting

● Dedicated transmission and reception flags with interrupt capability

● SPI bus busy status flag

● Hardware CRC feature for reliable communication:

– CRC value can be transmitted as last byte in Tx mode

– CRC error checking for last received byte

/2 both for master and slave

5.9.4 Inter integrated circuit (I2C) interface

The devices covered by this datasheet contain one I2C interface. The interface is available
on all the supported packages.

2

● I

C master features:

– Clock generation

– Start and stop generation

2

● I

C slave features:

– Programmable I

– Stop bit detection

● Generation and detection of 7-bit/10-bit addressing and general call

● Supports different communication speeds:

– Standard speed (up to 100 kHz),

– Fast speed (up to 400 kHz)

● Status flags:

– Transmitter/receiver mode flag

– End-of-byte transmission flag

2

–I

C busy flag

● Error flags:

– Arbitration lost condition for master mode

– Acknowledgement failure after address/data transmission

– Detection of misplaced start or stop condition

– Overrun/underrun if clock stretching is disabled

2

C address detection

26/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Product overview

● Interrupt:

– Successful address/data communication

– Error condition

– Wakeup from Halt

● Wakeup from Halt on address detection in slave mode

5.9.5 Controller area network interface (beCAN)

The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the
CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile
filter bank. Together with a filter match index, this allows a very efficient message handling in
today’s car network architectures. The CPU is significantly unloaded. The maximum
transmission speed is 1 Mbit/s.

Transmission

● Three transmit mailboxes

● Configurable transmit priority by identifier or order request

Reception

● 11- and 29-bit ID

● 1 receive FIFO (3 messages deep)

● Software-efficient mailbox mapping at a unique address space

● FMI (filter match index) stored with message for quick message association

● Configurable FIFO overrun

● Time stamp on SOF reception

● 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking

configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID.

● Filtering modes (mixable):

– Mask mode permitting ID range filtering

– ID list mode

Interrupt management

● Maskable interrupt

● Software-efficient mailbox mapping at a unique address space

Doc ID 14395 Rev 9 27/110

Product overview STM8AF52/62xx, STM8AF51/61xx

5.10 Input/output specifications

The product features four I/O types:

● Standard I/O 2 MHz

● Fast I/O up to 10 MHz

● High sink 8 mA, 2 MHz

● True open drain (I

To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum
slew rate. The rise and fall times are similar to those of standard I/Os.

The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt­trigger input stage on the analog I/Os can be disabled in order to reduce the device standby
consumption.

STM8A I/Os are designed to withstand current injection. For a negative injection current of
4

mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to

this feature, external protection diodes against current injection are no longer required.

2

C interface)

28/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Pinouts and pin description

PD4 (HS)/TIM2_CH1/BEEP

2

1

3
4
5
6
7
8

10

9

12

14

16

18

20

11

15

13

17

19

2526282730

32

34

36

38

29

33

31

35

37

39

57

58

56
55
54
53
52
51

49

50

47

45

43

41

48

44

46

42

60
59

61

62

63

64

666865

67

69

70

71

727473

75

76

77

78

79

80

PI4

PI3
PI2
PI1

PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1

PG6

PG5

PI5

PI0
PG4
PG3
PG2

PC7/SPI_MISO

V

SSIO_2

V

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

AIN12/PF4

V

SSIO_1

V

SS

VCAP

V

DD

USART_CK/PA6

(HS) PH0

(HS) PH1

PH2

PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5

NRST

OSCIN/PA1

OSCOUT/PA2

AIN5/PB5

AIN4/PB4

AIN1/PB1

AIN0/PB0

AIN8/PE7

V

REF-

AIN10/PF0

AIN7/PB7

AIN6/PB6

TIM1_ETR/PH4

TIM1_CH3N/PH5

TIM1_CH2N/PH6

40

AIN9/PE6

212224

23

AIN11/PF3

V

REF+

V

DDA

V

SSA

PD0 (HS)/TIM3_CH2

PE2/I 2C_SDA

PE3/TIM1_BKIN

PE4

PG7

PD7/TLI

PD6/LINUART_RX

PD5/LINUART_TX

PI7

PI6

PD2 (HS)/TIM3_CH1

PD1 (HS)/SWIM

PC5/SPI_SCK

PC6/SPI_MOSI

PG0/CAN_TX

(1)

PG1/CAN_RX

(1)

PE0/CLK_CCO

PD3 (HS)/TIM2_CH2

AIN3/PB3

AIN2/PB2

PC0/ADC_ETR
PE5/SPI_NSS

TIM1_CH1N/PH7

V

DDIO_2

PE1/I2C_SCL

6 Pinouts and pin description

6.1 Package pinouts

Figure 3. LQFP 80-pin pinout

1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.

2. (HS) stands for high sink capability.

Doc ID 14395 Rev 9 29/110

Pinouts and pin description STM8AF52/62xx, STM8AF51/61xx

V

REF-

AIN10/PF0

AIN7/PB7

AIN6/PB6

AIN5/PB5

AIN4/PB4

TIM1_ETR/AIN3/PB3

TIM1_CH3N/AIN2/PB2

TIM1_CH2N/AIN1/PB1

TIM1_CH1N/AIN0/PB0

AIN8/PE7

AIN9/PE6

AIN11/PF3

V

REF+

V

DDA

V

SSA

64 63 6261 60 5958 57 56 55 5453 52 51 50 49

48

47
46
45
44
43

42

41

40

39

38

37

36

35

34

33

17 18 1920 2122 2324 2930 31 3225 26 2728

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

V

SS

VCAP

V

DD

V

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

USART_CK/PA6

AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4

NRST

OSCIN/PA1

OSCOUT/PA2

V

SSIO_1

PG1/CAN_RX

(1)

PG0/CAN_TX

(1)

PC7/SPI_MISO
PC6/SPI_MOSI
V

DDIO_2

V

SSIO_2

PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS

PI0
PG4
PG3
PG2

PD3 (HS)/TIM2_CH2/ADC_ETR

PD2 (HS)/TIM3_CH1

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2

PE0/CLK_CCO

PE1/I2C_SCL

PE2/I2C_SDA

PE3/TIM1_BKIN

PE4

PG7

PG6

PG5

PD7/TLI

PD6/LINUART_RX

PD5/LINUART_TX

PD4 (HS)/TIM2_CH1/ BEEP

Figure 4. LQFP 64-pin pinout

1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.

2. HS stands for high sink capability.

30/110 Doc ID 14395 Rev 9

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44 43 42 41 4039 38 37

36
35

34
33
32
31
30
29
28
27
26
25

24

23

12

13 14 1516 1718 1920 21 22

1
2
3
4
5
6
7
8
9
10
11

48 4746 45

USART_CK/PA6

AIN8/PE7

PC1 (HS)/TIM1_CH1
PE5/SPI_NSS

PG1/CAN_Rx

AIN9/PE6

PD3 (HS)/TIM2_CH2/ADC_ETR

PD2 (HS)/TIM3_CH1

PE0/CLK_CCO

PE1/I

2

C_SCL

PE2/I

2

C_SDA

PE3/TIM1_BKIN

PD7/TLI

PD6/LINUART_RX

PD5/LINUART_TX

PD4 (HS)/TIM2_CH1/BEEP

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2

V

SSIO_2

PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2

PG0/CAN_Tx
PC7/SPI_MISO
PC6/SPI_MOSI
V

DDIO_2

AIN7/PB7

AIN6/PB6

AIN5/PB5

AIN4/PB4

TIM1_ETR/AIN3/PB3

TIM1_CH3N/AIN2/PB2

TIM1_CH2N/AIN1/PB1

TIM1_CH1N/AIN0/PB0

V

DDA

V

SSA

V

SS

VCAP

V

DD

V

DDIO_1

TIM2_CH3/PA3

USART_RX/PA4

USART_TX/PA5

NRST

OSCIN/PA1

OSCOUT/PA2

V

SSIO_1

Figure 5. LQFP 48-pin pinout

1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.

2. HS stands for high sink capability.

Doc ID 14395 Rev 9 31/110

Pinouts and pin description STM8AF52/62xx, STM8AF51/61xx

I2C_SCL/AIN4/PB4

TIM1_ETR/AIN3/PB3

TIM1_CH3N/AIN2/PB2

TIM1_CH2N/AIN1/PB1

TIM1_CH1N/AIN0/PB0

V

DDA

V

SSA

I2C_SDA/AIN5/PB5

32 31 3029 28 2726 25

24
23
22
21
20
19
18
17

9 10111213141516

1
2
3
4
5
6
7
8

VCAP

V

DD

V

DDIO

AIN12/PF4

NRST

OSCIN/PA1

OSCOUT/PA2

V

SS

PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS

PC7/SPI_MISO
PC6/SPI_MOSI
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4

PD3 (HS)/TIM2_CH2/ADC_ETR

PD2 (HS)/TIM3_CH1/TIM2_CH3

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2/CLK_CCO/TIM1_BRK

PD7/TLI

PD6/LINUART_RX

PD5/LINUART_TX

PD4 (HS)/TIM2_CH1/BEEP

Figure 6. LQFP/VFQFPN 32-pin pinout

1. HS stands for high sink capability.

Table 12. Legend/abbreviation for the pin description table

Type I= input, O = output, S = power supply

Input CM = CMOS (standard for all I/Os)

Level

Output HS = high sink (8 mA)

O1 = Standard (up to 2 MHz)

Output speed

O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset

Port and control
configuration

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).

32/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Pinouts and pin description

Table 13. STM8A microcontroller family pin description

Pin number

LQFP80

Input Output

Main

OD

function

(after

PP

reset)

Pin name

LQFP64

LQFP48

Typ e

wpu

floating

Speed

High sink

Ext. interrupt

Default
alternate
function

Alternate

function

after remap

[option bit]

LQFP32/VFQFPN32

1 1 1 1 NRST I/O - X — — — — — Reset —

2222 PA1/OSCIN

(1)

I/O X X——O1X XPort A1

3 3 3 3 PA2/OSCOUT I/O X XX—O1XXPort A2

444- V

5554 V

SSIO_1

SS

S — — — — — — — I/O ground —

S — — — — — — — Digital ground —

Resonator/

crystal in

Resonator/

crystal out

6 6 6 5 VCAP S — — — — — — — 1.8 V regulator capacitor —

7776 V

8887 V

DD

DDIO_1

9 9 9 - PA3/TIM2_CH3 I/O X XX—O1XXPort A3

10 10 10 - PA4/USART_RX I/O X XX—O3XXPort A4

11 11 11 - PA5/USART_TX I/O X XX—O3XXPort A5

S — — — — — — — Digital power supply —

S — — — — — — — I/O power supply —

Timer 2 -

TIM3_CH1

channel 3

USART

receive

USART

transmit

—

—

[AFR1]

—

—

USART

12 12 12 - PA6/USART_CK I/O X XX—O3XXPort A6

synchronous

—

clock

13--- PH0 I/OXX—HSO3XXPort H0 ——

14--- PH1 I/OX X—HSO3X XPort H1 ——

15--- PH2 I/OX X——O1X XPort H2 ——

16--- PH3 I/OX X——O1X XPort H3 ——

17 13 - - PF7/AIN15 I/O X X——O1X XPort F7

18 14 - - PF6/AIN14 I/O X X——O1X XPort F6

19 15 - - PF5/AIN13 I/O X X——O1X XPort F5

20 16 - 8 PF4/AIN12 I/O X X——O1X XPort F4

21 17 - - PF3/AIN11 I/O X X——O1X XPort F3

Analog

input 15

Analog

input 14

Analog

input 13

Analog

input 12

Analog

input 11

—

—

—

—

—

Doc ID 14395 Rev 9 33/110

Pinouts and pin description STM8AF52/62xx, STM8AF51/61xx

Table 13. STM8A microcontroller family pin description (continued)

Pin number

LQFP80

LQFP64

LQFP48

Pin name

Input Output

Typ e

wpu

floating

Ext. interrupt

High sink

Speed

OD

Main

function

(after

PP

reset)

Default
alternate
function

LQFP32/VFQFPN32

22 18 - - V

23 19 13 9 V

24 20 14 10 V

25 21 - - V

REF+

DDA

SSA

REF-

S———————

S — — — — — — — Analog power supply —

S — — — — — — — Analog ground —

S———————

26 22 - - PF0/AIN10 I/O X X——O1X XPort F0

27 23 15 - PB7/AIN7 I/O X XX—O1XXPort B7

28 24 16 - PB6/AIN6 I/O X XX—O1XXPort B6

29 25 17 11 PB5/AIN5 I/O X XX—O1XXPort B5

30 26 18 12 PB4/AIN4 I/O X XX—O1XXPort B4

31 27 19 13 PB3/AIN3 I/O X XX—O1XXPort B3

ADC positive reference

voltage

ADC negative reference

voltage

Analog

input 10

Analog input

7

Analog input

6

Analog input 5I

Analog input 4I

Analog input 3TIM1_ETR

32 28 20 14 PB2/AIN2 I/O X XX—O1XXPort B2 Analog input

Alternate

function

after remap

[option bit]

—

—

—

—

—

2

C_SDA

[AFR6]

2

C_SCL

[AFR6]

[AFR5]

TIM1_CH3N

[AFR5]

33 29 21 15 PB1/AIN1 I/O X XX—O1XXPort B1

34 30 22 16 PB0/AIN0 I/O X XX—O1XXPort B0

35 - - - PH4/TIM1_ETR I/O X X——O1X XPor t H4

36---

37---

38---

PH5/

TIM1_CH3N

PH6/

TIM1_CH2N

PH7/

TIM1_CH1N

I/O X X——O1X XPort H5

I/O X X——O1X XPort H6

I/O X X——O1X XPort H7

34/110 Doc ID 14395 Rev 9

Analog input 1TIM1_CH2N

[AFR5]

Analog input 0TIM1_CH1N

[AFR5]

Timer 1 -

trigger input

—

Timer 1 -

inverted

—

channel 3

Timer 1 -

inverted

—

channel 2

Timer 1 -

inverted

—

channel 2

STM8AF52/62xx, STM8AF51/61xx Pinouts and pin description

Table 13. STM8A microcontroller family pin description (continued)

Pin number

Input Output

Main

OD

function

(after

PP

reset)

LQFP80

LQFP64

LQFP48

Pin name

Typ e

wpu

floating

Speed

High sink

Ext. interrupt

LQFP32/VFQFPN32

39 31 23 - PE7/AIN8 I/O X X——O1X XPort E7

40 32 24 PE6/AIN9 I/O X XX—O1XXPor t E7

41 33 25 17 PE5/SPI_NSS I/O X XX—O1XXPor t E5

42 - - - PC0/ADC_ETR I/O X XX—O1XXPort C0

43 34 26 18 PC1/TIM1_CH1 I/O X XXHSO3XXPort C1

44 35 27 19 PC2/TIM1_CH2 I/O X XXHSO3XXPort C2

45 36 28 20 PC3/TIM1_CH3 I/O X XXHSO3XXPort C3

46 37 29 21 PC4/TIM1_CH4 I/O X XXHSO3XXPort C4

Default
alternate
function

Analog input

8

Analog input

9

SPI master/
slave select

ADC trigger

input

Timer 1 -

channel 1

Timer 1-

channel 2

Timer 1 -

channel 3

Timer 1 -

channel 4

Alternate

function

after remap

[option bit]

—

—

—

—

—

—

—

—

47 38 30 22 PC5/SPI_SCK I/O X XX—O3XXPort C5 SPI clock —

48 39 31 - V

49 40 32 - V

SSIO_2

DDIO_2

S — — — — — — — I/O ground —

S — — — — — — — I/O power supply —

SPI master

50 41 33 23 PC6/SPI_MOSI I/O X XX—O3XXPort C6

out/

—

slave in

51 42 34 24 PC7/SPI_MISO I/O X XX—O3XXPort C7

SPI master

in/ slave out

—

52 43 35 - PG0/CAN_Tx I/O X X——O1X XPort G0 CAN transmit —

53 44 36 - PG1/CAN_Rx I/O X X——O1X XPort G1 CAN receive —

54 45 - - PG2 I/O X X——O1X XPort G2 ——

55 46 - - PG3 I/O X X——O1X XPort G3 ——

56 47 - - PG4 I/O X X——O1X XPort G4 ——

57 48 - - PI0 I/O X X——O1X XPor t I0 ——

58--- PI1 I/OX X——O1X X Port I1 ——

59--- PI2 I/OX X——O1X X Port I2 ——

60--- PI3 I/OX X——O1X X Port I3 ——

Doc ID 14395 Rev 9 35/110

Pinouts and pin description STM8AF52/62xx, STM8AF51/61xx

Table 13. STM8A microcontroller family pin description (continued)

Pin number

LQFP80

LQFP64

LQFP48

Pin name

Input Output

Typ e

wpu

floating

Ext. interrupt

High sink

Speed

OD

Main

function

(after

PP

reset)

Default
alternate
function

Alternate

function

after remap

[option bit]

LQFP32/VFQFPN32

61--- PI4 I/OX X——O1X X Port I4 ——

62--- PI5 I/OX X——O1X X Port I5 ——

63 49 - - PG5 I/O X X——O1X XPort G5 ——

64 50 - - PG6 I/O X X——O1X XPort G6 ——

65 51 - - PG7 I/O X X——O1X XPort G7 ——

66 52 - - PE4 I/O X XX—O1XXPort E4 ——

67 53 37 - PE3/TIM1_BKIN I/O X XX—O1XXPort E3

68 54 38 - PE2/I

69 55 39 - PE1/I

2

C_SDA I/O X —X—O1T

2

C_SCL I/O X —X—O1T

(2)

- Port E2 I2C data —

(2)

- Port E1 I2C clock —

70 56 40 - PE0/CLK_CCO I/O X XX—O3XXPort E0

Timer 1 -

break input

Configurable

clock output

—

—

71--- PI6 I/OX X——O1X X Port I6 ——

72--- PI7 I/OX X——O1X X Port I7 ——

73 57 41 25 PD0/TIM3_CH2 I/O X XXHSO3XXPort D0

(3)

74 58 42 26 PD1/SWIM

I/O X X XHSO4X XPort D1

75 59 43 27 PD2/TIM3_CH1 I/O X XXHSO3XXPort D2

76 60 44 28 PD3/TIM2_CH2 I/O X XXHSO3XXPort D3

77 61 45 29

78 62 46 30

79 63 47 31

PD4/TIM2_CH1/

BEEP

PD5/

LINUART_TX

PD6/

LINUART_RX

I/O X XXHSO3XXPort D4

I/O X XX—O1XXPort D5

I/O

X

XX—O1XX

Port D6

X

(4)

80 64 48 32 PD7/TLI

I/O X XX—O1XXPort D7

Timer 3 -

channel 2

SWIM data

interface

Timer 3 -

channel 1

Timer 2 -

channel 2

Timer 2 -

channel 1

LINUART

data transmit

LINUART

data receive

Top level

interrupt

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

—

TIM2_CH3

[AFR1]

ADC_ETR

[AFR0]

BEEP output

[AFR7]

—

—

—

36/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Pinouts and pin description

1. In Halt/Active-halt mode, this pin behaves as follows:

- The input/output path is disabled.

- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.

- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the
corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in
Halt/Active-halt mode.

2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to V
not implemented)

3. The PD1 pin is in input pull-up during the reset phase and after reset release.

4. If this pin is configured as interrupt pin, it will trigger the TLI.

DD

are

6.2 Alternate function remapping

As shown in the rightmost column of Ta b le 13, some alternate functions can be remapped at
different I/O ports by programming one of eight AFR (alternate function remap) option bits.
Refer to
default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the STM8S and STM8A microcontroller families reference manual,
RM0016).

Section 9: Option bytes on page 51. When the remapping option is active, the

Doc ID 14395 Rev 9 37/110

Memory and register map STM8AF52/62xx, STM8AF51/61xx

Up to 2 Kbytes data EEPROM

Option bytes

HW registers

2 Kbytes boot ROM

CPU/SWIM/Debug/ITC registers

IT vectors

Up to 128 Kbytes

00 0000

RAM end address

00 4000

00 4800

00 5000

00 5800

00 6000

00 6800

00 7F00

00 8000

Memory end address

00 8080

Reserved

Reserved

Stack

Up to 6 Kbytes RAM

00 4900

Reserved

Flash program memory

7 Memory and register map

7.1 Memory map

Figure 7. Register and memory map

Table 14. Memory model 128K

Flash program

memory size

Flash program

memory end

address

RAM size

128K 0x00 27FFF

1. If the device contains the super set silicon (salestype contains SSS), the roll-over address is the same as

38/110 Doc ID 14395 Rev 9

96K 0x00 1FFFF 0x00 17FF 0x00 1400

64K 0x00 17FFF 0x00 17FF 0x00 1400

48K 0x00 13FFF 3K 0x00 0BFF n/a

32K 0x00 0FFFF 6K 0x00 17FF 0x00 1400

on the 128K device. For more information on stack handling refer to the “Memory and register map” section
in the reference manual RM0016. For more information on salestype composition, refer to section 13 in the
present document.

6K

RAM end

address

Stack roll-over

address

0x00 17FF 0x00 1400

(1)

STM8AF52/62xx, STM8AF51/61xx Memory and register map

7.2 Register map

In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to the
reference manual RM0016.

Table 15. I/O port hardware register map

Address Block Register label Register name

0x00 5000

PA_ODR Port A data output latch register 0x00

Reset

status

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

Por t A

0x00 5003 PA_CR1 Port A control register 1 0x00

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

Por t B

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PB_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

Por t C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

Por t D

0x00 5012 PD_CR1 Port D control register 1 0x02

(1)

(1)

(1)

(1)

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX

0x00 5016 PE_DDR Port E data direction register 0x00

Por t E

0x00 5017 PE_CR1 Port E control register 1 0x00

0x00 5018 PE_CR2 Port E control register 2 0x00

0x00 5019

PF_ODR Port F data output latch register 0x00

0x00 501A PF_IDR Port F input pin value register 0xXX

0x00 501B PF_DDR Port F data direction register 0x00

Por t F

0x00 501C PF_CR1 Port F control register 1 0x00

0x00 501D PF_CR2 Port F control register 2 0x00

Doc ID 14395 Rev 9 39/110

(1)

(1)

Memory and register map STM8AF52/62xx, STM8AF51/61xx

Table 15. I/O port hardware register map (continued)

Address Block Register label Register name

0x00 501E

PG_ODR Port G data output latch register 0x00

status

0x00 501F PG_IDR Port G input pin value register 0xXX

0x00 5020 PG_DDR Port G data direction register 0x00

Por t G

0x00 5021 PG_CR1 Port G control register 1 0x00

0x00 5022 PG_CR2 Port G control register 2 0x00

0x00 5023

PH_ODR Port H data output latch register 0x00

0x00 5024 PH_IDR Port H input pin value register 0xXX

0x00 5025 PH_DDR Port H data direction register 0x00

Por t H

0x00 5026 PH_CR1 Port H control register 1 0x00

0x00 5027 PH_CR2 Port H control register 2 0x00

0x00 5028

PI_ODR Port I data output latch register 0x00

0x00 5029 PI_IDR Port I input pin value register 0xXX

0x00 502A PI_DDR Port I data direction register 0x00

Por t I

0x00 502B PI_CR1 Port I control register 1 0x00

0x00 502C PI_CR2 Port I control register 2 0x00

1. Depends on the external circuitry.

Reset

(1)

(1)

(1)

Table 16. General hardware register map

Address Block Register label Register name

0x00 505A

FLASH_CR1 Flash control register 1 0x00

status

0x00 505B FLASH_CR2 Flash control register 2 0x00

0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF

0x00 505D FLASH_FPR Flash protection register 0x00

0x00 505E FLASH_NFPR

0x00 505F FLASH_IAPSR

0x00 5060 to

0x005061

0x00 5062 Flash FLASH_PUKR

Flash

Flash complementary protection

register

Flash in-application programming
status register

Reserved area (2 bytes)

Flash Program memory unprotection
register

0x00 5063 Reserved area (1 byte)

0x00 5064 Flash FLASH_DUKR Data EEPROM unprotection register 0x00

0x00 5065 to

0x00 509F

Reserved area (59 bytes)

Reset

0xFF

0x40

0x00

40/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Memory and register map

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 50A0

EXTI_CR1 External interrupt control register 1 0x00

Reset

status

ITC

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 to

0x00 50B2

Reserved area (17 bytes)

0x00 50B3 RST RST_SR Reset status register 0xXX

0x00 50B4 to

0x00 50BF

0x00 50C0

CLK_ICKR Internal clock control register 0x01

Reserved area (12 bytes)

CLK

0x00 50C1 CLK_ECKR External clock control register 0x00

0x00 50C2 Reserved area (1 byte)

0x00 50C3

CLK_CMSR Clock master status register 0xE1

0x00 50C4 CLK_SWR Clock master switch register 0xE1

0x00 50C5 CLK_SWCR Clock switch control register 0xXX

0x00 50C6 CLK_CKDIVR Clock divider register 0x18

0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF

0x00 50C8 CLK_CSSR Clock security system register 0x00

CLK

0x00 50C9 CLK_CCOR Configurable clock control register 0x00

(1)

0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF

0x00 50CB Reserved area (1 byte)

0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00

0x00 50CD CLK_SWIMCCR SWIM clock control register

0x00 50CE

to 0x00 50D0

0x00 50D1

WWDG_CR WWDG control register 0x7F

Reserved area (3 bytes)

0bXXXX

XXX0

WWDG

0x00 50D2 WWDG_WR WWDR window register 0x7F

0x00 50D3 to

0x00 50DF

0x00 50E0

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

IWDG

IWDG_KR IWDG key register 0xXX

Reserved area (13 bytes)

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1 AWU_APR

AWU

AWU_CSR1 AWU control/status register 1 0x00

Reserved area (13 bytes)

AWU asynchronous prescaler buffer

register

0x3F

0x00 50F2 AWU_TBR AWU timebase selection register 0x00

(2)

Doc ID 14395 Rev 9 41/110

Memory and register map STM8AF52/62xx, STM8AF51/61xx

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F

0x00 50F4 to

0x00 50FF

0x00 5200

0x00 5201 SPI_CR2 SPI control register 2 0x00

0x00 5202 SPI_ICR SPI interrupt control register 0x00

0x00 5203 SPI_SR SPI status register 0x02

SPI

0x00 5204 SPI_DR SPI data register 0x00

0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07

0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF

0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211 I2C_CR2 I2C control register 2 0x00

0x00 5212 I2C_FREQR I2C frequency register 0x00

0x00 5213 I2C_OARL I2C own address register low 0x00

0x00 5214 I2C_OARH I2C own address register high 0x00

SPI_CR1 SPI control register 1 0x00

I2C_CR1 I2C control register 1 0x00

Reserved area (12 bytes)

Reserved area (8 bytes)

Reset

status

0x00 5215

0x00 5216 I2C_DR I2C data register 0x00

0x00 5217 I2C_SR1 I2C status register 1 0x00

0x00 5218 I2C_SR2 I2C status register 2 0x00

0x00 5219 I2C_SR3 I2C status register 3 0x00

0x00 521A I2C_ITR I2C interrupt control register 0x00

0x00 521B I2C_CCRL I2C clock control register low 0x00

0x00 521C I2C_CCRH I2C clock control register high 0x00

0x00 521D I2C_TRISER I2C TRISE register 0x02

0x00 521E to

0x00 522F

I2C

Reserved area (18 bytes)

42/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Memory and register map

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 5230

0x00 5231 UART1_DR USART data register 0xXX

0x00 5232 UART1_BRR1 USART baud rate register 1 0x00

0x00 5233 UART1_BRR2 USART baud rate register 2 0x00

0x00 5234 UART1_CR1 USART control register 1 0x00

0x00 5235 UART1_CR2 USART control register 2 0x00

0x00 5236 UART1_CR3 USART control register 3 0x00

0x00 5237 UART1_CR4 USART control register 4 0x00

0x00 5238 UART1_CR5 USART control register 5 0x00

0x00 5239 UART1_GTR USART guard time register 0x00

0x00 523A UART1_PSCR USART prescaler register 0x00

0x00 523B to

0x00 523F

0x00 5240

0x00 5241 UART3_DR LINUART data register 0xXX

0x00 5242 UART3_BRR1 LINUART baud rate register 1 0x00

0x00 5243 UART3_BRR2 LINUART baud rate register 2 0x00

USART

UART1_SR USART status register 0xC0

Reserved area (5 bytes)

UART3_SR LINUART status register 0xC0

Reset

status

0x00 5244 UART3_CR1 LINUART control register 1 0x00

0x00 5245 UART3_CR2 LINUART control register 2 0x00

0x00 5246 UART3_CR3 LINUART control register 3 0x00

0x00 5247 UART3_CR4 LINUART control register 4 0x00

0x00 5248 Reserved

0x00 5249 UART3_CR6 LINUART control register 6 0x00

0x00 524A to

0x00 524F

LINUART

Reserved area (6 bytes)

Doc ID 14395 Rev 9 43/110

Memory and register map STM8AF52/62xx, STM8AF51/61xx

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 5250

0x00 5251 TIM1_CR2 TIM1 control register 2 0x00

0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00

0x00 5253 TIM1_ETR TIM1 external trigger register 0x00

0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00

0x00 5255 TIM1_SR1 TIM1 status register 1 0x00

0x00 5256 TIM1_SR2 TIM1 status register 2 0x00

0x00 5257 TIM1_EGR TIM1 event generation register 0x00

0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00

0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00

0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00

0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00

0x00 525C TIM1_CCER1

0x00 525D TIM1_CCER2

0x00 525E TIM1_CNTRH TIM1 counter high 0x00

0x00 525F TIM1_CNTRL TIM1 counter low 0x00

0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00

0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00

TIM1

TIM1_CR1 TIM1 control register 1 0x00

TIM1 capture/compare enable register

1

TIM1 capture/compare enable register

2

Reset

status

0x00

0x00

0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF

0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF

0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00

0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00

0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00

0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00

0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00

0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00

0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00

0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00

0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00

0x00 526D TIM1_BKR TIM1 break register 0x00

0x00 526E TIM1_DTR TIM1 dead-time register 0x00

0x00 526F TIM1_OISR TIM1 output idle state register 0x00

44/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Memory and register map

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 5270 to

0x00 52FF

0x00 5300

0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5302 TIM2_SR1 TIM2 status register 1 0x00

0x00 5303 TIM2_SR2 TIM2 status register 2 0x00

0x00 5304 TIM2_EGR TIM2 event generation register 0x00

0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00

0x00 5308 TIM2_CCER1

0x00 5309 TIM2_CCER2

TIM2

0x00 530A TIM2_CNTRH TIM2 counter high 0x00

0x00 530B TIM2_CNTRL TIM2 counter low 0x00

00 530C0x TIM2_PSCR TIM2 prescaler register 0x00

TIM2_CR1 TIM2 control register 1 0x00

Reserved area (147 bytes)

TIM2 capture/compare enable register

1

TIM2 capture/compare enable register

2

Reset

status

0x00

0x00

0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF

0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF

0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00

0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00

0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00

0x00 5315 to

0x00 531F

Reserved area (11 bytes)

Doc ID 14395 Rev 9 45/110

Memory and register map STM8AF52/62xx, STM8AF51/61xx

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 5320

0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00

0x00 5322 TIM3_SR1 TIM3 status register 1 0x00

0x00 5323 TIM3_SR2 TIM3 status register 2 0x00

0x00 5324 TIM3_EGR TIM3 event generation register 0x00

0x00 5325 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00

0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00

0x00 5327 TIM3_CCER1

0x00 5328 TIM3_CNTRH TIM3 counter high 0x00

0x00 5329 TIM3_CNTRL TIM3 counter low 0x00

0x00 532A TIM3_PSCR TIM3 prescaler register 0x00

0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF

0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF

0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00

0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00

0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00

TIM3

TIM3_CR1 TIM3 control register 1 0x00

TIM3 capture/compare enable register

1

Reset

status

0x00

0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00

0x00 5331 to

0x00 533F

0x00 5340

0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00

0x00 5342 TIM4_SR TIM4 status register 0x00

0x00 5343 TIM4_EGR TIM4 event generation register 0x00

0x00 5344 TIM4_CNTR TIM4 counter 0x00

0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00

0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF

0x00 5347 to

0x00 53FF

TIM4

TIM4_CR1 TIM4 control register 1 0x00

Reserved area (15 bytes)

Reserved area (185 bytes)

46/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Memory and register map

Table 16. General hardware register map (continued)

Address Block Register label Register name

0x00 5400

ADC _CSR ADC control/status register 0x00

Reset

status

0x00 5401 ADC_CR1 ADC configuration register 1 0x00

0x00 5402 ADC_CR2 ADC configuration register 2 0x00

0x00 5403 ADC_CR3 ADC configuration register 3 0x00

0x00 5404 ADC_DRH ADC data register high 0xXX

ADC

0x00 5405 ADC_DRL ADC data register low 0xXX

0x00 5406 ADC_TDRH

0x00 5407 ADC_TDRL

0x00 5408 to

0x00 541F

0x00 5420

CAN_MCR CAN master control register 0x02

ADC Schmitt trigger disable register

high

ADC Schmitt trigger disable register

low

Reserved area (24 bytes)

0x00

0x00

0x00 5421 CAN_MSR CAN master status register 0x02

0x00 5422 CAN_TSR CAN transmit status register 0x00

0x00 5423 CAN_TPR CAN transmit priority register 0x0C

0x00 5424 CAN_RFR CAN receive FIFO register 0x00

0x00 5425 CAN_IER CAN interrupt enable register 0x00

0x00 5426 CAN_DGR CAN diagnosis register 0x0C

0x00 5427 CAN_FPSR CAN page selection register 0x00

0x00 5428 CAN_P0 CAN paged register 0 0xXX

0x00 5429 CAN_P1 CAN paged register 1 0xXX

0x00 542A CAN_P2 CAN paged register 2 0xXX

0x00 542B CAN_P3 CAN paged register 3 0xXX

beCAN

0x00 542C CAN_P4 CAN paged register 4 0xXX

0x00 542D CAN_P5 CAN paged register 5 0xXX

0x00 542E CAN_P6 CAN paged register 6 0xXX

0x00 542F CAN_P7 CAN paged register 7 0xXX

0x00 5430 CAN_P8 CAN paged register 8 0xXX

0x00 5431 CAN_P9 CAN paged register 9 0xXX

0x00 5432 CAN_PA CAN paged register A 0xXX

0x00 5433 CAN_PB CAN paged register B 0xXX

0x00 5434 CAN_PC CAN paged register C 0xXX

0x00 5435 CAN_PD CAN paged register D 0xXX

0x00 5436 CAN_PE CAN paged register E 0xXX

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

Doc ID 14395 Rev 9 47/110

Memory and register map STM8AF52/62xx, STM8AF51/61xx

Table 16. General hardware register map (continued)

Address Block Register label Register name

status

0x00 5437 beCAN CAN_PF CAN paged register F 0xXX

0x00 5438 to

0x00 57FF

1. Depends on the previous reset source.

2. Write only register.

3. If the bootloader is enabled, it is initialized to 0x00.

Table 17. CPU/SWIM/debug module/interrupt controller registers

Address Block Register label Register name

0x00 7F00

A Accumulator 0x00

Reserved area (968 bytes)

status

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x80

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

(1)

0x00 7F05 XL X index register low 0x00

CPU

0x00 7F06 YH Y index register high 0x00

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x17

Reset

(3)

Reset

(2)

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CC Condition code register 0x28

0x00 7F0B

to 0x00

Reserved area (85 bytes)

7F5F

0x00 7F60 CPU CFG_GCR Global configuration register 0x00

0x00 7F70

ITC_SPR1 Interrupt software priority register 1 0xFF

0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF

0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF

ITC

0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF

0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF

0x00 7F78

to

Reserved area (2 bytes)

0x00 7F79

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

48/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Memory and register map

Table 17. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register label Register name

Reset

status

0x00 7F81

to

Reserved area (15 bytes)

0x00 7F8F

0x00 7F90

DM_BK1RE DM breakpoint 1 register extended byte 0xFF

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF

0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF

DM

0x00 7F96 DM_CR1 DM debug module control register 1 0x00

0x00 7F97 DM_CR2 DM debug module control register 2 0x00

0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B

to 0x00

Reserved area (5 bytes)

7F9F

1. Accessible by debug module only

2. Product dependent value, see Figure 7: Register and memory map.

Table 18. Temporary memory unprotection registers

Address Block Register label Register name

0x00 5800

Reset
status

TMU_K1 Temporary memory unprotection key register 1 0x00

0x00 5801 TMU_K2 Temporary memory unprotection key register 2 0x00

0x00 5802 TMU_K3 Temporary memory unprotection key register 3 0x00

0x00 5803 TMU_K4 Temporary memory unprotection key register 4 0x00

0x00 5804 TMU_K5 Temporary memory unprotection key register 5 0x00

TMU

0x00 5805 TMU_K6 Temporary memory unprotection key register 6 0x00

0x00 5806 TMU_K7 Temporary memory unprotection key register 7 0x00

0x00 5807 TMU_K8 Temporary memory unprotection key register 8 0x00

0x00 5808 TMU_CSR

Temporary memory unprotection control and status

register

0x00

Doc ID 14395 Rev 9 49/110

Interrupt table STM8AF52/62xx, STM8AF51/61xx

8 Interrupt table

Table 19. STM8A interrupt table

Priority Source block Description

(1)

Interrupt vector

address

Wakeup

from Halt

Comments

— Reset Reset 0x00 6000 Yes Reset vector in ROM

— TRAP SW interrupt 0x00 8004 — —

0 TLI External top level interrupt 0x00 8008 — —

1 AWU Auto-wakeup from Halt 0x00 800C Yes —

2

Clock

controller

Main clock controller 0x00 8010 — —

3 MISC External interrupt E0 0x00 8014 Yes Port A interrupts

4 MISC External interrupt E1 0x00 8018 Yes Port B interrupts

5 MISC External interrupt E2 0x00 801C Yes Port C interrupts

6 MISC External interrupt E3 0x00 8020 Yes Port D interrupts

7 MISC External interrupt E4 0x00 8024 Yes Port E interrupts

8 CAN CAN interrupt Rx 0x00 8028 Yes —

9 CAN CAN interrupt TX/ER/SC 0x00 802C — —

10 SPI End of transfer 0x00 8030 Yes —

11 Timer 1

Update/overflow/
trigger/break

0x00 8034 — —

12 Timer 1 Capture/compare 0x00 8038 — —

13 Timer 2 Update/overflow 0x00 803C — —

14 Timer 2 Capture/compare 0x00 8040 — —

15 Timer 3 Update/overflow 0x00 8044 — —

16 Timer 3 Capture/compare 0x00 8048 — —

17 USART Tx complete 0x00 804C — —

18 USART Receive data full reg. 0x00 8050 — —

19 I

2

C I

2

C interrupts 0x00 8054 Yes —

20 LINUART Tx complete/error 0x00 8058 — —

21 LINUART Receive data full reg. 0x00 805C — —

22 ADC End of conversion 0x00 8060 — —

23 Timer 4 Update/overflow 0x00 8064 — —

24 EEPROM

1. All unused interrupts must be initialized with ‘IRET’ for robust programming.

End of programming/
write in not allowed area

0x00 8068 — —

50/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Option bytes

9 Option bytes

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be changed in ICP mode (via SWIM).

Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.

Table 20. Option bytes

Ta bl e 20: Option bytes below.

Addr.

0x00
4800

0x00
4801

0x00
4802

0x00
4803

0x00
4804

0x00
4805

0x00
4806

0x00
4807

0x00
4808

0x00
4809

0x00
480A

Option

name

Read-out
protection
(ROP)

User boot
code
(UBC)

Alternate
function
remapping
(AFR)

Watchdog
option

Clock
option

HSE clock
startup

Option

byte

no.

OPT0 ROP[7:0] 0x00

OPT1 UBC[7:0] 0x00

NOPT1 NUBC[7:0] 0xFF

OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00

NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF

OPT3 Reserved

NOPT3 Reserved

OPT4 Reserved

NOPT4 Reserved

OPT5 HSECNT[7:0] 0x00

NOPT5 NHSECNT[7:0] 0xFF

76543 2 1 0

Option bits Factory

default
setting

LSI_ENIWDG

_HW

NLSI_ENNIWD

G_HW

EXT
CLK

NEXT

CLK

CKAW

USEL

NCKAW

USEL

WWD

G _HW

NWWD

G_HW

PRSC1 PRSC0 0x00

NPRSC1

WWDG

_HALT

NWWG

_HALT

NPRSC

0

0x00

0xFF

0xFF

Doc ID 14395 Rev 9 51/110

Option bytes STM8AF52/62xx, STM8AF51/61xx

Table 20. Option bytes (continued)

Addr.

0x00
480B

0x00

480C

0x00

480D

0x00
480E

0x00
480F

0x00
4810

0x00
4811

0x00
4812

0x00
4813

0x00
4814

0x00
4815

Option

name

TMU

Flash wait
states

TMU

Option

byte

no.

76543 2 1 0

Option bits Factory

default
setting

OPT6 TMU[3:0] 0x00

NOPT6 NTMU[3:0] 0xFF

OPT7 Reserved

NOPT7 Reserved

WAIT

STATE

NWAIT

STATE

0x00

0xFF

Reserved

OPT8 TMU_KEY 1 [7:0] 0x00

OPT9 TMU_KEY 2 [7:0] 0x00

OPT10 TMU_KEY 3 [7:0] 0x00

OPT11 TMU_KEY 4 [7:0] 0x00

OPT12 TMU_KEY 5 [7:0] 0x00

OPT13 TMU_KEY 6 [7:0] 0x00

0x00
4816

0x00
4817

0x00
4818

OPT14 TMU_KEY 7 [7:0] 0x00

OPT15 TMU_KEY 8 [7:0] 0x00

OPT16 TMU_MAXATT [7:0] 0xC7

0x00
4819

to

Reserved

487D

0x00
487E

0x00

Boot­loader

487F

1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no
effect on EMC reset.

OPT17 BL [7:0] 0x00

(1)

NOPT

17

NBL [7:0] 0xFF

52/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Option bytes

Table 21. Option byte description

Option byte no. Description

ROP[7:0]: Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

OPT0

OPT1

OPT2

Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM memory readout protection for
details.

UBC[7:0]: User boot code area

0x00: No UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected

Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM write protection for more details.

AFR7: Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP

AFR6: Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I

2

C_SCL.

I

2

C_SDA, port B4 alternate function =

AFR5: Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N.

AFR4: Alternate function remapping option 4

0: Port D7 alternate function = TLI
1: Reserved

AFR3: Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN

AFR2: Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1: Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1.
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3.

AFR0: Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR

Doc ID 14395 Rev 9 53/110

Option bytes STM8AF52/62xx, STM8AF51/61xx

Table 21. Option byte description (continued)

Option byte no. Description

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

OPT3

OPT4

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on Halt

0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN

CKAWUSEL: Auto-wakeup unit/clock

0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU

OPT5

OPT6

OPT7

OPT8

OPT9

OPT10

OPT11

PRSC[1:0]: AWU clock prescaler

00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilization time to 0.5, 8, 128, and 2048 HSE
cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and
0x00.

TMU[3:0]: Enable temporary memory unprotection

0101: TMU disabled (permanent ROP).
Any other value: TMU enabled.

WAIT STATE: Wait state configuration

This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
0: No wait state
1: One wait state

TMU_KEY 1 [7:0]: Temporary unprotection key 0

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 2 [7:0]: Temporary unprotection key 1

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 3 [7:0]: Temporary unprotection key 2

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 4 [7:0]: Temporary unprotection key 3

Temporary unprotection key: Must be different from 0x00 or 0xFF

54/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Option bytes

Table 21. Option byte description (continued)

Option byte no. Description

OPT12

OPT13

OPT14

OPT15

OPT16

OPT17

TMU_KEY 5 [7:0]: Temporary unprotection key 4

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 6 [7:0]: Temporary unprotection key 5

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 7 [7:0]: Temporary unprotection key 6

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_KEY 8 [7:0]: Temporary unprotection key 7

Temporary unprotection key: Must be different from 0x00 or 0xFF

TMU_MAXATT [7:0]: TMU access failure counter

TMU_MAXATT can be initialized with the desired value only if TMU is
disabled (TMU[3:0]=0101 in OPT6 option byte).

When TMU is enabled, any attempt to temporary remove the readout
protection by using wrong key values increments the counter.
When the option byte value reaches 0x08, the Flash memory and data
EEPROM are erased.

BL[7:0]: Bootloader enable

If this option byte is set to 0x55 (complementary value 0xAA) the
bootloader program is activated also in case of a programmed code
memory (for more details, see the bootloader user manual, UM0560).

Doc ID 14395 Rev 9 55/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

50 pF

STM8A pin

10 Electrical characteristics

10.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
TA = T

Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.

(given by the selected temperature range).

Amax

10.1.2 Typical values

= -40 °C, TA = 25 °C, and

A

Unless otherwise specified, typical data are based on TA = 25 °C, V
given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range

10.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

10.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

Figure 8. Pin loading conditions

= 5.0 V. They are

DD

.

56/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

V

IN

STM8A pin

10.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 9. Pin input voltage

10.2 Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 22. Voltage characteristics

Symbol Ratings Min Max Unit

V

DDx

- V

Supply voltage (including V

SS

DDA and VDDIO

Input voltage on true open drain pins (PE1, PE2)

V

IN

- VDD| Variations between different power pins — 50

|V

DDx

- VSS| Variations between all the different ground pins — 50

|V

SSx

Input voltage on any other pin

(2)

(1)

)

(2)

-0.3 6.5 V

V

- 0.3 6.5

SS

V

- 0.3 V

SS

DD

+ 0.3

see Absolute maximum ratings

V

ESD

Electrostatic discharge voltage

(electrical sensitivity) on

page 85

1. All power (VDD, V
external power supply

2. I

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I
injection is induced by V
pads, there is no positive injection current, and the corresponding V

DDIO

, V

) and ground (VSS, V

DDA

> VDD while a negative injection is induced by V

IN

SSIO

, V

) pins must always be connected to the

SSA

value. A positive

INJ(PIN)

< VSS. For true open-drain

IN

maximum must always be respected

IN

V

mV

Doc ID 14395 Rev 9 57/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

Table 23. Current characteristics

Symbol Ratings Max. Unit

I

VDDIO

I

VSSIO

Total current into V

DDIO

Total current out of V

power lines (source)

ground lines (sink)

SS IO

Output current sunk by any I/O and control pin 20

I

IO

I

INJ(PIN)

I

INJ(TOT)

1. All power (VDD, V
external supply.

2. The total limit applies to the sum of operation and injected currents.

3. V

4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the

Table 24. Thermal characteristics

includes the sum of the positive injection currents. V

DDIO

currents.

injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >
VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive
injection current allowed and the corresponding VIN maximum must always be respected.

Output current source by any I/Os and control pin -20

(4)

Injected current on any pin ±10

Sum of injected currents 50

, V

DDIO

) and ground (VSS, V

DDA

SSIO

, V

SSA

(1)(2)(3)

(1)(2)(3)

100

100

) pins must always be connected to the

includes the sum of the negative injection

SSIO

mA

Symbol Ratings Value Unit

T

STG

T

J

Table 25. Operating lifetime

Storage temperature range -65 to 150

Maximum junction temperature 160

(1)

Symbol Ratings Value Unit

−40 to 125 °C Grade 1

OLF Conforming to AEC-Q100 rev G

−40 to 150 °C Grade 0

1. For detailed mission profile analysis, please contact your local ST Sales Office.

°C

58/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

f

CPU

[MHz]

Supply voltage [V]

24

12

8

4
0

3.0 4.0 5.0

Functionality

not guaranteed

in this area

16

5.5

Functionality guaranteed

@ T

A

-40 to 150 °C at 1 waitstate

Functionality guaranteed

@ T

A

-40 to 150 °C at 0 waitstate

10.3 Operating conditions

Table 26. General operating conditions

Symbol Parameter Conditions Min Max Unit

f

CPU

V

DD/VDDIO

V

CAP

1 wait state

T

= -40 °C to 150 °C

Internal CPU clock frequency

A

0 wait state

T

= -40 °C to 150 °C

A

Standard operating voltage - 3.0 5.5 V

C

: capacitance of external

EXT

capacitor

(1)

ESR of external capacitor

at 1 MHz

(2)

16 24

016

470 3300 nF

-0.3

ESL of external capacitor - 15 nH

Suffix A

85

Suffix B 105

T

A

Ambient temperature

Suffix C 125

Suffix D 150

- 40

Suffix A 90

Suffix B 110

T

J

Junction temperature range

Suffix C 130

Suffix D 155

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.

2. This frequency of 1 MHz as a condition for V

parameters is given by design of internal regulator.

CAP

MHz

Ω

°C

Figure 10. f

CPUmax

versus V

Doc ID 14395 Rev 9 59/110

DD

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

C

Rleak

ESR ESL

Table 27. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit

8

µs/V

8

t

VDD

VDD rise time rate — 2

fall time rate — 2

V

DD

(1)

(1)

—

—

Reset release delay VDD rising — 3 — ms

t

TEMP

V

IT+

Reset generation delay V

Power-on reset
threshold

(2)

falling — 3 — µs

DD

— 2.65 2.8 2.95

V

V

IT-

V

HYS(BOR)

1. Guaranteed by design, not tested in production.

2. If VDD is below 3 V, the code execution is guaranteed above the V
kept. The EEPROM programming sequence must not be initiated.

Brown-out reset
threshold

Brown-out reset
hysteresis

— 2.58 2.73 2.88

——70

and V

IT-

(1)

thresholds. RAM content is

IT+

mV

10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C
V

CAP

pin. C

is specified in Ta bl e 26. Care should be taken to limit the series inductance

EXT

to less than 15 nH.

Figure 11. External capacitor C

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

EXT

10.3.2 Supply current characteristics

The current consumption is measured as described in Figure 8 on page 56 and Figure 9 on

page 57.

If not explicitly stated, general conditions of temperature and voltage apply.

EXT

to the

60/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

Table 28. Total current consumption in Run, Wait and Slow mode. General conditions

for V

Symbol Parameter Conditions Typ Max Unit

DD(WFI)

(1)

(1)

(1)

(1)

I

DD(RUN)

I

DD(RUN)

I

I

DD(SLOW)

1. The current due to I/O utilization is not taken into account in these values.

2. Values not tested in production. Design guidelines only.

apply, TA = −40 °C to 150 °C

DD

All peripherals

clocked, code
Supply current in
Run mode

executed from Flash

program memory,

HSE external clock

(without resonator)

All peripherals

Supply current in
Run mode

clocked, code

executed from RAM,

HSE external clock

(without resonator)

Supply current in
Wait mode

Supply current in
Slow mode

CPU stopped, all

peripherals off, HSE

external clock

f

CPU

all peripherals off,

code executed from

RAM

scaled down,

= 24 MHz 1 ws 8.7 16.8

f

CPU

f

= 16 MHz 7.4 14

CPU

= 8 MHz 4.0 7.4

f

CPU

f

= 4 MHz 2.4 4.1

CPU

f

= 2 MHz 1.5 2.5

CPU

= 24 MHz 4.4 6.0

f

CPU

f

= 16 MHz 3.7 5.0

CPU

f

= 8 MHz 2.2 3.0

CPU

f

= 4 MHz 1.4 2.0

CPU

f

= 2 MHz 1.0 1.5

CPU

= 24 MHz 2.4 3.1

f

CPU

f

= 16 MHz 1.65 2.5

CPU

f

= 8 MHz 1.15 1.9

CPU

f

= 4 MHz 0.90 1.6

CPU

f

= 2 MHz 0.80 1.5

CPU

External clock 16 MHz

= 125 kHz

f

CPU

LSI internal RC

= 128 kHz

f

CPU

1.50 1.95

1.50 1.80

(2)

(2)

(2)

(2)

(2)

(2)

mA

(2)

(2)

(2)

(2)

Doc ID 14395 Rev 9 61/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

Table 29. Total current consumption in Halt and Active-halt modes. General conditions for V

applied. TA = −40 °C to 55 °C unless otherwise stated

Conditions

Symbol Parameter

I

DD(H)

Supply current in
Halt mode

Supply current in
Active-halt mode
with regulator on

I

DD(AH)

Supply current in
Active-halt mode
with regulator off

Wakeup time from
Active-halt mode
with regulator on

t

WU(AH)

Wakeup time from
Active-halt mode
with regulator off

1. Configured by the REGAH bit in the CLK_ICKR register.

2. Configured by the AHALT bit in the FLASH_CR1 register.

3. Data based on characterization results. Not tested in production.

Main

voltage

regulator

(1)

(MVR)

Flash

mode

(2)

Clock source and

temperature condition

Typ Max Unit

Clocks stopped 5 35

Off

On

Power-

down

Power-

down

Clocks stopped,

T

= 25 °C

A

External clock 16 MHz

MASTER

= 125 kHz

f

525

770 900

LSI clock 128 kHz 150 230

LSI clock 128 kHz 25 42

Off

On

Power-

down

Operating

mode

LSI clock 128 kHz,

= 25 °C

T

A

=−40 to 150 °C

T

A

25 30

10 30

Off 50 80

(3)

(3)

µA

(3)

(3)

(3)

µs

(3)

DD

Current consumption for on-chip peripherals

Table 30. Oscillator current consumption

Symbol Parameter Conditions Typ Max

I

DD(OSC)

I

DD(OSC)

1. During startup, the oscillator current consumption may reach 6 mA.

2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small R
to crystal manufacturer for more details

3. Informative data.

62/110 Doc ID 14395 Rev 9

HSE oscillator current
consumption

HSE oscillator current
consumption

(2)

(2)

Quartz or

ceramic

resonator,

CL = 33 pF

= 5 V

V

DD

Quartz or

ceramic

resonator,

CL = 33 pF

= 3.3 V

V

DD

f

= 24 MHz 1 2.0

OSC

f

= 16 MHz 0.6 —

OSC

= 8 MHz 0.57 —

f

OSC

= 24 MHz 0.5 1.0

f

OSC

f

= 16 MHz 0.25 —

OSC

= 8 MHz 0.18 —

f

OSC

(1)

(3)

(3)

value. Refer

m

Unit

mA

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

Table 31. Programming current consumption

Symbol Parameter Conditions Typ Max Unit

VDD = 5 V, -40 °C to 150 °C, erasing

I

DD(PROG)

Programming current

and programming data or Flash

1.0 1.7 mA

program memory

Table 32. Typical peripheral current consumption VDD = 5.0 V

Symbol Parameter

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM3)

I

DD(TIM4)

I

DD(USART)

I

DD(LINUART)

I

DD(SPI)

I

DD(I2C)

I

DD(CAN)

I

DD(AWU)

I

DD(TOT_DIG)

I

DD(ADC)

Typ.

TIM1 supply current

TIM2 supply current

TIM3 supply current

TIM4 supply current

USART supply current

(2)

(2)

(2)

(2)

(2)

LINUART supply current

SPI supply current

I2C supply current

CAN supply current

AWU supply current

(2)

(2)

(3)

(2)

f

(2)

= 2 MHz

master

0.03 0.23 0.34

0.02 0.12 0.19

0.01 0.1 0.16

0.004 0.03 0.05

0.03 0.09 0.15

0.03 0.11 0.18

0.01 0.04 0.07

0.02 0.06 0.91

0.06 0.30 0.40

0.003 0.02 0.05

All digital peripherals on 0.22 1 2.4

ADC supply current when
converting

(4)

0.93 0.95 0.96

f

master

(1)

Typ.

= 16 MHz

f

master

Typ.

=24 MHz

Unit

mA

1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital
supply voltage, the values are similar in the full supply voltage range.

2. Data based on a differential I
measurement does not include the pad toggling consumption.

3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data
transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption.

4. Data based on a differential I

measurement between no peripheral clocked and a single active peripheral. This

DD

measurement between reset configuration and continuous A/D conversions.

DD

Doc ID 14395 Rev 9 63/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

0

1

2

3

4

5

6

7

8

9

10

2.533.544.555.56

V

DD

[V]

I

DD(RUN)HSE

[mA]

25°C

85°C

12 5 °C

0

1

2

3

4

5

6

7

8

9

10

0 5 10 15 20 25 30

fcpu [MHz]

I

DD(RUN)HSE

[mA]

25°C

85°C

12 5 °C

0

1

2

3

4

2.5 3.5 4.5 5.5 6.5

VDD [V]

IDD(RUN)HSI [mA]

25°C
85°C
125°C

0

1

2

3

4

5

6

2.5 3.5 4.5 5.5 6.5

VDD [V]

IDD(WFI)HSE [mA]

25°C
85°C
125°C

0

1

2

3

4

5

6

0 5 10 15 20 25 30

fcpu [MHz]

I

DD(WFI)HSE

[mA]

25°C

85°C

12 5 °C

0

0.5

1

1.5

2

2.5

2.5 3 3. 5 4 4.5 5 5. 5 6

V

DD

[V]

I

DD(WFI)HSI

[mA]

25°C

85°C

12 5 °C

Current consumption curves

Figure 12 to Figure 17 show typical current consumption measured with code executing in

RAM.

Figure 12. Typ. I

@f

CPU

DD(RUN)HSE

vs. VDD

= 16 MHz, peripherals = on

Figure 13. Typ. I

@ VDD = 5.0 V, peripherals = on

DD(RUN)HSE

vs. f

CPU

Figure 14. Typ. I

@ f

CPU

Figure 16. Typ. I

@ VDD = 5.0 V, peripherals = on

DD(RUN)HSI

vs. VDD

= 16 MHz, peripherals = off

DD(WFI)HSE

vs. f

CPU

Figure 15. Typ. I

@ f

CPU

Figure 17. Typ. I

@ f

CPU

DD(WFI)HSE

vs. V

DD

= 16 MHz, peripherals = on

DD(WFI)HSI

vs. V

DD

= 16 MHz, peripherals = off

64/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

OSCIN

f

HSE

External clock

STM8A

source

V

HSEL

V

HSEH

10.3.3 External clock sources and timing characteristics

HSE external clock

An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the
OSCIN pin.

Clock characteristics are subject to general operating conditions for VDD and TA.

Table 33. HSE external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HSE_ext

V

HSEdHL

V

HSEH

V

HSEL

I

LEAK_HSE

1. If CSS is used, the external clock must have a frequency above 500 kHz.

User external clock source
frequency

= -40 °C to 150 °C 0

T

A

Comparator hysteresis — 0.1 x V

OSCIN high-level input pin
voltage

OSCIN low-level input pin
voltage

OSCIN input leakage current V

— 0.7 x V

—V

< V

IN

< V

DD

SS

Figure 18. HSE external clock source

(1)

DD

DD

SS

—24MHz

——

—V

— 0.3 x V

DD

V

DD

-1 — +1 µA

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.
All the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Doc ID 14395 Rev 9 65/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

OSCOUT

OSCIN

f

HSE

to core

C

L1

C

L2

R

F

STM8A

Resonator

Current control

g

m

R

m

C

m

L

m

C

O

Resonator

gmg

mcrit

»

g

mcrit

2 Π× HSE

f

×()

2

Rm× 2Co C+()

2

=

Table 34. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

C

L1/CL2

g

m

t

SU(HSE)

1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (C
(C

L1

2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is
reached. It can vary with the crystal type that is used.

Feedback resistor — — 220 — kΩ

F

(1)

Recommended load capacitance — — — 20 pF

Oscillator trans conductance — 5 — — mA/V

V

(2)

Startup time

* CL2)/(CL1 + CL2). If CL1 = CL2, C

load

= C

. Some oscillators have built-in load capacitors, CL1 and CL2.

L1/2

is

DD

stabilized

—2.8 —ms

Load

) is

Figure 19. HSE oscillator circuit diagram

HSE oscillator critical gm formula

The crystal characteristics have to be checked with the following formula:

Equation 1

where g

Equation 2

Rm: Notional resistance (see crystal specification)
L
C
Co: Shunt capacitance (see crystal specification)
C

66/110 Doc ID 14395 Rev 9

can be calculated with the crystal parameters as follows:

mcrit

: Notional inductance (see crystal specification)

m

: Notional capacitance (see crystal specification)

m

= C

L1

= C: Grounded external capacitance

L2

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

-3%

-2%

-1%

0%

1%

2%

3%

2.533.544.555.56

V

DD

[V]

HSI frequenc y variation [%]

-40°C

25°C

85°C

10.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA.

High-speed internal RC oscillator (HSI)

Table 35. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

ACC

t

su(HSI)

1. Guaranteed by characterization, not tested in production

Figure 20. Typical HSI frequency vs V

Frequency — — 16 — MHz

HSI

HSI oscillator user
trimming accuracy

HS

HSI oscillator accuracy
(factory calibrated)

Trimmed by the application

for any V

conditions

V

= 3.0 V ≤ VDD ≤ 5.5 V,

DD

-40 °C ≤ TA ≤ 150 °C

HSI oscillator wakeup time — — — 2

DD

and TA

DD

-1 — 1

-5 — 5

125°C

(1)

%

µs

Doc ID 14395 Rev 9 67/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

-3%

-2%

-1%

0%

1%

2%

3%

2.5 3 3.5 4 4.5 5 5.5 6
V

DD

[V]

LSI frequenc y variation [%]

Low-speed internal RC oscillator (LSI)

Subject to general operating conditions for VDD and TA.

Table 36. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

t

su(LSI)

Frequency — 112 128 144 kHz

LSI

LSI oscillator wakeup time — — — 7

1. Data based on characterization results, not tested in production.

Figure 21. Typical LSI frequency vs V

DD

25°C

(1)

µs

68/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

10.3.5 Memory characteristics

Flash program memory/data EEPROM memory

General conditions: TA = -40 °C to 150 °C.

Table 37. Flash program memory/data EEPROM memory

Symbol Parameter Conditions Min

f

is 16 to 24 M Hz

V

Operating voltage

DD

(all modes, execution/write/erase)

CPU

with 1 ws

f

is 0 to 16 MHz

CPU

with 0 ws

is 16 to 24 M Hz

f

CPU

V

Operating voltage (code execution)

DD

with 1 ws

is 0 to 16 MHz

f

CPU

with 0 ws

Standard programming time
(including erase) for byte/word/block

t

(1 byte/4 bytes/128 bytes)

prog

Fast programming time for 1 block
(128 bytes)

t

erase

1. Guaranteed by characterization, not tested in production.

Erase time for 1 block (128 bytes) — — 3 3.3 ms

——66.6

——33.3

(1)

Typ Max Uni t

3.0 — 5.5

2.6 — 5.5

V

ms

Table 38. Flash program memory

Symbol Parameter Condition Min Max Unit

T

N

t

RET

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.

Temperature for writing and erasing — -40 150 °C

WE

Flash program memory endurance

WE

(erase/write cycles)

Data retention time

(1)

TA = 25 °C 1000 — cycles

T

= 25 °C 40 —

A

= 55 °C 20 —

T

A

years

Doc ID 14395 Rev 9 69/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

Table 39. Data memory

Symbol Parameter Condition Min Max Unit

T

N

t

1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a

2. More information on the relationship between data retention time and number of write/erase cycles is

3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.

Temperature for writing and erasing — -40 150 °C

WE

Data memory endurance

WE

(erase/write cycles)

Data retention time

RET

write/erase operation addresses a single byte.

available in a separate technical document.

(1)

TA = 25 °C 300 k —

= -40°C to 125 °C 100 k

T

A

TA = 25 °C 40

= 55 °C 20

T

A

(2)

(2)(3)

(2)(3)

cycles

—

—

—

years

70/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

10.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.

Table 40. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

V

V

V

Low-level input voltage

IL

High-level input voltage 0.7 x V

IH

hys

Hysteresis

(1)

Standard I/0, V

—

DD

= 5 V,

I = 3 mA

High-level output voltage

OH

Standard I/0, VDD = 3 V,

I = 1.5 mA

-0.3 V 0.3 x V

DD

—

V

- 0.5 V — —

DD

V

- 0.4 V — —

DD

0.1 x
V

VDD + 0.3 V

DD

DD

—

—

High sink and true open

drain I/0, V

DD

= 5 V

——0.5

I = 8 mA

V

R

t

R

I

Low-level output voltage

OL

Pull-up resistor VDD = 5 V, V

pu

Standard and high sink I/Os

Rise and fall time

, t

F

(10% - 90%)

Standard and high sink I/Os

Digital input pad leakage

lkg

current

I = 3 mA

Standard I/0, V

I = 1.5 mA

Fast I/Os

Load = 50 pF

Load = 50 pF

Fast I/Os

Load = 20 pF

Load = 20 pF

V

≤ V

SS

IN

DD

DD

IN

≤ V

= 5 V

= 3 V

= V

DD

SS

——0.6

——0.4

35 50 65 kΩ

20

50

(2)

(2)

(2)

(2)

——35

— — 125

——±1µA

VStandard I/0, V

ns

≤ V

≤ V

IN

IN

≤ V

≤ V

DD

DD

— — ±250

— — ±500

(3)

V

SS

I

lkg ana

Analog input pad leakage
current

-40 °C < TA < 125 °C

V

SS

-40 °C < TA < 150 °C

I

lkg(inj)

I

DDIO

1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

Leakage current in
adjacent I/O

(3)

Total current on either
V

or V

DDIO

SSIO

Injection current ±4 mA — — ±1

Including injection currents — — 60 mA

Doc ID 14395 Rev 9 71/110

nA

µA

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

0

1

2

3

4

5

6

2.5 3 3.5 4 4.5 5 5.5 6
V

DD

[V]

V

IL

/ V

IH

[V]

-40°C

25°C

85°C

125°C

30

35

40

45

50

55

60

2.53 3.54 4.55 5.56
V

DD

[V]

Pull-Up resistance [k ohm]

-40°C

25°C

85°C

125°C

2. Guaranteed by design.

3. Data based on characterization results, not tested in production.

Figure 22. Typical VIL and VIH vs VDD @ four temperatures

Figure 23. Typical pull-up resistance RPU vs VDD @ four temperatures

72/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

0

20

40

60

80

100

120

140

0123456

V

DD

[V]

Pull-Up current [µA]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

01234567

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

024681012

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0246 8101214

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0 5 10 15 20 25

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

125°C

Figure 24. Typical pull-up current Ipu vs VDD @ four temperatures

(1)

1. The pull-up is a pure resistor (slope goes through 0).

Typical output level curves

Figure 25 to Figure 34 show typical output level curves measured with output on a single pin.

Figure 25. Typ. VOL @ VDD = 3.3 V (standard

ports)

Figure 26. Typ. VOL @ VDD = 5.0 V (standard

ports)

Figure 27. Typ. VOL @ VDD = 3.3 V (true open

drain ports)

Figure 28. Typ. VOL @ VDD = 5.0 V (true open

drain ports)

Doc ID 14395 Rev 9 73/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

0

0.25

0.5

0.75

1

1.25

1.5

0246 8101214

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

0 5 10 15 20 25

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

01234567

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

024681012

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0246 8101214

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

125°C

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0 5 10 15 20 25

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

125°C

Figure 29. Typ. VOL @ VDD = 3.3 V (high sink

ports)

Figure 31. Typ. V

DD - VOH

@ VDD = 3.3 V

(standard ports)

Figure 30. Typ. VOL @ VDD = 5.0 V (high sink

ports)

Figure 32. Typ. V

DD - VOH

@ VDD = 5.0 V

(standard ports)

Figure 33. Typ. V

DD - VOH

sink ports)

74/110 Doc ID 14395 Rev 9

@ VDD = 3.3 V (high

Figure 34. Typ. V

sink ports)

DD - VOH

@ VDD = 5.0 V (high

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

0

1

2

3

4

5

6

2.5 3 3.5 4 4.5 5 5.5 6
V

DD

[V]

V

IL

/ V

IH

[V]

-40°C

25°C

85°C

125°C

10.3.7 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 41. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

(1)

(1)

(1)

—VSS— 0.3 x V

— 0.7 x V

I

= 3 mA — 0.6 V

OL

—V

DD

DD

DD

—

—85—315ns

500 ns

V

IL(NRST)

V

IH(NRST)

V

OL(NRST)

R

PU(NRST)

t

IFP

t

IFP(NRST)

NRST low-level input voltage

NRST high-level input voltage

NRST low-level output voltage

NRST pull-up resistor — 30 40 60 kΩ

NRST input filtered pulse

NRST Input not filtered pulse
duration

(2)

1. Data based on characterization results, not tested in production.

2. Data guaranteed by design, not tested in production.

Figure 35. Typical NRST VIL and VIH vs VDD @ four temperatures

Doc ID 14395 Rev 9 75/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

30

35

40

45

50

55

60

2.5 3 3.5 4 4.5 5 5.5 6
V

DD

[V]

NRST Pull-Up resistance [k ohm]

-40°C

25°C

85°C

125°C

0

20

40

60

80

100

120

140

0123456

V

DD

[V]

NRST Pull-Up current [µA]

-40°C

25°C

85°C

125°C

Figure 36. Typical NRST pull-up resistance RPU vs V

Figure 37. Typical NRST pull-up current Ipu vs V

DD

DD

The reset network shown in Figure 38 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below V

NRST pin characteristics), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.

76/110 Doc ID 14395 Rev 9

IL(NRST)

max (see Ta bl e 41:

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

External

STM8A

Filter

R

PU

V

DD

Internal reset

NRST

0.1µF

reset

circuit

(optional)

Figure 38. Recommended reset pin protection

10.3.8 TIM 1, 2, 3, and 4 electrical specifications

Subject to general operating conditions for VDD, f

Table 42. TIM 1, 2, 3, and 4 electrical specifications

MASTER

and TA.

Symbol Parameter Conditions Min Typ Max Unit

f

EXT

Timer external clock frequency

1. Not tested in production.

(1)

———24MHz

Doc ID 14395 Rev 9 77/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

10.3.9

SPI interface

Unless otherwise specified, the parameters given in Ta b le 43 are derived from tests
performed under ambient temperature, f
conditions. t

MASTER

= 1/f

MASTER

.

MASTER

frequency, and VDD supply voltage

Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).

Table 43. SPI characteristics

Symbol Parameter Conditions Min Max Unit

f

SCK

1/t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

1. f

SCK

2. The pad has to be configured accordingly (fast mode).

3. Values based on design simulation and/or characterization results, and not tested in production.

4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Master mode 0 10

SPI clock frequency

VDD < 4.5 V 0 6

Slave mode

VDD = 4.5 V to 5.5 V 0 8

SPI clock rise and fall time Capacitive load: C = 30 pF — 25

(3)

NSS setup time Slave mode 4 * t

(3)

NSS hold time Slave mode 70 —

(3)

SCK high and low time Master mode t

(3)

(3)

Data input setup time

(3)

(3)

Data input hold time

(3)

(3)(4)

Data output access time Slave mode — 3* t

(3)(5)

Data output disable time Slave mode 25

(3)

Data output valid time

(3)

Data output valid time Master mode (after enable edge) — 30

(3)

Data output hold time

(3)

< f

MASTER

/2.

Master mode 5 —

Slave mode 5 —

Master mode 7 —

Slave mode 10 —

V

Slave mode
(after enable edge)

DD

V

DD

Slave mode (after enable edge) 31 —

Master mode (after enable edge) 12 —

/2 - 15 t

SCK

< 4.5 V — 75

= 4.5 V to 5.5 V — 53

SCK

MASTER

/2 + 15

(1)

(1)

—

t

w(SCKH)

t

w(SCKL)

MASTER

(2)

(3)

(3)

MHz

ns

78/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

NSS input

Figure 39. SPI timing diagram in slave mode and with CPHA = 0

1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 V

DD

.

Figure 40. SPI timing diagram in slave mode and with CPHA = 1

1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 V

DD

.

Doc ID 14395 Rev 9 79/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

AI

3#+OUTPUT

#0(!

-/3)

/5454

-)3/

).0 54

#0(!

-3").

- 3"/54

")4).

,3"/54

,3").

#0/,

#0/,

" ) 4/54

.33INPUT

T

C3#+

T

W3#+(

T

W3#+,

T

R3#+

T

F3#+

T

H-)

(IGH

3#+OUTPUT

#0(!

#0(!

#0/,

#0/,

T

SU-)

T

V-/

T

H-/

Figure 41. SPI timing diagram - master mode

1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 V

DD

.

80/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

10.3.10 I2C interface characteristics

Table 44. I2C characteristics

Symbol Parameter

Standard mode I

(2)

Min

Max

2

C Fast mode I2C

(2)

Min

(2)

Max

(2)

(1)

Unit

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

1. f

MASTER

Data based on standard I

2.

The maximum hold time of the start condition has only to be met if the interface does not stretch the low

3.
time

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

4.
undefined region of the falling edge of SCL

SCL clock low time 4.7 — 1.3 —

SCL clock high time 4.0 — 0.6 —

SDA setup time 250 — 100 —

SDA data hold time 0

SDA and SCL rise time

3 V to 5.5 V)

(V

DD

SDA and SCL fall time
(V

3 V to 5.5 V)

DD

(3)

—0

— 1000 — 300

— 300 — 300

(4)

START condition hold time 4.0 — 0.6 —

Repeated START condition setup time 4.7 — 0.6 —

STOP condition setup time 4.0 — 0.6 — µs

STOP to START condition time
(bus free)

Capacitive load for each bus line — 400 — 400 pF

b

, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)

2

C protocol requirement, not tested in production

4.7 — 1.3 — µs

900

µs

(3)

ns

µs

Doc ID 14395 Rev 9 81/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

AINx

STM8A

V

DD

I

L

V

T

0.6V

V

T

0.6V

V

AIN

R

AIN

10-bit A/D
conversion

C

AIN

T

s

C

samp

Rswitch

10.3.11 10-bit ADC characteristics

Subject to general operating conditions for V

DDA

, f

MASTER

and TA unless otherwise

specified.

Table 45. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

V

V

V

V

C

t

t

STAB

t

CONV

R

switch

1. During the sample time, the sampling capacitance, C

ADC clock frequency — 111 kHz — 4 MHz kHz/MHz

ADC

Analog supply — 3 — 5.5

DDA

Positive reference voltage — 2.75 — V

REF+

Negative reference voltage — V

REF-

—V

Conversion voltage range

AIN

Internal sample and hold capacitor — — — 3 pF

samp

Sampling time

(1)

S

(3 x 1/f

ADC

)

(1)

Wakeup time from standby

Total conversion time including

Devices with

external V

f

ADC

f

ADC

f

ADC

f

ADC

f

ADC

REF+

pins

V

REF-

= 2 MHz — 1.5 —

= 4 MHz — 0.75 —

= 2 MHz — 7 —

= 4 MHz 3.5

= 2 MHz — 7 —

SSA

SSA

V

/

REF-

—0.5

—V

—V

DDA

DDA

REF+

sampling time

= 4 MHz — 3.5 —

f

(14 x 1/f

ADC

)

ADC

Equivalent switch resistance — — — 30 kΩ

(3 pF typ), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within t
effect on the conversion result.

After the end of the sample time tS, changes of the analog input voltage have no

S.

samp

V

µs

Figure 42. Typical application with ADC

1. Legend: R

82/110 Doc ID 14395 Rev 9

= external resistance, C

AIN

= capacitors, C

AIN

= internal sample and hold capacitor.

samp

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

E

O

E

G

1LSB

IDEAL

1LSB

IDEAL

V

DDAVSSA

–

1024

------------------------------ -----------=

1023

1022
1021

5

4

3

2

1

0

7

6

1234567

1021102210231024

(1)

(2)

E

T

E

D

E

L

(3)

V

DDA

V

SSA

Table 46. ADC accuracy for V

Symbol Parameter Conditions Typ Max

|E

| Total unadjusted error

T

| Offset error

|E

O

| Gain error

|E

G

|E

| Differential linearity error

D

| Integral linearity error

|E

L

| Total unadjusted error

|E

T

|EO| Offset error

|EG| Gain error

|ED| Differential linearity error

|EL| Integral linearity error

1. Max value is based on characterization, not tested in production.

2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for
I

and ΣI

INJ(PIN)

INJ(PIN)

3. TUE 2LSB can be reached on specific salestypes on the whole temperature range.

4. Target values.

(2)

(2)

(2)

(2)

(2)

(2)

in Section 10.3.6 does not affect the ADC accuracy.

(2)

(2)

DDA

(2)

(2)

= 5 V

f

ADC

f

ADC

= 2 MHz

= 4 MHz

1.4 3

0.8 3

0.1 2

0.9 1

0.7 1.5

(4)

1.9

(4)

1.3

(4)

0.6

(4)

1.5

(4)

1.2

1.5

(1)

Unit

(3)

(4)

4

(4)

4

(4)

3

(4)

2

LSB

(4)

Figure 43. ADC accuracy characteristics

1. Example of an actual transfer curve

2. The ideal transfer curve

3. End point correlation line

= Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.

E

T

EO = Offset error: Deviation between the first actual transition and the first ideal one.
EG = Gain error: Deviation between the last ideal transition and the last actual one.
E

= Differential linearity error: Maximum deviation between actual steps and the ideal one.

D

EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation

line.

Doc ID 14395 Rev 9 83/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

10.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.

● FTB: A burst of fast transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

and VSS

DD

Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Table 47. EMS data

Symbol Parameter Conditions Level/class

= 3.3 V, TA= 25 °C,

V

V

V

Voltage limits to be applied on any I/O pin

FESD

to induce a functional disturbance

Fast transient voltage burst limits to be
applied through 100 pF on VDD and V

EFTB

pins to induce a functional disturbance

SS

DD

f

MASTER

f

MASTER

= 16 MHz (HSI clock),

Conforms to IEC 1000-4-2

VDD= 3.3 V, TA= 25 °C,

= 16 MHz (HSI clock),

Conforms to IEC 1000-4-4

3B

4A

84/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

Electromagnetic interference (EMI)

Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.

Table 48. EMI data

Conditions

Symbol Parameter

Peak level

S

EMI

SAE EMI level — 2 2.5 2.5

1. Data based on characterization results, not tested in production.

General

conditions

V

= 5 V,

DD

= 25 °C,

T

A

LQFP80 package
conforming to SAE
J 1752/3

Monitored

frequency band

0.1 MHz to 30 MHz 15 17 22

30 MHz to 130 MHz 18 22 16

130 MHz to 1 GHz -1 3 5

Max f

8

MHz

CPU

16

MHz

(1)

Unit

24

MHz

dBµV

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.

Table 49. ESD absolute maximum ratings

Symbol Ratings Conditions Class

V

ESD(HBM)

ESD(CDM)

V

ESD(MM)

1. Data based on characterization results, not tested in production

Electrostatic discharge voltage
(human body model)

Electrostatic discharge voltage
(charge device model)

Electrostatic discharge voltage
(charge device model)

TA = 25 °C, conforming to

JESD22-A114

TA = 25 °C, conforming to

JESD22-C101

TA = 25 °C, conforming to

JESD22-A115

Doc ID 14395 Rev 9 85/110

Maximum

value

3A 4000

3 500

B 200

(1)

Uni

t

VV

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up
performance.

● A supply overvoltage (applied to each power supply pin) and

● A current injection (applied to each input, output and configurable I/O pin) are

performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.

Table 50. Electrical sensitivities

Symbol Parameter Conditions Class

= 25 °C

T

A

T

= 85 °C

LU Static latch-up class

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).

A

= 125 °C

T

A

T

= 150 °C

A

(1)

A

86/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Electrical characteristics

10.4 Thermal characteristics

In case the maximum chip junction temperature (T

) specified in Ta bl e 26: General

Jmax

operating conditions is exceeded, the functionality of the device cannot be guaranteed.

T

, in degrees Celsius, may be calculated using the following equation:

Jmax

Equation 3

T

Jmax

= T

Amax

+ (P

Dmax

x ΘJA)

where:

T

is the maximum ambient temperature in °C

Amax

Θ

is the package junction-to-ambient thermal resistance in ° C/W

JA

P

is the sum of P

Dmax

P

INTmax

is the product of I

INTmax

DD

and P

I/Omax (PDmax

= P

INTmax

+ P

I/Omax

)

and VDD, expressed in Watts. This is the maximum chip

internal power.

P

represents the maximum power dissipation on output pins

I/Omax

where:

Equation 4

P

I/Omax =

taking into account the actual V

Σ (VOL * IOL) + Σ((V

/ I

OL

and V

OH

OL

- VOH) * IOH)

DD

/ IOH of the I/Os at low- and high-level in the

application.

Table 51. Thermal characteristics

(1)

Symbol Parameter Value Unit

Θ

JA

Θ

JA

Θ

JA

Θ

JA

Θ

JA

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.

Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm

Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm

Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm

Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm

Thermal resistance junction-ambient
VFQFPN 32 - 5 x 5 mm

10.4.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.

38 °C/W

46 °C/W

57 °C/W

59 °C/W

25 °C/W

Doc ID 14395 Rev 9 87/110

Electrical characteristics STM8AF52/62xx, STM8AF51/61xx

10.4.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 52: Ordering information scheme(1) on page 98).

The following example shows how to calculate the temperature range needed for a given
application.

Assuming the following application conditions:

– Maximum ambient temperature T

–I

–V

DDmax

= 5 V

DD

= 8 mA

– maximum 20 I/Os used at the same time in output at low-level with I

–V

OL

= 0.4 V

Equation 5

= 82 °C (measured according to JESD51-2)

Amax

OL

= 8 mA

P

INTmax =

8 mA x 5 V = 400 mW

Equation 6

P

IOmax =

20 x 8 mA x 0.4 V = 64 mW

This gives:

P

INTmax

= 400 mW and P

IOmax

64 mW:

Equation 7

P

Dmax =

400 mW + 64 mW

Thus:

P

= 464 mW.

Dmax

Using the values obtained in Tab le 51: Thermal characteristics on page 87 T
calculated as follows:

For LQFP64 46 °C/W

Equation 8

T

= 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C

jmax

Jmax

is

This is within the range of the suffix B version parts (-40 °C < Tj < 105 ° C).

Parts must be ordered at least with the temperature range suffix B.

88/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Package characteristics

11 Package characteristics

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at:
ECOPACK® is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK®

www.st.com.

Doc ID 14395 Rev 9 89/110

Package characteristics STM8AF52/62xx, STM8AF51/61xx

1S_ME

L

A1 K

L1

c

A

A2

ccc

C

D

D1

D3

E3

E1 E

40

41

60

61

b

80

1

Pin 1
identification

11.1 Package mechanical data

Figure 44. LQFP 80-pin low profile quad flat package (14 x 14)

Table 52. LQFP 80-pin low profile quad flat package mechanical data

mm inches

(1)

Dim.

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.220 0.320 0.380 0.0087 0.0126 0.0150

c 0.090 — 0.200 0.0035 — 0.0079

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 — 12.350 — — 0.4862 —

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 — 12.350 — — 0.4862 —

e — 0.650 — — 0.0256 —

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

ccc — — 0.100 — — 0.0039

k 0°3.5°7° 0°3.5°7°

1. Values in inches are converted from mm and rounded to 4 decimal digits

90/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Package characteristics

5W_ME

L

A1 K

L1

c

A

A2

ccc

C

D

D1

D3

E3

E1 E

32

33

48

49

b

64

1

Pin 1
identification

16

17

Figure 45. LQFP 64-pin low profile quad flat package (10 x 10)

Table 53. LQFP 64-pin low profile quad flat package mechanical data

mm inches

(1)

Dim.

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079

D 11.800 12.000 12.200 0.4646 0.4724 0.4803

D1 9.800 10.000 10.200 0.3858 0.3937 0.4016

D3 — 7.500 — — 0.2953 —

E 11.800 12.000 12.200 0.4646 0.4724 0.4803

E1 9.800 10.000 10.200 0.3858 0.3937 0.4016

E3 — 7.500 — — 0.2953 —

e — 0.500 — — 0.0197 —

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

ccc — — 0.080 — — 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits

Doc ID 14395 Rev 9 91/110

Package characteristics STM8AF52/62xx, STM8AF51/61xx





 





















7?&0

Figure 46. LQFP 64-pin recommended footprint

1. Drawing is not to scale. Dimensions are in millimeters.

92/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Package characteristics

5B_ME

L

A1 K

L1

c

A

A2

ccc

C

D

D1

D3

E3

E1 E

24

25

36

37

b

48

1

Pin 1
identification

12

13

Figure 47. LQFP 48-pin low profile quad flat package (7 x 7)

Table 54. LQFP 48-pin low profile quad flat package mechanical data

mm inches

(1)

Dim.

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 — 5.500 — — 0.2165 —

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 — 5.500 — — 0.2165 —

e — 0.500 — — 0.0197 —

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

ccc — — 0.080 — — 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits

Doc ID 14395 Rev 9 93/110

Package characteristics STM8AF52/62xx, STM8AF51/61xx

Figure 48. LQFP 48-pin recommended footprint

















1. Drawing is not to scale. Dimensions are in millimeters.





















"?&0

94/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Package characteristics

5V_ME

L

A1 K

L1

c

A

A2

ccc

C

D

D1

D3

E3

E1 E

16

17

24

25

b

32

1

Pin 1
identification

8

9

Figure 49. LQFP 32-pin low profile quad flat package (7 x 7)

Table 55. LQFP 32-pin low profile quad flat package mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

(1)

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.300 0.370 0.450 0.0118 0.0146 0.0177

c 0.090 — 0.200 0.0035 — 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 — 5.600 — — 0.2205 —

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 — 5.600 — — 0.2205 —

e — 0.800 — — 0.0315 —

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

ccc — — 0.100 — — 0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits

Doc ID 14395 Rev 9 95/110

Package characteristics STM8AF52/62xx, STM8AF51/61xx











6?&0

Figure 50. LQFP 32-pin recommended footprint

1. Drawing is not to scale. Dimensions are in millimeters.

96/110 Doc ID 14395 Rev 9

STM8AF52/62xx, STM8AF51/61xx Package characteristics

Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5)

Seating plane

C

A

ddd C

A3

A1

D

e

9

8

b

E2

1

Pin # 1 ID
R = 0.30

Table 56. VFQFPN 32-lead very thin fine pitch quad flat no-lead package

32

D2

Bottom view

16

17

E

24

L

L

42_ME

mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

(1)

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 0.000 0.020 0.050 0.000 0.0008 0.0020

A3 — 0.200 — — 0.0079 —

b 0.180 0.250 0.300 0.0071 0.0098 0.0118

D 4.850 5.000 5.150 0.1909 0.1969 0.2028

D2 3.400 3.450 3.500 0.1339 0.1358 0.1378

E 4.850 5.000 5.150 0.1909 0.1969 0.2028

E2 3.400 3.450 3.500 0.1339 0.1358 0.1378

e — 0.500 — — 0.0197 —

L 0.300 0.400 0.500 0.0118 0.0157 0.0197

ddd — — 0.080 — — 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits

Doc ID 14395 Rev 9 97/110

Ordering information STM8AF52/62xx, STM8AF51/61xx

STM8A F 62 A A T D XXX

(2)

Y

Product class

8-bit automotive microcontroller

Program memory size

6 = 32 Kbytes

7 = 48 Kbytes

(3)

8 = 64 Kbytes

9 = 96 Kbytes

(3)

A= 128 Kbytes

Package type

T = LQFP

U = VFQFPN

Example:

Device family

51 = Silicon rev X, CAN/LIN

(3)

61 = Silicon rev X, LIN only

(3

52 = Silicon rev U and rev T, CAN/LIN

62 = Silicon rev U and rev T, LIN only

Program memory type

F = Flash + EEPROM

P = FASTROM

H = Flash no EEPROM

(3)

Temperature range

A = -40 to 85 °C

B = -40 to 105 °C

(3)

C = -40 to 125 °C

D = -40 to 150 °C

(4)

Pin count

6 = 32 pins

8 = 48 pins

9= 64 pins

A = 80 pins

Packing

Y = Tray

U = Tube

X = Tape and reel compliant with EIA 481-C

12 Ordering information

Figure 52. Ordering information scheme

(1)

98/110 Doc ID 14395 Rev 9

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further

2. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device

3. Not recommended for new design.

4. Available on STM8AFx2xx devices.

information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.

contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed
to be replaced later by the target silicon.

STM8AF52/62xx, STM8AF51/61xx STM8 development tools

13 STM8 development tools

Development tools for the STM8A microcontrollers include the

● STice emulation system offering tracing and code profiling

● STVD high-level language debugger including assembler and visual development

environment - seamless integration of third party C compilers

● STVP Flash programming software

In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.

13.1 Emulation and in-circuit debugging tools

The STM8 tool line includes the STice emulation system offering a complete range of
emulation and in-circuit debugging features on a platform that is designed for versatility and
cost-effectiveness. In addition, STM8A application development is supported by a low-cost
in-circuit debugger/programmer.

The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including tracing, profiling and code coverage
analysis to help detect execution bottlenecks and dead code.

In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.

13.1.1 STice key features

● Program and data trace recording up to 128 K records

● Advanced breakpoints with up to 4 levels of conditions

● Data breakpoints

● Real-time read/write of all device resources during emulation

● Occurrence and time profiling and code coverage analysis (new features)

● In-circuit debugging/programming via SWIM protocol

● 8-bit probe analyzer

● 1 input and 2 output triggers

● USB 2.0 high-speed interface to host PC

● Power supply follower managing application voltages between 1.62 to 5.5 V

● Modularity that allows you to specify the components you need to meet your

development requirements and adapt to future requirements

● Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

Doc ID 14395 Rev 9 99/110

STM8 development tools STM8AF52/62xx, STM8AF51/61xx

13.2 Software tools

STM8 development tools are supported by a complete, free software package from STMi­croelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer
(STVP) software interface. STVD provides seamless integration of the Cosmic and Raiso
nance C compilers for STM8.

13.2.1 STM8 toolset

The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:

ST visual develop

Full-featured integrated development environment from STMicroelectronics, featuring:

● Seamless integration of C and ASM toolsets

● Full-featured debugger

● Project management

● Syntax highlighting editor

● Integrated programming interface

● Support of advanced emulation features for STice such as code profiling and coverage

-

ST visual programmer (STVP)

Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A
microcontroller’s Flash memory. STVP also offers project mode for saving programming
configurations and automating programming sequences.

13.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface. Available toolchains include:

C compiler for STM8

All compilers are available in free version with a limited code size depending on the
compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,
and www.iar.com.

STM8 assembler linker

Free assembly toolchain included in the STM8 toolset, which allows you to assemble and
link your application source code.

100/110 Doc ID 14395 Rev 9