ST STM809, STM810, STM811, STM812 User Manual

STM809, STM810

STM811, STM812

Reset circuit

Features

■ Precision monitoring of 3 V, 3.3 V, and 5 V

supply voltages

■ Two output configurations

– Push-pull RST
– Push-pull RST output (STM810/812)

■ 140 ms reset pulse width (min)

■ Low supply current - 6 µA (typ)

■ Guaranteed RST/RST assertion down to

V

= 1.0 V

CC

■ Operating temperature:

–40 °C to 85 °C (industrial grade)

■ Lead-free, small SOT23 and SOT143 package

output (STM809/811)

SOT23-3 (WX)

SOT143-4 (W1)

Table 1. Device summary

Active-low reset Active-high reset Manual reset input Package

STM809 ✔ SOT23-3

STM810 ✔ SOT23-3

STM811 ✔✔SOT143-4

STM812 ✔✔SOT143-4

January 2010 Doc ID 9873 Rev 5 1/21

www.st.com

1

Contents STM809/810/811/812

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Push-button reset input (STM811/812) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Negative-going V

2.4 Valid RST

output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CC

3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21 Doc ID 9873 Rev 5

STM809/810/811/812 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. SOT23-3 – 3-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 16

Table 7. SOT143-4 – 4-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . 17

Table 8. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Marking description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Doc ID 9873 Rev 5 3/21

List of figures STM809/810/811/812

List of figures

Figure 1. Logic diagram (STM809/810) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic diagram (STM811/812) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. SOT23-3 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. SOT143-4 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. Supply current vs. temperature, L/M/R/S/T (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. Power-down reset delay vs. temperature - V
Figure 9. Power-down reset delay vs. temperature - V
Figure 10. Power-up t

Figure 11. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 12. Max transient duration NOT causing reset pulse vs. reset comparator overdrive . . . . . . . 11

Figure 13. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 14. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 15. SOT23-3 – 3-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 16. SOT143-4 – 4-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . 17

vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

rec

= VTH – VCC (L/M) . . . . . . . . . . . . . . . . . . . 9

OD

= VTH – VCC (R/S/T) . . . . . . . . . . . . . . . . 10

OD

4/21 Doc ID 9873 Rev 5

STM809/810/811/812 Description

1 Description

The STM809/810/811/812 microprocessor reset circuits are low-power supervisory devices
used to monitor power supplies. They perform a single function: asserting a reset signal
whenever the V
V

has risen above the preset threshold for a minimum period of time (t

CC

STM811/812 also provide a push-button reset input (MR

Figure 1. Logic diagram (STM809/810)

supply voltage drops below a preset value and keeping it asserted until

CC

rec

). The

).

V

CC

STM809/810

V

1. For STM810

Figure 2. Logic diagram (STM811/812)

MR

1. For STM812

STM811/812

RST (RST)

SS

V

CC

RST (RST)

V

SS

(1)

AI07832

(1)

AI07831

Table 2. Signal names

V

SS

RST Active-low reset output

(1)

RST

V

CC

(2)

MR

1. STM810/812 only

2. STM811/812 only

Ground

Active-high reset output

Supply voltage

Manual reset input

Doc ID 9873 Rev 5 5/21

Description STM809/810/811/812

Figure 3. SOT23-3 connections

V

SS

RST (RST)

(For STM810)

Figure 4. SOT143-4 connections

V

SS

RST (RST)

(For STM812)

Figure 5. Block diagram

V

CC

V

RST

(1)

MR

1
2

1
2

COMPARE

DEBOUNCE

3

4
3

V

V

CC

MR

CC

t

rec

Generator

RST

AI07833

AI07834

(2)

1. STM811/812 only

2. RST for STM810/812

Figure 6. Hardware hookup

V

CC

V

CC

STM809/810/

811/812

(2)

Push-button

RESET

1. STM809/811 only (RST for STM810/812)

2. STM811/812 only

MR

V

6/21 Doc ID 9873 Rev 5

SS

RST

(1)

MCU

RESET
Input

AI07835

V

CC

V

SS

AI07836

STM809/810/811/812 Operation

2 Operation

2.1 Reset output

The STM809/810/811/812 microprocessor reset circuit asserts a reset signal to the MCU
whenever V
(MR

) is taken low (see Figure 14 on page 13). RST (active high for STM810/812) is

guaranteed valid down to V

During power-up, once V
the reset time-out period, t

If V

drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

CC

low for at least the reset time-out period. Any time V
internal timer clears. The reset timer starts when V
active-low reset (RST

2.2 Push-button reset input (STM811/812)

goes below the reset threshold (V

CC

= 1 V (0° to 70°C).

CC

exceeds the reset threshold an internal timer keeps RST low for

CC

. After this interval, RST returns high.

rec

) and active-high reset (RST) both source and sink current.

), or when the push-button reset input

RST

goes below the reset threshold, the

CC

returns above the reset threshold. The

CC

A logic low on MR asserts RST. RST remains asserted while MR is low, and for t
returns high. The MR

input has an internal 20 kΩ pull-up resistor, allowing it to be left open if
not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector
outputs. Connect a normally open push-button switch from MR
reset function; external debounce circuitry is not required. If the device is used in a noisy
environment, connect a 0.1 µF capacitor from MR
immunity.

2.3 Negative-going VCC transients

The STM809/810/811/812 are relatively immune to negative-going VCC transients (glitches).

Figure 12 on page 11 shows typical transient duration versus reset comparator overdrive

(for which the STM809/810/811/812 will NOT generate a reset pulse). The graph was
generated using a negative pulse applied to V
threshold and ending below it by the magnitude indicated (comparator overdrive). The graph
indicates the maximum pulse width a negative V
reset pulse. As the magnitude of the transient increases (further below the threshold), the
maximum allowable pulse width decreases. Any combination of duration and overdrive
which lies under the curve will NOT generate a reset signal. Typically, a V
goes 100 mV below the reset threshold and lasts 20 µs or less will not cause a reset pulse.
A 0.1 µF bypass capacitor mounted as close as possible to the V
transient immunity.

rec

to GND to create a manual

to GND to provide additional noise

, starting at 0.5V above the actual reset

CC

transient can have without causing a

CC

transient that

CC

pin provides additional

CC

after it

Doc ID 9873 Rev 5 7/21