ST STM690A, STM692A, STM703, STM704, STM802 User Manual

STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9

5 V supervisor with battery switchover

Features

■5 V operating voltage

■NVRAM supervisor for external LPSRAM

■Chip-enable gating (STM818 only) for external LPSRAM (7 ns max prop delay)

■RST and RST outputs

■200 ms (typ) trec

■Watchdog timer - 1.6 sec (typ)

■Automatic battery switchover

■Low battery supply current - 0.4 µA (typ)

■Power-fail comparator (PFI/PFO)

■Low supply current - 40 µA (typ)

■Guaranteed RST (RST) assertion down to VCC = 1.0 V

■Operating temperature:

–40 °C to +85 °C (industrial grade)

■RoHS compliance

–Lead-free components are compliant with the RoHS directive

Table 1. Device summary

8

1

SO8 (M)

TSSOP8 3 x 3 (DS)(1)

1. Contact local ST sales office for availability.

				Watchdog	Active-low	Active-	Manual	Battery	Power-fail	Chip-	Battery
	Part number						reset	switch-		enable	freshness
				input	RST(1)	high RST			comparator
							input(1)	over		gating	seal
	STM690A
	STM692A
	STM703
	STM704
	STM802L/M
	STM805L
	STM817L/M
	STM818L/M
	STM819L/M
	1. All		and RST outputs are push-pull.
		RST
	August 2010					Doc ID 10522 Rev 10					1/43

www.st.com

Contents	STM690A/692A/703/704/802/805/817/818/819

Contents

1	Description . .			.		. .			. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	1.1	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .								8
		1.1.1								8
			MR
		1.1.2		WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						8
		1.1.3								8
				RST
		1.1.4		RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						8
		1.1.5		VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						. 9
		1.1.6		VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						9
		1.1.7								9
				E
		1.1.8			CON
				E						9
		1.1.9		PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						9
		1.1.10								9
				PFO

2	Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	2.1	Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	2.2	Push-button reset input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . .	13
	2.3	Watchdog input (NOT available on STM703/704/819) . . . . . . . . . . . . . . .	13
	2.4	Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	2.5	Chip-enable gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.6	Chip-enable input (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.7	Chip-enable output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.8	Power-fail input/output (NOT available on STM818) . . . . . . . . . . . . . . . .	16
	2.9	Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	2.10	Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . .	17
	2.11	Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	2.12	Battery freshness seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . .	19
3	Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
4	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
5	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32

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STM690A/692A/703/704/802/805/817/818/819		Contents
6	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 37
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 40
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 42

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List of tables	STM690A/692A/703/704/802/805/817/818/819

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 8. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data. . . . . . 38 Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 39 Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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STM690A/692A/703/704/802/805/817/818/819	List of figures

List of figures

Figure 1. Logic diagram (STM690A/692/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Logic diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. STM690A/692A/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. STM703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. STM818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Block diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Block diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Block diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. Chip-enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. Power-fail comparator waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. Power-fail comparator waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . . . . 17 Figure 15. Using a SuperCap™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17. VCC to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18. VBAT to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 19. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 20. Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 21. VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 22. Reset comparator propagation delay vs. temperature (other than STM817/818/819) . . . . 22

Figure 23. Reset comparator propagation delay vs. temperature (VBAT = 3.0 V; STM817/818/819) . 23

Figure 24. Power-up tREC vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 25. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 26. Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27. E to ECON on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 28. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 29. Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26 Figure 30. Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26 Figure 31. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 32. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 33. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 34. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 35. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 36. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 37. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 38. E to ECON propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 39. E to ECON propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 40. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 41. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 42. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 43. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing . . . 38 Figure 44. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . . 39

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Description	STM690A/692A/703/704/802/805/817/818/819

1 Description

The STM690A/692A/703/704/802/805/817/818/819 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset

output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM703/704/819) as well as a power-fail comparator (except for STM818) to provide the system with an early warning of impending power failure.

These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.

Figure 1. Logic diagram (STM690A/692/802/805/817)

		VCC VBAT
	WDI			VOUT
		STM690A/
		692A/802/			RST(RST)(1)
	PFI	805/817
				PFO

VSS

AI07894

1. For STM805, reset output is active-high.

Figure 2. Logic diagram (STM703/704/819)

VCC VBAT

VOUT

MR

STM703/

704/819

PFI

RST

PFO

VSS	AI07895

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STM690A/692A/703/704/802/805/817/818/819

Description

Figure 3.

Logic diagram (STM818)

VCC VBAT

WDI

VOUT

STM818

RST

E

ECON

VSS

AI07896

Table 2.

Signal names

MR

Push-button reset input

WDI

Watchdog input

Active-low reset output

RST

RST

Active-high reset outpu

(1)

Chip-enable input

E

(1)

Conditioned chip-enable output

ECON

VOUT

Supply voltage output

VCC

Supply voltage

VBAT

Backup supply voltage

PFI

Power-fail input

Power-fail output

PFO

VSS

Ground

1.

STM818

Figure 4. STM690A/692A/802/805/817 connections

SO8/TSSOP8

VOUT	1	8		VBAT
VCC	2	7		RST(RST)(1)
VSS	3	6		WDI
PFI	4	5		PFO

AI07889

1. For STM805, reset output is active-high.

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Description

STM690A/692A/703/704/802/805/817/818/819

Figure 5.

STM703/704/819 connections

SO8/TSSOP8

VOUT

VBAT

1

8

VCC

2

7

RST

VSS

3

6

MR

PFI

4

5

PFO

AI07890

Figure 6.

STM818 connections

SO8/TSSOP8

VOUT

VBAT

1

8

VCC

2

7

RST

VSS

3

6

WDI

E

4

5

ECON

AI07892

1.1Pin descriptions

1.1.1MR

A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low

and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if

unused.

1.1.2WDI

If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge.

The watchdog function can be disabled by allowing the WDI pin to float.

1.1.3RST

Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold

or when MR is a logic low. It remains low for trec after either VCC rises above the reset

threshold, the watchdog triggers a reset, or MR goes from low to high.

1.1.4RST

Pulses high for trec when triggered, and stays high whenever VCC is above the reset

threshold or when MR is a logic high. It remains high for trec after either VCC falls below the

reset threshold, the watchdog triggers a reset, or MR goes from high to low.

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STM690A/692A/703/704/802/805/817/818/819	Description

1.1.5VOUT

When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through a P- channel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT.

1.1.6VBAT

When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.

1.1.7E

The input to the chip-enable gating circuit. Connect to ground if unused.

1.1.8ECON

ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is

asserted, ECON will remain low for 15 µs or until E goes high, whichever occurs first. In the

disabled mode, ECON is pulled up to VOUT.

1.1.9PFI

When PFI is less than VPFI or when VCC falls below 2.4 V (or VSO), PFO goes low;

otherwise, PFO remains high. Connect to ground if unused.

1.1.10PFO

When PFI is less than VPFI, or VCC falls below 2.4 V (or VSO), PFO goes low; otherwise,

PFO remains high. Leave open if unused. Output type is push-pull.

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Description																STM690A/692A/703/704/802/805/817/818/819
Table 3.				Pin description
												Pin
							STM690A							STM703		Name														Function
							STM692A
STM818														STM704	STM805
									STM802
														STM819
									STM817
-						-								6	-													Push-button reset input
																			MR
6						6								-	6			WDI										Watchdog input
7						7								7	-													Active-low reset output
																		RST
-						-								-	7			RST										Active-high reset output
1						1								1	1		VOUT											Supply output for external LPSRAM
2						2								2	2			VCC										Supply voltage
8						8								8	8		VBAT											Backup battery input
4						-								-	-													Chip-enable input
																					E
5						-								-	-					CON								Conditioned chip-enable output
																	E
-						4								4	4				PFI									Power-fail input
-						5								5	5													Power-fail output (push-pull)
																		PFO
3						3								3	3			VSS										Ground
Figure 7.				Block diagram (STM690A/692A/802/805/817)
	VCC																													VOUT
					VBAT

VSO

COMPARE

VRST

COMPARE

WATCHDOG

trec

(1)

WDI

RST(RST)

TIMER

Generator

PFI

COMPARE

VPFI

PFO

AI07897

1. For STM805, reset output is active-high.

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STM690A/692A/703/704/802/805/817/818/819

Description

Figure 8. Block diagram (STM703/704/819)

VCC

VOUT

VBAT

VSO

COMPARE

VRST

COMPARE

trec

RST

MR

Generator

PFI

COMPARE

VPFI

PFO

AI07898

Figure 9. Block diagram (STM818)

VCC VOUT

VBAT

VSO

COMPARE

VRST

COMPARE

WATCHDOG

trec

WDI

RST

TIMER

Generator

ECON OUTPUT

CONTROL

E ECON

AI07899a

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Description	STM690A/692A/703/704/802/805/817/818/819

Figure 10. Hardware hookup

Unregulated	Regulator
	VIN	VCC	VCC		VOUT		VCC
Voltage
							VCC
			STM690A/692A/				LPSRAM
			703/704/802/805/
		0.1 F
			817/818/819				E
							E
						0.1	F
			WDI(1)
	From Microprocessor
			E(2)	E	(2)
	R1				CON
			PFI(3)	PFO(3)		To Microprocessor NMI
	R2				(5)
			MR(4)			To Microprocessor Reset
		Push-Button		RST
			VBAT
							AI07893

1.For STM690A/692A/802/805/817/818.

2.For STM818 only.

3.Not available on STM818.

4.For STM703/704/819.

5.Active high on STM805.

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STM690A/692A/703/704/802/805/817/818/819	Operation

2 Operation

2.1Reset output

The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or

when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM805) for 0V < VCC < VRST if VBAT is greater than 1 V. Without a backup

battery, RST is guaranteed valid down to VCC =1 V.

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for

the reset time-out period, trec. After this interval RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold.

2.2Push-button reset input (STM703/704/819)

A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 41) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used.

2.3Watchdog input (NOT available on STM703/704/819)

The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD(1.6 sec typ), the reset is asserted. The internal watchdog timer is cleared by either:

1.a reset pulse, or

2.by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (tWD + trec).

The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure 42).

Note: 1 The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and the maximum allowable load capacitance is 200 pF.

2 Input pulses less than 20 ns will be ignored.

Doc ID 10522 Rev 10

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