Features
STM706T/S/R, STM706P, STM708T/S/R
3 V supervisor
■ Precision V
monitor
CC
– STM706/708
T: 3.00 V
S: 2.88 V
R: STM706P: 2.59 V
■ RST and RST outputs
■ 200 ms (typ.) t
Watchdog timer - 1.6 s (typ.)
■
■ Manual reset input (MR)
■ Power-fail comparator (PFI/PFO)
■ Low supply current - 40 µA (typ.)
■ Guaranteed RST (RST) assertion down to
V
= 1.0 V
CC
■ Operating temperature: –40 °C to 85 °C
≤
≤
V
V
rec
RST
RST
≤
≤
3.15 V
3.00 V
≤
V
RST
≤
2.70 V
(industrial grade)
■ RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Table 1. Device summary
8
1
SO8 (M)
TSSOP8 3x3 (DS)
1. Contact local ST sales office for availability.
(1)
Watchdog
input
Watchdog
output
(1)
Active-low
(1)
RST
Active-high
(1)
RST
Manual
reset input
Power-fail
comparator
STM706T/S/R ✓✓ ✓ ✓ ✓
STM706P
(2)
✓✓ ✓ ✓ ✓
STM708T/S/R ✓✓✓✓
1. Push-pull output.
2. The STM706P is identical to the STM706R, except its reset output is active-high.
September 2011 Doc ID 10518 Rev 11 1/32
www.st.com
1
Contents STM706T/S/R, STM706P, STM708T/S/R
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 WDO
2.4 RST
2.5 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 PFO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Watchdog input (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . 11
3.4 Watchdog output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . 11
3.5 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Ensuring a valid reset output down to V
3.7 Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 13
= 0 V . . . . . . . . . . . . . . . . . . . 12
CC
4 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R List of tables
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 10518 Rev 11 3/32
List of figures STM706T/S/R, STM706P, STM708T/S/R
List of figures
Figure 1. Logic diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. STM706T/S/R and STM706P SO8 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STM706T/S/R and STM706P TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM708T/S/R SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. STM708T/S/R TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Block diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Block diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. V
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Power-up t
Figure 16. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Watchdog timeout period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. PFI to PFO
Figure 19. Output voltage vs. load current (V
Figure 20. RST
Figure 21. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. MR
Figure 28. Watchdog timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. SO8 – 8-lead plastic small outline, 150 mils body width,
Figure 30. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 28
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PFI
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
rec
propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
= 5 V; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
package mechanical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CC
4/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Description
1 Description
The STM70x supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the V
for an out-of-tolerance condition. When an invalid V
(RST
) is forced low (or high in the case of RST).
condition occurs, the reset output
CC
These devices also offer a watchdog timer (except for STM708T/S/R) as well as a power-fail
comparator to provide the system with an early warning of impending power failure.
The STM706P is identical to the STM706R, except its reset output is active-high. These
devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP
package.
Figure 1. Logic diagram (STM706T/S/R and STM706P)
V
CC
CC
input
WDI
STM706T/S/R,
MR
PFI
1. For STM706P only.
STM706P
Figure 2. Logic diagram (STM708T/S/R)
V
CC
MR
PFI
STM708T/S/R
WDO
RST (RST)
PFO
V
SS
RST
RST
PFO
(1)
AI08841
V
SS
AI08842
Doc ID 10518 Rev 11 5/32
Description STM706T/S/R, STM706P, STM708T/S/R
Table 2. Signal names
Symbol Name
MR
Push-button reset input
WDI Watchdog input
WDO
RST
RST
V
CC
(1)
Watchdog output
Active-low reset output
Active-high reset output
Supply voltage
PFI Power-fail input
PFO
Power-fail output
V
Ground
SS
NC No connect
1. For STM706P and STM708T/S/R only.
Figure 3. STM706T/S/R and STM706P SO8 connections
SO8
8
7
6
5
WDO
RST(RST)
WDI
PFO
SS
1
2
3
4
MR
V
CC
V
PFI
(1)
AI08837
1. For STM706P reset output is active-high.
Figure 4. STM706T/S/R and STM706P TSSOP8 connections
TSSOP8
1
2
3
4
8
WDI
7
PFO
PFI
6
V
5
SS
RST(RST)
WDO
V
1. For STM706P reset output is active-high.
(1)
MR
CC
AI08838
6/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Description
Figure 5. STM708T/S/R SO8 connections
SO8
RST
MR
V
CC
V
SS
PFI
1
2
3
4
8
7
RST
NC
6
5
PFO
AI08839
Figure 6. STM708T/S/R TSSOP8 connections
TSSOP8
RST
RST
MR
V
CC
1
2
3
4
8
NC
7
PFO
6
PFI
V
5
SS
AI08840
Doc ID 10518 Rev 11 7/32
Pin descriptions STM706T/S/R, STM706P, STM708T/S/R
2 Pin descriptions
2.1 MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
2.2 WDI
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or
WDO
sees a rising or falling edge.
The watchdog function cannot be disabled by allowing the WDI pin to float.
2.3 WDO
after MR returns high. This active-low input has an internal pull-up. It can be
rec
) is triggered. The internal watchdog timer clears while reset is asserted or when WDI
WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until
a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO
goes low when V
goes high as soon as V
Note: For those devices with a WDO
is connected to MR
falls below the reset threshold; however, unlike the reset output, WDO
CC
exceeds the reset threshold. Output type is push-pull.
CC
.
2.4 RST
Pulses low for t
threshold or when MR
reset threshold, the watchdog triggers a reset, or MR
when triggered, and stays low whenever VCC is below the reset
rec
is a logic low. It remains low for t
2.5 RST
Pulses high for t
threshold or when MR
reset threshold, the watchdog triggers a reset, or MR
when triggered, and stays high whenever VCC is above the reset
rec
is a logic high. It remains high for t
2.6 PFI
also
output, a watchdog timeout will not trigger reset unless WDO
after either VCC rises above the
rec
goes from low to high.
after either VCC falls below the
rec
goes from high to low.
When PFI is less than V
ground if unused.
8/32 Doc ID 10518 Rev 11
, PFO goes low; otherwise, PFO remains high. Connect to
PFI
STM706T/S/R, STM706P, STM708T/S/R Pin descriptions
2.7 PFO
When PFI is less than V
push-pull. PFO
during the period PFO
Table 3. Pin description
pin is not supposed to be forced low by a processor. MR input is gated off
, PFO goes low; otherwise, PFO remains high. Output type is
PFI
is forced low. Leave open if unused.
Pin
STM706P STM706T/S/R STM708T/S/R
Name Function
SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8
1 3 1 3 1 3 MR
Push-button reset input
6 8 6 8 — — WDI Watchdog input
8 2 8 2 — — WDO
— — 7 1 7 1 RST
Watchdog output (push-pull)
Active-low reset output
7 1 — — 8 2 RST Active-high reset output
2 4 2 4 2 4 V
Supply voltage
CC
4 6 4 6 4 6 PFI Power-fail input
5 7 5 7 5 7 PFO
3 5 3 5 3 5 V
Power-fail output (push-pull)
Ground
SS
— — — — 6 8 NC No connect
Figure 7. Block diagram (STM706T/S/R and STM706P)
WDI
V
CC
MR
PFI
1. For STM706P only.
V
CC
WDI
transitional
detector
V
RST
V
PFI
WATCHDOG
TIMER
COMPARE
COMPARE
t
rec
generator
WDO
RST (RST)
PFO
(1)
AI08829
Doc ID 10518 Rev 11 9/32
Pin descriptions STM706T/S/R, STM706P, STM708T/S/R
Figure 8. Block diagram (STM708T/S/R)
V
CC
MR
V
RST
V
CC
COMPARE
t
rec
generator
RST
RST
PFI
Figure 9. Hardware hookup
Unregulated
voltage
R1
R2
Regulator
V
IN
V
PFI
V
CC
0.1 μF
From microprocessor
Push-button
COMPARE
V
CC
STM706T/S/R;
STM706P;
STM708T/S/R
(1)
WDI
PFI
MR
WDO
PFO
RST
RST
(2)
(1)
PFO
AI08830
To microprocessor IRQ
To microprocessor NMI
To microprocessor reset
1. For STM706T/S/R and STM706P.
2. For STM706P and STM708T/S/R.
10/32 Doc ID 10518 Rev 11
AI08843
STM706T/S/R, STM706P, STM708T/S/R Operation
3 Operation
3.1 Reset output
The STM70x supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (V
push-button reset input (MR
STM706P and STM708T/S/R) for V
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset timeout period, t
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
If V
CC
low for at least the reset timeout period (t
the internal timer clears. The reset timer starts when V
3.2 Push-button reset input
), a watchdog timeout occurs (if WDO is connected to MR), or when the
RST
) is taken low. RST is guaranteed to be a logic low (logic high for
< V
CC
. After this interval RST returns high.
rec
down to VCC =1 V for TA = 0 °C to 85 °C.
RST
). Any time VCC goes below the reset threshold
rec
returns above the reset threshold.
CC
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
Figure 27) after it returns high. The MR
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain / collector outputs. Connect a normally open momentary switch from MR
to create a manual reset function; external debounce circuitry is not required. If MR
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR
not used.
to GND to provide additional noise immunity. MR may float, or be tied to VCC when
input has an internal 40 kΩ pull-up resistor, allowing
3.3 Watchdog input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within t
asserted. The internal 1.6s timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
See Figure 28 for STM706T/S/R and STM706P.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
(1.6 s), the watchdog output pin (WDO) is
WD
3.4 Watchdog output (STM706T/S/R and STM706P)
(see
rec
to GND
is driven
When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has
not yet timed out. However, unlike the reset output, WDO
exceeds the reset threshold. WDO
to the MR
input.
may be used to generate a reset pulse by connecting it
Doc ID 10518 Rev 11 11/32
goes high as soon as VCC
Operation STM706T/S/R, STM706P, STM708T/S/R
3.5 Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V
output (PFO
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the V
V
PFI
processor drops below the minimum operating voltage.
comparator). If PFI is less than the power-fail threshold (V
RST
), the power-fail
PFI
) will go low. This function is intended for use as an undervoltage detector to
regulator. The voltage divider can be set up such that the voltage at PFI falls below
CC
several milliseconds before the regulated VCC input to the STM70x or the micro-
If the comparator is unused, PFI should be connected to V
PFO
may be connected to MR on the STM70x so that a low voltage on PFI will generate
and PFO left unconnected.
SS
a reset output.
3.6 Ensuring a valid reset output down to VCC = 0 V
When VCC falls below 1 V, the state of the RST output can no longer be guaranteed, and
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST
Figure 10. Reset output valid to ground circuit
to ground during this low voltage condition (see Figure 10).
STM70x
RST
R1
AI08844
12/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Operation
3.7 Interfacing to microprocessors with bi-directional reset pins
Microprocessors with bi-directional reset pins can contend with the STM70x reset output.
For example, if the reset output is driven high and the micro wants to pull it low, signal
contention will result. To prevent this from occurring, connect a 4.7kΩ resistor between the
reset output and the micro's reset I/O as in Figure 11.
Figure 11. Interfacing to microprocessors with bi-directional reset I/O
Buffered reset to other
system components
V
CC
STM70x
GND
4.7 kΩ
RST
V
CC
Microprocessor
RST
GND
AI08845
Doc ID 10518 Rev 11 13/32
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
4 Typical operating characteristics
Typical values are at TA = 25 °C.
Figure 12. Supply current vs. temperature (no load)
30
25
20
15
VCC = 2.7 V
10
Supply current (µA)
5
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
0
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09141b
14/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
Figure 13. V
1.270
1.265
1.260
1.255
1.250
threshold (V)
1.245
PFI
1.240
V
1.235
1.230
1.225
threshold vs. temperature
PFI
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09142b
Figure 14. Reset comparator propagation delay vs. temperature
30
28
26
24
22
20
18
Propagation delay (µs)
16
14
12
10
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09143b
Doc ID 10518 Rev 11 15/32
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
Figure 15. Power-up t
vs. temperature
rec
240
235
230
225
(ms)
rec
t
220
215
210
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
Figure 16. Normalized reset threshold vs. temperature
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI09144b
1.004
1.002
threshold
1.000
reset
0.998
Normalized
0.996
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09145b
16/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
Figure 17. Watchdog timeout period vs. temperature
1.90
1.85
1.80
period (s)
1.75
timeout
1.70
Watchdog
1.65
1.60
–40 –20 0 20 40 60 80 100 120
Temperature (˚C)
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI09146b
Figure 18. PFI to PFO propagation delay vs. temperature
4.0
3.0
2.0
1.0
PFI to PFO propagation dela
0.0
–40 –20 0 20 40 60 80 100 120
Temperature (˚C)
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
AI09148b
Doc ID 10518 Rev 11 17/32
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C)
5.00
4.98
(V)
OUT
V
4.96
4.94
0 1020304050
I
(mA)
OUT
AI10496
Figure 20. RST output voltage vs. supply voltage
5
4
3
(V)
RST
2
V
1
0
500 ms / div
V
V
RST
CC
5
4
3
VCC (V)
2
1
0
AI09149b
18/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
Figure 21. RST output voltage vs. supply voltage
5
4
3
(V)
RST
2
V
1
0
500 ms / div
Figure 22. Power-fail comparator response time (assertion)
5V
PFO
V
V
RST
CC
5
4
3
VCC (V)
2
1
0
AI09150b
1V/div
1.3 V
PFI
0V
500 mV / div
0V
500 ns / div
AI09153b
Doc ID 10518 Rev 11 19/32
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
Figure 23. Power-fail comparator response time (de-assertion)
5V
PFO
0V
PFI
0V
500 ns / div
Figure 24. Maximum transient duration vs. reset threshold overdrive
6000
5000
1V/div
1.3 V
500 mV / div
AI09154b
4000
Reset occurs
duration (µs)
3000
Transient
2000
1000
0
above the cur ve
Reset comparator ov erdrive, V
RST
20/32 Doc ID 10518 Rev 11
– VCC (V)
0111.010.0100.0
AI09156b
STM706T/S/R, STM706P, STM708T/S/R Maximum ratings
5 Maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
T
STG
T
SLD
(2)
V
IO
V
CC
I
O
P
D
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. Negative undershoot of –1.5 V for up to 10 ns or positive overshoot of V
allowable on the WDI and MR input pins.
Storage temperature (VCC off) –55 to 150 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltage –0.3 to VCC +0.3 V
Supply voltage –0.3 to 7.0 V
Output current 20 mA
Power dissipation 320 mW
+ 1.5 V for up to 10 ns is
CC
Doc ID 10518 Rev 11 21/32
DC and AC parameters STM706T/S/R, STM706P, STM708T/S/R
6 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Ta bl e 5 , operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5. Operating and AC measurement conditions
Parameter STM70x Unit
V
supply voltage 1.0 to 5.5 V
CC
Ambient operating temperature (T
Input rise and fall times
Input pulse voltages 0.2 to 0.8 V
Input and output timing ref. voltages 0.3 to 0.7 V
) –40 to 85 °C
A
≤
5 ns
V
CC
V
CC
Figure 25. AC testing input/output waveforms
0.8 V
CC
0.2 V
CC
Figure 26. Power-fail comparator waveform
V
CC
V
RST
PFO
0.7 V
0.3 V
CC
CC
t
AI02568
rec
RST
22/32 Doc ID 10518 Rev 11
AI08860a
STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters
Figure 27. MR timing waveform
MR
t
MLRL
(1)
RST
t
MLMH
t
rec
1. RST for STM706P and STM708T/S/R.
Figure 28. Watchdog timing (STM706T/S/R and STM706P)
V
CC
t
RST
WDI
WDO
rec
t
AI07837a
WD
AI08833
Doc ID 10518 Rev 11 23/32
DC and AC parameters STM706T/S/R, STM706P, STM708T/S/R
Table 6. DC and AC characteristics
Symbol Description Test condition
Operating voltage 1.2
V
CC
VCC < 3.6 V 35 50 µA
I
VCC supply current
CC
Input leakage current
(WDI)
Input leakage current
I
(PFI)
LI
Input leakage current
(MR
)
Input high voltage (MR)
V
IH
V
Input high voltage (WDI) V
IH
V
< 5.5 V 40 60 µA
CC
0 V < V
0 V < V
V
(max.) < VCC < 3.6 V 25 80 250 µA
RST
4.5 V < V
4.5 V < V
V
(max.) < VCC < 3.6 V 0.7 VCC V
RST
(max.) < VCC < 5.5 V 0.7 VCC V
RST
< VCC –1 +1 µA
IN
< VCC –25 2 +25 nA
IN
CC
CC
4.5 V < VCC < 5.5 V 0.8 V
V
V
V
V
V
Input low voltage (MR)
IL
Input low voltage (WDI) V
IL
Output low voltage (PFO
OL
RST
, RST, WDO)
Output low voltage (RST)
OL
Output high voltage (RST
OH
RST, WDO
)
,
,
Output high voltage
(PFO
)
V
(max.) < VCC < 3.6 V 0.6 V
RST
(max.) < VCC < 5.5 V 0.3 VCC V
RST
= V
V
CC
RST
I
= 3.2 mA
SINK
I
= 50 µA, VCC = 1.0 V,
SINK
T
= 0 °C to 85 °C
A
I
= 100 µA,
SINK
V
= 1.2 V
CC
= V
= V
= 1 mA,
RST
= 75 µA,
RST
I
SOURCE
V
CC
I
SOURCE
V
CC
(1)
Min. Typ. Max. Unit
(2)
5.5 V
< 5.5 V 75 125 300 µA
< 5.5 V 2.0 V
(max.),
0.3 V
0.3 V
0.3 V
(max.)
(max.)
2.4 V
0.8 V
V
CC
Power-fail comparator
PFI falling
V
PFI input threshold
PFI
(STM70xP/R, VCC = 3.0 V;
STM70xS/T, V
PFD
delay
PFI to PFO propagation
t
24/32 Doc ID 10518 Rev 11
= 3.3 V)
CC
1.20 1.25 1.30 V
2 µs
STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters
Table 6. DC and AC characteristics (continued)
Symbol Description Test condition
Reset thresholds
STM706P/70xR 2.55 2.63 2.70 V
V
RST
Reset threshold
(3)
STM70xS 2.85 2.93 3.00 V
STM70xT 3.00 3.08 3.15 V
(1)
Min. Typ. Max. Unit
Reset threshold
hysteresis
Blank (see Tab le 9 ) 140 200 280
t
RST pulse width
rec
(4)
A
(see Tab le 9) 160 200 280
Push-button reset input
V
(max.) < VCC < 3.6 V 500 ns
t
MLMH
(or tMR)
t
MLRL
(or t
MRD
pulse width
MR
to RST output delay
MR
)
RST
4.5 V < V
V
(max.) < VCC < 3.6 V 750 ns
RST
4.5 V < V
Watchdog timer (STM706T/S/R and STM706P)
STM706P/70xR,
V
t
WD
Watchdog timeout period
CC
STM70xS/70XT,
V
CC
4.5 V < V
WDI pulse width
V
(max.) < VCC < 3.6 V 100 ns
RST
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = V
(min) = 1.0 V for TA = 0 °C to +85 °C.
2. V
CC
3. For V
4. STM706P/STM70xR, V
falling.
CC
= 3 V; STM706xS/STM70xT, VCC = 3.3 V.
CC
20 mV
< 5.5 V 150 ns
CC
< 5.5 V 250 ns
CC
= 3.0 V
1.12 1.60 2.24 s
= 3.3 V
< 5.5 V 50 ns
CC
(max.) to 5.5 V (except where noted).
RST
ms
Doc ID 10518 Rev 11 25/32
Package mechanical data STM706T/S/R, STM706P, STM708T/S/R
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
26/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Package mechanical data
Figure 29. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical
A2
B
e
D
8
1
Note: Drawing is not to scale.
Table 7. SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
Typ. Min. Max. Typ. Min. Max.
A
C
ddd
E
H
LA1
SO-A
mm inches
A — 1.35 1.75 — 0.053 0.069
A1 — 0.10 0.25 — 0.004 0.010
B — 0.33 0.51 — 0.013 0.020
C — 0.19 0.25 — 0.007 0.010
D — 4.80 5.00 — 0.189 0.197
ddd — — 0.10 — — 0.004
E — 3.80 4.00 — 0.150 0.157
e 1.27 — — 0.050 — —
H — 5.80 6.20 — 0.228 0.244
h — 0.25 0.50 — 0.010 0.020
L — 0.40 0.90 — 0.016 0.035
α — 0° 8° — 0° 8°
N 8 8
Doc ID 10518 Rev 11 27/32
Package mechanical data STM706T/S/R, STM706P, STM708T/S/R
Figure 30. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
1
CP
Note: Drawing is not to scale.
Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data
Symbol
Typ. Min. Max. Typ. Min. Max.
5
EE1
4
A1
A2A
eb
L
L1
c
TSSOP8BM
mm inches
A — — 1.10 — — 0.043
A1 — 0.05 0.15 — 0.002 0.006
A2 0.85 0.75 0.95 0.034 0.030 0.037
b — 0.25 0.40 — 0.010 0.016
c — 0.13 0.23 — 0.005 0.009
CP — — 0.10 — — 0.004
D 3.00 2.90 3.10 0.118 0.114 0.122
e 0.65 — — 0.026 — —
E 4.90 4.65 5.15 0.193 0.183 0.203
E1 3.00 2.90 3.10 0.118 0.114 0.122
L 0.55 0.40 0.70 0.022 0.016 0.030
L1 0.95 — — 0.037 — —
α — 0° 6° — 0° 6°
N 8 8
28/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Part numbering
8 Part numbering
Table 9. Ordering information scheme
Example: STM706 T M 6 E
Device type
STM706
STM708
Reset threshold voltage
T: 3.00 V
S: 2.88 V
R, STM706P: 2.59 V ≤
RST
≤
V
RST
≤
V
RST
pulse width
≤
≤
3.15 V
3.00 V
V
RST
≤
2.70 V
Blank = 140 to 280 ms
(1)
A
= 160 to 280 ms
Package
M = SO8
(2)
= TSSOP8
DS
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK
F = ECOPACK
1. Available in SO8 (M) package only.
2. Contact local ST sales office for availability.
®
packages, tubes
®
packages, tape and reel
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 10518 Rev 11 29/32
Part numbering STM706T/S/R, STM706P, STM708T/S/R
Table 10. Marking description
Part number Reset threshold Package Topside marking
STM706P 2.63 V
STM706T 3.08 V
STM706S 2.93 V
STM706R 2.63 V
STM708T 3.08 V
STM708S 2.93 V
STM708R 2.63 V
SO8
706P
TSSOP8
SO8
706T
TSSOP8
SO8
706S
TSSOP8
SO8
706R
TSSOP8
SO8
708T
TSSOP8
SO8
708S
TSSOP8
SO8
708R
TSSOP8
30/32 Doc ID 10518 Rev 11
STM706T/S/R, STM706P, STM708T/S/R Revision history
9 Revision history
Table 11. Document revision history
Date Revision Changes
Oct-2003 1 Initial release.
12-Dec-2003 2
16-Jan-2004 2.1 Add Typical operating characteristics (Figure 13, to 19, 21, to 25).
09-Apr-2004 3 Reformatted; update characteristics (Figure 15, 19, 21, 22, 25; Ta b le 8 ).
25-May-2004 4 Update characteristics (Tab le 3 , Ta b le 6 ).
02-Jul-2004 5 Datasheet promoted; waveform corrected (Ta bl e 2 7 ).
21-Sep-2004 6 Clarify root part numbers; (Figure 2, to 10, 29; Ta bl e 1 , 3, 6, 9).
25-Feb-2005 7 Update typical characteristics (Figure 13 to 25).
02-Nov-2009 8
30-Apr-2010 9
06-Aug-2010 10 Updated Features, Section 4: Typical operating characteristics; Ta b l e 9 .
06-Sep-2011 11
Reformatted; update characteristics (Figure 2, 3, 8 to 10, 27 to 29;
Ta b le 6 to 9).
Updated Ta bl e 1 , Table 3, Ta b l e 4 , Ta bl e 6 , Ta b l e 9 , Section 2.3,
Section 2.7, text in Section 7; reformatted document.
Updated Ta bl e 4 , corrected typo in Tab le 2 , Section 2.3, Section 3,
Section 5
Updated Section 2.7, Section 5 and Disclaimer, minor typo
modifications throughout the document.
and Section 6, Figure 17, Ta bl e 7 and Ta b l e 8 .
Doc ID 10518 Rev 11 31/32
STM706T/S/R, STM706P, STM708T/S/R
y
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32/32 Doc ID 10518 Rev 11
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