ST STM690, STM704, STM795, STM802, STM804 User Manual

STM690, STM704, STM795 STM802, STM804, STM805, STM806

3 V supervisor with battery switchover

Features

■RST or RST outputs

■NVRAM supervisor for external LPSRAM

■Chip enable gating (STM795 only) for external LPSRAM (7 ns max prop delay)

■Manual (push-button) reset input

■200 ms (typ) trec

■Watchdog timer - 1.6 s (typ)

■Automatic battery switchover

■Low battery supply current - 0.4 µA (typ)

■Power-fail comparator (PFI/PFO)

■Low supply current - 40 µA (typ)

■Guaranteed RST (RST) assertion down to VCC = 1.0 V

■Operating temperature:

–40 °C to 85 °C (industrial grade)

■RoHS compliance

–Lead-free components are compliant with the RoHS directive

8

1

SO8 (M)

TSSOP8 3x3 (DS)(1)

1. Contact local ST sales office for availability.

Table 1.		Device summary
			Watchdog	Activelow			Activehigh	Manual	Battery	Power-fail	Chip enable
								reset
			Input		RST(1)		RST(1)		switchover	comparator	gating
								input
STM690T/S/R
STM704T/S/R
STM795T/S/R					(2)
STM802T/S/R
STM804T/S/R							(2)
STM805T/S/R							(2)
STM806T/S/R

1.All RST outputs push-pull (unless otherwise noted).

2.Open drain output.

August 2010

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Contents	STM690, STM704, STM795, STM802, STM804, STM805, STM806

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	1.1	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9

1.1.1 MR (manual reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.2 WDI (watchdog input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.3 RST (active-low reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.4 RST (active-high reset - open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.5 PFI (power-fail input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.6 PFO (power-fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.7 VOUT (supply output voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.8 Vccsw (VCC switch output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1.9 E (chip enable input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.10 ECON (conditional chip enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.11 VBAT (backup battery input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2	Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	2.1	Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	2.2	Push-button reset input (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	2.3	Watchdog input (NOT available on STM704/795/806) . . . . . . . . . . . . . . .	14
	2.4	Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.5	Chip enable gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	2.6	Chip enable input (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	2.7	Chip enable output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	2.8	Power-fail input/output (NOT available on STM795) . . . . . . . . . . . . . . . .	17
	2.9	Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	2.10	Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . .	19
	2.11	Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
3	Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
4	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
5	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31

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STM690, STM704, STM795, STM802, STM804, STM805, STM806		Contents
6	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 36
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 39
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 41

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List of tables	STM690, STM704, STM795, STM802, STM804, STM805, STM806

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8. SO8 - 8-lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 38 Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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STM690, STM704, STM795, STM802, STM804, STM805, STM806	List of figures

List of figures

Figure 1.	Logic diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 2.	Logic diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 3.	Logic diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
Figure 4.	STM690/802/804/805 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
Figure 5.	STM704/806 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
Figure 6.	STM795 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
Figure 7.	Block diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 8.	Block diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 9.	Block diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 10.	Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 11.	Chip enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 12.	Chip enable waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 13.	Power-fail comparator waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . . .	18
Figure 14.	Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 15.	VCC to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 16.	VBAT to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 17.	Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 18.	Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 19.	VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 20.	Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 21.	Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 22.	Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 23.	Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 24.	E to ECON on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 25.	PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 26.	Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . .	25
Figure 27.	Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . .	26
Figure 28.	RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 29.	RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 30.	Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 31.	Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 32.	Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 33.	E to ECON propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 34.	E to ECON propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 35.	AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 36.	MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 37.	Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 38.	SO8 – 8-lead plastic small outline, 150 mils body width,
	package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
Figure 39.	TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . .	38

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Description	STM690, STM704, STM795, STM802, STM804, STM805, STM806

1 Description

The STM690/704/795/802/804/805/806 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and writeprotect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset

output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795) to provide the system with an early warning of impending power failure.

These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.

Figure 1. Logic diagram (STM690/802/804/805)

		VCC VBAT
			VOUT
	WDI	STM690/
			RST (RST) (1)
		802/804/
	PFI	805	PFO
		VSS

AI08846

1. For STM804/805, reset output is active-high and open drain.

Figure 2. Logic diagram (STM704/806)

		VCC VBAT
	MR		VOUT
		STM704
			RST
		STM806
	PFI
			PFO
		VSS	AI08847

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Description

Figure 3.

Logic diagram (STM795)

VCC VBAT

VCCSW

VOUT

STM795

RST

E

ECON

VSS

AI08848

Table 2.

Signal names

MR

Push-button reset input

WDI

Watchdog input

Active-low reset output

RST

RST(1)

Active-high reset output

(2)

Chip enable input

E

(2)

Conditioned chip enable output

ECON

(2)

VCC switch output

Vccsw

VOUT

Supply voltage output

VCC

Supply voltage

VBAT

Backup supply voltage

PFI

Power-fail input

Power-fail output

PFO

VSS

Ground

1. Open drain for STM804/805 only.

2.

STM795.

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Description	STM690, STM704, STM795, STM802, STM804, STM805, STM806

Figure 4. STM690/802/804/805 connections

SO8/TSSOP8

VOUT	1	8			VBAT
VCC	2	7				RST	(RST)(1)
VSS	3	6			WDI
PFI	4	5			PFO

AI08849

1. For STM804/805, reset output is active-high and open drain.

Figure 5. STM704/806 connections

SO8/TSSOP8

VOUT	1	8		VBAT
VCC	2	7			RST
VSS	3	6			MR
PFI	4	5			PFO

AI08850

Figure 6. STM795 connections

SO8/TSSOP8

	VOUT	1	8		VBAT
	VCC	2	7		RST
	VCCSW	3	6	ECON
	VSS	4	5			E

AI08851

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1.1Pin descriptions

1.1.1MR (manual reset)

A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low

and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if

unused.

1.1.2WDI (watchdog input)

If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge.

The watchdog function cannot be disabled by allowing the WDI pin to float.

1.1.3RST (active-low reset)

Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold

or when MR is a logic low. It remains low for trec after either VCC rises above the reset

threshold, the watchdog triggers a reset, or MR goes from low to high.

1.1.4RST (active-high reset - open drain)

Pulses high for trec when triggered, and stays high whenever VCC is above the reset

threshold or when MR is a logic high. It remains high for trec after either VCC falls below the

reset threshold, the watchdog triggers a reset, or MR goes from high to low.

1.1.5PFI (power-fail input)

When PFI is less than VPFI or when VCC falls below VSW (2.4 V), PFO goes low; otherwise,

PFO remains high. Connect to ground if unused.

1.1.6PFO (power-fail output)

When PFI is less than VPFI, or VCC falls below VSW, PFO goes low; otherwise, PFO remains high. Leave open if unused. Output type is push-pull.

1.1.7VOUT (supply output voltage)

When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through

a P-channel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT. Connect to VCC if no battery is used.

1.1.8Vccsw (VCC switch output)

When VOUT switches to battery, Vccsw is high. When VOUT switches back to VCC, Vccsw is low. It can be used to drive gate of external PMOS transistor for IOUT requirements exceeding 75 mA. Output type is push-pull.

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Description	STM690, STM704, STM795, STM802, STM804, STM805, STM806

1.1.9E (chip enable input)

The input to the chip enable gating circuit. Connect to ground if unused.

1.1.10ECON (conditional chip enable)

ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is

asserted, ECON will remain low for 15 µs or until E goes high, whichever occurs first. In the

disabled mode, ECON is pulled up to VOUT.

1.1.11VBAT (backup battery input)

When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.

Table 3.	Pin description
		Pin
						Name											Function
STM795	STM690		STM704	STM804
	STM802		STM806	STM805
—	—		6	—													Push-button reset input
									MR
—	6		—	6				WDI									Watchdog input
7	7		7	—													Active-low reset output
								RST
—	—		—	7				RST									Active-high reset output
—	4		4	4					PFI								Power-fail input
—	5		5	5													Power-fail output (push-pull)
								PFO
1	1		1	1			VOUT										Supply output for external LPSRAM
2	2		2	2				VCC									Supply voltage
3	—		—	—													VCC switch output (push-pull)
						Vccsw
4	3		3	3				VSS									Ground
5	—		—	—													Chip enable input
											E
6	—		—	—						CON							Conditioned chip enable output
							E
8	8		8	8			VBAT										Backup battery input

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STM690, STM704, STM795, STM802, STM804, STM805, STM806	Description

Figure 7. Block diagram (STM690/802/804/805)

VCC			VOUT
VBAT
VSO	COMPARE
VRST	COMPARE
WDI	WATCHDOG	trec	RST (RST)(1)
	TIMER	generator
PFI	COMPARE
VPFI			PFO
			AI07897

1. For STM804/805, reset output is active-high and open drain.

Figure 8. Block diagram (STM704/806)

VCC			VOUT
VBAT
VSO	COMPARE
VRST	COMPARE
MR		trec	RST
		generator
PFI	COMPARE
VPFI			PFO
			AI07898

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Description	STM690, STM704, STM795, STM802, STM804, STM805, STM806

Figure 9. Block diagram (STM795)

VCC			VOUT
VBAT
VSO	COMPARE		VCCSW
VRST	COMPARE	t rec	RST
		generator
	ECON OUTPUT
	CONTROL
E			ECON
PFI	COMPARE
VPFI			PFO
			AI08852

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STM690, STM704, STM795, STM802, STM804, STM805, STM806	Description

Figure 10. Hardware hookup

	Unregulated	Regulator		VCCSW (2)
		VIN	VCC	VCC		VOUT			VCC
	voltage
									VCC
				STM690/704/					LPSRAM
				795/802/804/
			0.1 F
				805/806					E
									E
				WDI(1)				0.1	F
		From microprocessor
				E(2)	E	CON	(2)
	R1
				PFI(3)		PFO(3)		To microprocessor NMI
	R2
			Push-button	MR(4)		RST		To microprocessor reset
				VBAT
									AI08853
1.	For STM690/802/804/805.

2.For STM795 only.

3.Not available on STM795.

4.For STM704/806.

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