STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9
5 V supervisor with battery switchover
Features
■5 V operating voltage
■NVRAM supervisor for external LPSRAM
■Chip-enable gating (STM818 only) for external LPSRAM (7 ns max prop delay)
■RST and RST outputs
■200 ms (typ) trec
■Watchdog timer - 1.6 sec (typ)
■Automatic battery switchover
■Low battery supply current - 0.4 µA (typ)
■Power-fail comparator (PFI/PFO)
■Low supply current - 40 µA (typ)
■Guaranteed RST (RST) assertion down to VCC = 1.0 V
■Operating temperature:
–40 °C to +85 °C (industrial grade)
■RoHS compliance
–Lead-free components are compliant with the RoHS directive
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SO8 (M)
TSSOP8 3 x 3 (DS)(1)
1. Contact local ST sales office for availability.
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Watchdog |
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Battery |
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input(1) |
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STM805L |
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STM819L/M |
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1. All |
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RST |
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August 2010 |
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Doc ID 10522 Rev 10 |
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1/43 |
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www.st.com
Contents |
STM690A/692A/703/704/802/805/817/818/819 |
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Contents
1 |
Description . . |
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1.1 |
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1.1 |
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WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1.3 |
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RST |
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1.1.4 |
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RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1.5 |
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VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1.6 |
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VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1.7 |
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1.1.8 |
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CON |
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1.1.9 |
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PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1.10 |
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PFO |
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Push-button reset input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . |
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Watchdog input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . |
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Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Chip-enable gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Chip-enable input (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Chip-enable output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Power-fail input/output (NOT available on STM818) . . . . . . . . . . . . . . . . |
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Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.10 |
Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . |
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Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Battery freshness seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . |
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Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
2/43 |
Doc ID 10522 Rev 10 |
STM690A/692A/703/704/802/805/817/818/819 |
Contents |
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 42 |
Doc ID 10522 Rev 10 |
3/43 |
List of tables |
STM690A/692A/703/704/802/805/817/818/819 |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 8. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data. . . . . . 38 Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 39 Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4/43 |
Doc ID 10522 Rev 10 |
STM690A/692A/703/704/802/805/817/818/819 |
List of figures |
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List of figures
Figure 1. Logic diagram (STM690A/692/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Logic diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. STM690A/692A/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. STM703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. STM818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Block diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Block diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Block diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. Chip-enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. Power-fail comparator waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. Power-fail comparator waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . . . . 17 Figure 15. Using a SuperCap™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. VCC to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18. VBAT to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 19. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 22. Reset comparator propagation delay vs. temperature (other than STM817/818/819) . . . . 22
Figure 23. Reset comparator propagation delay vs. temperature (VBAT = 3.0 V; STM817/818/819) . 23
Figure 24. Power-up tREC vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 25. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 26. Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. E to ECON on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 28. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29. Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26 Figure 30. Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26 Figure 31. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 33. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 34. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 35. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 36. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 37. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 38. E to ECON propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 39. E to ECON propagation delay test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 40. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 41. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 42. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 43. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing . . . 38 Figure 44. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . . 39
Doc ID 10522 Rev 10 |
5/43 |
Description |
STM690A/692A/703/704/802/805/817/818/819 |
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The STM690A/692A/703/704/802/805/817/818/819 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset
output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM703/704/819) as well as a power-fail comparator (except for STM818) to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.
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AI07894
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STM690A/692A/703/704/802/805/817/818/819 |
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Description |
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Figure 3. |
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Logic diagram (STM818) |
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Table 2. |
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(1) |
Conditioned chip-enable output |
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ECON |
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VOUT |
Supply voltage output |
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VCC |
Supply voltage |
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VBAT |
Backup supply voltage |
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PFI |
Power-fail input |
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Power-fail output |
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PFO |
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VSS |
Ground |
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1. |
STM818 |
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SO8/TSSOP8
VOUT |
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8 |
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VBAT |
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VCC |
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RST(RST)(1) |
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VSS |
3 |
6 |
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WDI |
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PFI |
4 |
5 |
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PFO |
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AI07889
1. For STM805, reset output is active-high.
Doc ID 10522 Rev 10 |
7/43 |
Description |
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STM690A/692A/703/704/802/805/817/818/819 |
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Figure 5. |
STM703/704/819 connections |
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SO8/TSSOP8 |
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VOUT |
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VBAT |
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VCC |
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2 |
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RST |
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VSS |
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3 |
6 |
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MR |
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PFI |
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PFO |
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AI07890 |
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Figure 6. |
STM818 connections |
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SO8/TSSOP8 |
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VOUT |
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VBAT |
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7 |
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RST |
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6 |
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E |
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4 |
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ECON |
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AI07892 |
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1.1.1MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.2WDI
If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
1.1.3RST
Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold
or when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.4RST
Pulses high for trec when triggered, and stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
8/43 |
Doc ID 10522 Rev 10 |
STM690A/692A/703/704/802/805/817/818/819 |
Description |
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1.1.5VOUT
When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through a P- channel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT.
1.1.6VBAT
When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.
1.1.7E
The input to the chip-enable gating circuit. Connect to ground if unused.
1.1.8ECON
ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is
asserted, ECON will remain low for 15 µs or until E goes high, whichever occurs first. In the
disabled mode, ECON is pulled up to VOUT.
1.1.9PFI
When PFI is less than VPFI or when VCC falls below 2.4 V (or VSO), PFO goes low;
otherwise, PFO remains high. Connect to ground if unused.
1.1.10PFO
When PFI is less than VPFI, or VCC falls below 2.4 V (or VSO), PFO goes low; otherwise,
PFO remains high. Leave open if unused. Output type is push-pull.
Doc ID 10522 Rev 10 |
9/43 |
Description |
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STM690A/692A/703/704/802/805/817/818/819 |
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Table 3. |
Pin description |
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STM690A |
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STM703 |
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Name |
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Function |
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STM692A |
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STM818 |
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STM704 |
STM805 |
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STM802 |
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STM819 |
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STM817 |
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- |
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6 |
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Push-button reset input |
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MR |
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6 |
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6 |
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WDI |
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Watchdog input |
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7 |
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7 |
- |
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Active-low reset output |
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RST |
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- |
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7 |
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RST |
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Active-high reset output |
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1 |
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1 |
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1 |
1 |
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VOUT |
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Supply output for external LPSRAM |
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2 |
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2 |
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2 |
2 |
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VCC |
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Supply voltage |
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8 |
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8 |
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8 |
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VBAT |
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Backup battery input |
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4 |
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Chip-enable input |
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E |
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CON |
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Conditioned chip-enable output |
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4 |
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PFI |
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Power-fail input |
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5 |
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Power-fail output (push-pull) |
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Ground |
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Figure 7. |
Block diagram (STM690A/692A/802/805/817) |
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VOUT |
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VSO |
COMPARE |
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VRST |
COMPARE |
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WATCHDOG |
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trec |
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(1) |
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WDI |
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RST(RST) |
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TIMER |
Generator |
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PFI |
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COMPARE |
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PFO |
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AI07897
1. For STM805, reset output is active-high.
10/43 |
Doc ID 10522 Rev 10 |
STM690A/692A/703/704/802/805/817/818/819 |
|
Description |
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Figure 8. Block diagram (STM703/704/819) |
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VOUT |
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VSO |
COMPARE |
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COMPARE |
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MR |
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COMPARE |
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PFO |
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AI07898
VCC VOUT
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VBAT |
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VSO |
COMPARE |
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VRST |
COMPARE |
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WATCHDOG |
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trec |
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WDI |
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RST |
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TIMER |
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Generator |
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ECON OUTPUT
CONTROL
E ECON
AI07899a
Doc ID 10522 Rev 10 |
11/43 |
Description |
STM690A/692A/703/704/802/805/817/818/819 |
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Unregulated |
Regulator |
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VIN |
VCC |
VCC |
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VOUT |
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VCC |
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Voltage |
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VCC |
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STM690A/692A/ |
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LPSRAM |
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703/704/802/805/ |
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0.1 F |
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817/818/819 |
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E |
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E |
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0.1 |
F |
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WDI(1) |
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From Microprocessor |
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E(2) |
E |
(2) |
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R1 |
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CON |
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PFI(3) |
PFO(3) |
To Microprocessor NMI |
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R2 |
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(5) |
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MR(4) |
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To Microprocessor Reset |
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Push-Button |
RST |
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VBAT |
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AI07893 |
1.For STM690A/692A/802/805/817/818.
2.For STM818 only.
3.Not available on STM818.
4.For STM703/704/819.
5.Active high on STM805.
12/43 |
Doc ID 10522 Rev 10 |
STM690A/692A/703/704/802/805/817/818/819 |
Operation |
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The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or
when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM805) for 0V < VCC < VRST if VBAT is greater than 1 V. Without a backup
battery, RST is guaranteed valid down to VCC =1 V.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, trec. After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
2.2Push-button reset input (STM703/704/819)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 41) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used.
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD(1.6 sec typ), the reset is asserted. The internal watchdog timer is cleared by either:
1.a reset pulse, or
2.by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (tWD + trec).
The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure 42).
Note: 1 The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and the maximum allowable load capacitance is 200 pF.
2 Input pulses less than 20 ns will be ignored.
Doc ID 10522 Rev 10 |
13/43 |