ST STM7007 User Manual

Single-chip hardware accelerated encryption engine for

computer and peripherals applications

Features

■ World class encryption engine

– HardCache™ Crypto module
– FIPS 140-2 security level 3
– NIST Certificate #1599

■ Symmetric algorithms (NIST FIPS approved)

– AES Rijndael block cipher: Key length

128/192/256 bits, ECB/CBC/CBC-FVE
modes, NIST Certificate #1068

– Triple DES: Key length 112/168 bits,

ECB/CBC modes, NIST Certificate #798

– SHA-256, SHA-384 and SHA-512 with

associated HMAC: NIST SHS Certificate
#1015, NIST HMAC Certificate #606

■ Asymmetric Algorithms

– ECDSA, 256- and 384-bit elliptic curves
– RSA PKCS#1 v2.1 padding scheme
– 2048 bit operands

■ Algorithm control policy

– Easy algorithm configuration
– Export control

■ PCI Express

■ Advanced 65 nm process technology

■ Windows XP, Windows 2000, Windows Vista,

Windows 7

ECOPACK® ROHS compliant

■

®

x1 interface

(a)

STM7007

Data brief

■ Best in class performance / power ratio

■ Secure key management protected inside a

tamper resistant cryptographic boundary

■ Resists attacks that use software and/or

instrumentation monitors

■ Enables secure remote administration

■ Shielded locations and protected operations

Applications

■ Desktop PC clients

■ Laptop and mobile PC

■ Server and workstation

■ Entire volume encryption

■ Data loss protection

■ Cryptographic service provider

■ Secure messaging

System benefits

Description

■ Off-loads intensive cryptographic calculations

(asymmetric and symmetric) from the system
CPU

■ Out performs SW based solutions and 3 GHz

processors

■ Full duplex DMA operation

a. Windows is a trademark of Microsoft Corporation.

October 2011 Doc ID 022239 Rev 1 1/27

For further information contact your local STMicroelectronics sales office.

The STM7007 is a PCI Express encryption
engine built on the STMicroelectronics’
HardCache™ cryptographic channel controller
(a

high performance core computing block, with
FIPS 140-2 security level 3 certification).
The

STM7007 provides hardware acceleration for
commonly used algorithms, including AES, 3DES,
SHA, HMAC, RSA, and ECC.

www.st.com

1

Contents STM7007

Contents

1 Device pinout and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Device pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Device package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.1 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2.2 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2.3 Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2.4 Recommended land pad layout and solder reflow profile . . . . . . . . . . . 11

1.2.5 Rework guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Environment maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.1 PCI, miscellaneous 3.3V interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.2 PHY 1.2V and 2.5V interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 AC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 Differential interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . 17

2.7.1 PCIe test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 PCB layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 PCB Routing of RX/TX differential signals . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1 Example: PCB impedance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 PCB power and ground decoupling guidelines . . . . . . . . . . . . . . . . . . . . 22

3.3 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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STM7007 Device pinout and package

1

1 Device pinout and package

Device pinout, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Device pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Signal types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

STM7007 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Device package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 1. Device pinout, top view

PETn

PETp

VDD1V2

rsvd

rsvd

rsvd

PERST#

rsvd

10

11

12

13

14

15

16

VDDR1V2

PERn

7

PERp

6

GND

5

rsvd

8

9

STM7007

32-Pin

LGA 5x5

18

17

VDD3V3

rsvd

19

rsvd

20

rsvd

VDDT1V2

4

21

VDD2V5

VDDPLL1V2

3

22

rsvd

REFCLKn

2

23

rsvd

REFCLKp

24

CLKREQ#

32

31

30

29

28

27

26

25

REFRES

GND_PLL

VDDPLL2V5

VDD1V2

rsvd

rsvd

rsvd

PGOOD

Doc ID 022239 Rev 1 3/27

Device pinout and package STM7007

1.1 Device pins

● Ta b le 1 lists the abbreviations used for the signal type names in Tabl e 3 .

Note that abbreviations may be combined, as with APWR (Analog power supply).

● Ta b le 2 lists device signals and how they are grouped, color coding each group.

● Ta b le 3 lists device pins, and uses the same color coding as Tab le 2 to indicate pin

grouping.

Table 1. Signal types

Abbreviation Description

AAnalog

DI Digital input

DO Digital output

GND Ground

I Input

LVDSI Low voltage differential input

LVDSO Low voltage differential output

NC No connection

O Output

PWR Power supply

Table 2. Signal groups

Signal Group Count (32-pin LGA 5x5 package)

VDD1V2, VDD2V5, VDD3V3,
VDD1V2, VDDPLL1V2, VDDPLL2V5,

Power (VDD) 8

VDDR1V2, VDDT1V2

VSS_PLL, VSS Ground (VSS) 2 (GND pad slug on bottom of device)

PETp, PETn, PERp, PERn, REFCLKp,
REFCLKn, CLKREQ#, PERST#

PCI Express 8

REFRES, PGOOD MISC 3

RSVD Not connected 3

Table 3. STM7007 pins

Pin

number

1 REFCLKp

Pin

name

Signal

(1)

type

External

component

Description

LV DS I — Low voltage differential clock input

2 REFCLKn

3 VDDPLL1V2 APWR

4 VDDT1V2 APWR

Decoupling

capacitor

Decoupling

capacitor

1.2 volt analog power input for the internal
PLL block

1.2 volt analog power input for PCIe transmit
channel

4/27 Doc ID 022239 Rev 1

STM7007 Device pinout and package

Table 3. STM7007 pins (continued)

Pin

number

Pin

name

Signal

(1)

type

External

component

Description

5 PERn

6 PERp

7 VDDR1V2 APWR

8 RSVD NC Reserved pins, do not connect

9 PETn

10 PETp

11 VDD1V2 PWR

12 RSVD NC — Reserved

13 RSVD NC — Reserved

14 RSVD NC — Reserved

15 PERST# DI —

16 RSVD NC — Reserved

17 VDD3V3 PWR

18 RSVD NC — Reserved

19 RSVD NC — Reserved

20 RSVD NC — Reserved

21 VDD2V5 PWR

22

RSVD NC — Reserved pins, do not connect

23

24 CLKREQ# DO —

25 PGOOD DI — Power on reset, used to reset the core.

26 RSVD NC — Reserved

27 RSVD NC — Reserved

28 RSVD NC — Reserved

29 VDD1V2 PWR

30 VDDPLL2V5 PWR —

31 GND_PLL GND — DC return pin for PLL block

LV DS I — Low voltage differential receive pair

Decoupling

capacitor

LV DS O — Low voltage differential transmit pair

Decoupling

capacitor

Decoupling

capacitor

Decoupling

capacitor

Decoupling

capacitor

1.2 volt analog power input for PCIe receive
channel

1.2 volt power supply input for core

Asynchronous device reset input from
system. When asserted, STM7007 resets all
volatile content and executes a reboot after
de-assertion of signal.

3.3 volt power supply input for I/O logic

2.5 volt power supply

Informs the host controller that the reference
clock input is required by the STM7007. It is
an open drain active low output; when 0, the
reference clock is required, otherwise the
reference clock can be off.

1.2 volt power supply input for core

Doc ID 022239 Rev 1 5/27

Device pinout and package STM7007

Table 3. STM7007 pins (continued)

Pin

number

32 REFRES AI Resistor

— GND GND - DC return pad

1. For acronym definitions, see Table 1: Signal types on page 4.

Pin

name

Signal

(1)

type

External

component

Description

Reference resistor input for PLL block. This
pin is tied to 1.2V PLL using a 475_1% ohm
resistor

6/27 Doc ID 022239 Rev 1

STM7007 Device pinout and package

1.2 Device package

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

This device uses a 32-Lead, 5 x 5 x 0.82 mm land grid array (LGA) package.

Note: 1 This package is not yet defined in JEDEC publications.

2 The exact shape of each corner is optional.

Doc ID 022239 Rev 1 7/27

Device pinout and package STM7007

1.2.1 Dimensions

Table 4. Package dimensions (mm)

Reference Minimum Typical Maximum

A 0.74 0.82 0.88

A1 0.00 0.035

A3 0.22

b 0.18 0.25 0.30

D 4.90 5.00 5.10

D1 3.50

D2 2.65 2.70 2.75

E 4.90 5.00 5.10

E1 3.50

E2 2.65 2.70 2.75

e0.50

L0.35 0.45

L1 0.075

ddd 0.100

8/27 Doc ID 022239 Rev 1

STM7007 Device pinout and package

GND VIA (8)

PCB_Metal: 250 x 325 µm 
(1 to 1 ratio to package pad)

PCB_Solder Mask Opening: 300 x 375 µm

GND Pad

PCB Metal: 3600 x 3600 µm

ePad Soldering Area (5)

PCB_Solder Mask Opening: 700 µm dia.

Stencil thickness: 4 mils

Land aperture: 250 x 325 µm (1 to 1 ratio)

ePad soldering aperture: 750 u dia. (slight increase)

Thicker stencil option

Stencil thickness: 5 mils

Land aperture: 275 x 357 µm (10% increase)

ePad soldering aperture: 800 µm dia.

For a thicker stencil, slightly increase the aperture size
for robust solder paste release 
(increase area ratio:

area of pad / area of aperture wall).

1.2.2 Recommended footprint

Figure 2. PCB layout recommendation

Figure 3. Stencil layout recommendation

Doc ID 022239 Rev 1 9/27