Features
STM690, STM704, STM795
STM802, STM804, STM805, STM806
3 V supervisor with battery switchover
■ RST or RST outputs
■ NVRAM supervisor for external LPSRAM
■ Chip enable gating (STM795 only) for external
LPSRAM (7 ns max prop delay)
■ Manual (push-button) reset input
■ 200 ms (typ) t
■
Watchdog timer - 1.6 s (typ)
■ Automatic battery switchover
■ Low battery supply current - 0.4 µA (typ)
■ Power-fail comparator (PFI/PFO)
■ Low supply current - 40 µA (typ)
■ Guaranteed RST (RST) assertion
down to V
■ Operating temperature:
rec
= 1.0 V
CC
–40 °C to 85 °C (industrial grade)
■ RoHS compliance
– Lead-free components are compliant with
the RoHS directive
Table 1. Device summary
8
1
SO8 (M)
TSSOP8 3x3 (DS)
1. Contact local ST sales office for availability.
(1)
Manual
reset
input
Battery
switchover
Power-fail
comparator
Chip enable
gating
Watchdog
Input
Active- low
(1)
RST
Active- high
RST
(1)
STM690T/S/R ✓✓ ✓✓
STM704T/S/R ✓✓✓✓
STM795T/S/R ✓
(2)
✓✓
STM802T/S/R ✓✓ ✓✓
STM804T/S/R ✓✓
STM805T/S/R ✓✓
(2)
(2)
✓✓
✓✓
STM806T/S/R ✓✓✓✓
1. All RST outputs push-pull (unless otherwise noted).
2. Open drain output.
August 2010 Doc ID 10519 Rev 9 1/42
www.st.com
1
Contents STM690, STM704, STM795, STM802, STM804, STM805, STM806
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.1 MR (manual reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.2 WDI (watchdog input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.3 RST
1.1.4 RST (active-high reset - open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.5 PFI (power-fail input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.6 PFO
1.1.7 V
1.1.8 Vccsw
1.1.9 E
1.1.10 E
1.1.11 V
(active-low reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(power-fail output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(supply output voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OUT
(VCC switch output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(chip enable input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
(conditional chip enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CON
(backup battery input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BAT
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Push-button reset input (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Watchdog input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . 14
2.4 Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Chip enable gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Chip enable input (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Chip enable output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 Power-fail input/output (NOT available on STM795) . . . . . . . . . . . . . . . . 17
2.9 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10 Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . 19
2.11 Negative-going V
transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Contents
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 10519 Rev 9 3/42
List of tables STM690, STM704, STM795, STM802, STM804, STM805, STM806
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 38
Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 List of figures
List of figures
Figure 1. Logic diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Logic diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. STM690/802/804/805 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. STM704/806 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. STM795 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Block diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Block diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Chip enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Chip enable waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . . . 18
Figure 14. Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. V
Figure 16. V
Figure 17. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. V
Figure 20. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. Power-up t
Figure 22. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 24. E
Figure 25. PFI to PFO
Figure 26. Output voltage vs. load current (V
Figure 27. Output voltage vs. load current (V
Figure 28. RST
Figure 29. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 30. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 32. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. E
Figure 34. E
Figure 35. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 36. MR
Figure 37. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width,
Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 38
to V
CC
to V
BAT
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PFI
to E
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUT
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
rec
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CON
propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
= 5 V; V
CC
= 0 V; V
CC
= 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 25
BAT
= 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26
BAT
output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
to E
to E
propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CON
propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CON
timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 10519 Rev 9 5/42
Description STM690, STM704, STM795, STM802, STM804, STM805, STM806
1 Description
The STM690/704/795/802/804/805/806 supervisors are self-contained devices which
provide microprocessor supervisory functions with the ability to non-volatize and write-
protect external LPSRAM. A precision voltage reference and comparator monitors the V
input for an out-of-tolerance condition. When an invalid V
output (RST
) is forced low (or high in the case of RST). These devices also offer a watchdog
condition occurs, the reset
CC
timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795)
to provide the system with an early warning of impending power failure.
These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1. Logic diagram (STM690/802/804/805)
VCCV
BAT
V
WDI
PFI
STM690/
802/804/
805
OUT
RST (RST)
PFO
(1)
CC
V
SS
1. For STM804/805, reset output is active-high and open drain.
Figure 2. Logic diagram (STM704/806)
VCCV
BAT
MR
PFI
STM704
STM806
V
SS
V
OUT
RST
PFO
AI08846
AI08847
6/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description
Figure 3. Logic diagram (STM795)
VCCV
BAT
V
OUT
RST
E
CON
AI08848
Table 2. Signal names
MR Push-button reset input
WDI Watchdog input
RST Active-low reset output
(1)
RST
(2)
Chip enable input
E
(2)
E
CON
(2)
Vccsw
V
OUT
V
CC
V
BAT
Active-high reset output
Conditioned chip enable output
VCC switch output
Supply voltage output
Supply voltage
Backup supply voltage
PFI Power-fail input
V
CCSW
E
STM795
V
SS
PFO Power-fail output
Ground
V
SS
1. Open drain for STM804/805 only.
2. STM795.
Doc ID 10519 Rev 9 7/42
Description STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 4. STM690/802/804/805 connections
SO8/TSSOP8
V
OUT
V
V
CC
SS
PFI
1
2
3
4
1. For STM804/805, reset output is active-high and open drain.
8
7
6
5
V
BAT
RST (RST)
WDI
PFO
(1)
AI08849
Figure 5. STM704/806 connections
SO8/TSSOP8
V
OUT
V
V
PFI
CC
SS
1
2
3
4
V
BAT
8
RST
7
MR
6
PFO
5
AI08850
Figure 6. STM795 connections
V
V
CCSW
SO8/TSSOP8
OUT
V
CC
V
SS
1
2
3
4
RST
7
E
6
CON
E
5
AI08851
V
BAT
8
8/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description
1.1 Pin descriptions
1.1.1 MR (manual reset)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for t
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.2 WDI (watchdog input)
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset is
triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge.
The watchdog function cannot be disabled by allowing the WDI pin to float.
1.1.3 RST (active-low reset)
after MR returns high. This active-low input has an internal pull-up. It can be
rec
Pulses low for t
or when MR
when triggered, and stays low whenever VCC is below the reset threshold
rec
is a logic low. It remains low for t
threshold, the watchdog triggers a reset, or MR
1.1.4 RST (active-high reset - open drain)
Pulses high for t
threshold or when MR
reset threshold, the watchdog triggers a reset, or MR
when triggered, and stays high whenever VCC is above the reset
rec
is a logic high. It remains high for t
1.1.5 PFI (power-fail input)
When PFI is less than V
PFO
remains high. Connect to ground if unused.
or when VCC falls below VSW (2.4 V), PFO goes low; otherwise,
PFI
1.1.6 PFO (power-fail output)
1.1.7 V
When PFI is less than V
high. Leave open if unused. Output type is push-pull.
(supply output voltage)
OUT
When VCC is above the switchover voltage (VSO), V
a P-channel MOSFET switch. When V
to V
if no battery is used.
CC
, or VCC falls below VSW, PFO goes low; otherwise, PFO remains
PFI
falls below VSO, V
CC
after either VCC rises above the reset
rec
goes from low to high.
after either VCC falls below the
rec
goes from high to low.
is connected to VCC through
OUT
connects to V
BAT
OUT
. Connect
1.1.8 Vccsw (VCC switch output)
When V
low. It can be used to drive gate of external PMOS transistor for I
exceeding 75 mA. Output type is push-pull.
switches to battery, Vccsw is high. When V
OUT
Doc ID 10519 Rev 9 9/42
switches back to VCC, Vccsw is
OUT
requirements
OUT
Description STM690, STM704, STM795, STM802, STM804, STM805, STM806
1.1.9 E (chip enable input)
The input to the chip enable gating circuit. Connect to ground if unused.
1.1.10 E
1.1.11 V
(conditional chip enable)
CON
E
goes low only when E is low and reset is not asserted. If E
CON
asserted, E
disabled mode, E
(backup battery input)
BAT
When VCC falls below VSO, V
hysteresis, V
will remain low for 15 µs or until E goes high, whichever occurs first. In the
CON
OUT
is pulled up to V
CON
switches from VCC to V
OUT
reconnects to VCC. V
.
OUT
may exceed VCC. Connect to VCC if no battery is
BAT
is low when reset is
CON
. When VCC rises above VSO +
BAT
used.
Table 3. Pin description
STM795
— — 6 — MR Push-button reset input
— 6 — 6 WDI Watchdog input
7 7 7 — RST
— — — 7 RST Active-high reset output
— 4 4 4 PFI Power-fail input
— 5 5 5 PFO
1 1 1 1 V
2 2 2 2 V
3 — — — Vccsw
4 3 3 3 V
5 — — — E
6 — — — E
8 8 8 8 V
STM690
STM802
Pin
STM704
STM806
STM804
STM805
Name Function
Active-low reset output
Power-fail output (push-pull)
OUT
Supply voltage
CC
SS
CON
BAT
Supply output for external LPSRAM
VCC switch output (push-pull)
Ground
Chip enable input
Conditioned chip enable output
Backup battery input
10/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description
Figure 7. Block diagram (STM690/802/804/805)
V
CC
V
BAT
COMPARE
COMPARE
WATCHDOG
TIMER
COMPARE
WDI
PFI
V
V
V
SO
RST
PFI
1. For STM804/805, reset output is active-high and open drain.
Figure 8. Block diagram (STM704/806)
V
CC
t
rec
generator
V
OUT
RST (RST)
PFO
V
OUT
(1)
AI07897
MR
PFI
V
BAT
V
V
V
SO
RST
PFI
COMPARE
COMPARE
COMPARE
t
rec
generator
RST
PFO
AI07898
Doc ID 10519 Rev 9 11/42
Description STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 9. Block diagram (STM795)
V
CC
PFI
V
OUT
V
BAT
V
CCSW
RST
E
CON
PFO
AI08852
V
PFI
COMPARE
COMPARE
COMPARE
E
CON
CONTROL
OUTPUT
t
rec
generator
V
SO
V
RST
E
12/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Description
Figure 10. Hardware hookup
(2)
Unregulated
voltage
R1
R2
Regulator
V
V
CC
IN
0.1 F
From microprocessor
Push-button
V
CCSW
V
CC
STM690/704/
795/802/804/
805/806
(1)
WDI
(2)
E
PFI
MR
(3)
(4)
E
CON
PFO
V
RST
OUT
(2)
(3)
V
CC
V
CC
LPSRAM
E
0.1 F
To microprocessor NMI
To microprocessor reset
E
1. For STM690/802/804/805.
2. For STM795 only.
3. Not available on STM795.
4. For STM704/806.
V
BAT
AI08853
Doc ID 10519 Rev 9 13/42
Operation STM690, STM704, STM795, STM802, STM804, STM805, STM806
2 Operation
2.1 Reset output
The STM690/704/795/802/804/805/806 supervisor asserts a reset signal to the MCU
whenever V
the push-button reset input (MR
high for STM804/805) for 0 V < V
battery, RST
goes below the reset threshold (V
CC
RST
) is taken low. RST is guaranteed to be a logic low (logic
CC
< V
RST
if V
BAT
is guaranteed valid down to VCC = 1 V.
), a watchdog time-out occurs, or when
is greater than 1 V. Without a backup
During power-up, once V
the reset time-out period, t
If V
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset time-out period (t
the internal timer clears. The reset timer starts when V
exceeds the reset threshold an internal timer keeps RST low for
CC
. After this interval RST returns high.
rec
). Any time VCC goes below the reset threshold
rec
returns above the reset threshold.
CC
2.2 Push-button reset input (STM704/806)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
Figure 36) after it returns high. The MR
input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain/ collector outputs. Connect a normally open momentary switch from MR
to create a manual reset function; external debounce circuitry is not required. If MR
from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor
from MR
to GND to provide additional noise immunity. MR may float, or be tied to VCC when
not used.
2.3 Watchdog input (NOT available on STM704/795/806)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within t
watchdog timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
If WDI is tied high or low, a reset pulse is triggered every 1.8 s (t
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting (see Figure 37).
(1.6 s typ), the reset is asserted. The internal
WD
+ t
WD
rec
).
(see
rec
to GND
is driven
Note: Input frequency greater than 20 ns (50 MHz) will be filtered.
14/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Operation
2.4 Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through V
automatically switch the SRAM to the backup supply when V
Note: When the battery is first connected without V
immediately provide battery backup voltage on V
switchover operate as described below. This mode allows a battery to be attached during
manufacturing but not used until after the system has been activated for the first time. As a
result, no battery power is consumed by the device during storage and shipment. If the
backup battery is not used, connect both V
This family of supervisors does not always connect V
V
. V
CC
V
BAT
connects to V
BAT
(whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V lithium cell)
to have a higher voltage than V
Assuming that V
before V
gets too close to the 2.0 V minimum required to reliably retain data in most
OUT
external SRAMs. When V
point. V
is connected to VCC through a 3 Ω PMOS power switch.
OUT
Note: The backup battery may be removed while V
decoupled (0.1 µF typ), without danger of triggering a reset.
Table 4. I/O status in battery backup
. With a backup battery installed with voltage V
OUT
power applied, the device does not
CC
BAT
(through a 100 Ω switch) when VCC is below VSW (2.4 V) or
OUT
.
CC
> 2.0 V, switchover at VSO ensures that battery backup mode is entered
BAT
recovers, hysteresis is used to avoid oscillation around the VSO
CC
CC
. Only after VCC exceeds V
OUT
and V
OUT
BAT
to VCC.
to V
is valid, assuming V
CC
OUT
falls.
, the devices
BAT
when V
BAT
will the
RST
is greater than
BAT
is adequately
Pin Status
V
Connected to V
OUT
Disconnected from V
V
CC
PFI Disabled
PFO Logic low
E
E
CON
WDI Watchdog timer is disabled
MR
RST
RST Logic high
V
BAT
Vccsw
High impedance
Logic high
Disabled
Logic low
Connected to V
Logic high (STM795)
through internal switch
BAT
OUT
OUT
Doc ID 10519 Rev 9 15/42
Operation STM690, STM704, STM795, STM802, STM804, STM805, STM806
2.5 Chip enable gating (STM795 only)
Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the
external CMOS RAM in the event of an undervoltage condition. The STM795 uses a series
transmission gate from E
asserted), the E
transmission gate is enabled and passes all E transitions. When reset is
to E
(see Figure 11). During normal operation (reset not
CON
asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS
RAM. The short E
most µPs. If E
propagation delay from E to E
is low when reset asserts, E
enables the STM795 to be used with
CON
remains low for typically 10 µs to permit the
CON
current write cycle to complete.
2.6 Chip enable input (STM795 only)
The chip enable transmission gate is disabled and E is high impedance (disabled mode)
while reset is asserted. During a power-down sequence when V
threshold, the chip enable transmission gate disables and E
impedance if the voltage at E
is high. If E is low when reset asserts, the chip enable
transmission gate will disable 10 µs after reset asserts (see Figure 12). This permits the
current write cycle to complete during power-down.
passes the reset
CC
immediately becomes high
Any time a reset is generated, the chip enable transmission gate remains disabled and E
remains high impedance (regardless of E
period (t
/2). When the chip enable transmission gate is enabled, the impedance of E
rec
activity) for the first half of the reset time-out
appears as a 40 Ω resistor in series with the load at E
the chip enable transmission gate depends on V
connected to E
tested from the 50% point on E
, and the loading on E
to the 50% point on E
. The chip enable propagation delay is production
CON
CC
load capacitance (see Figure 35). For minimum propagation delay, minimize the capacitive
load at E
and use a low-output impedance driver.
CON
2.7 Chip enable output (STM795 only)
When the chip enable transmission gate is enabled, the impedance of E
a 40 Ω resistor in series with the source driving E
gate is off and an active pull-up connects E
off when the transmission gate is enabled.
Figure 11. Chip enable gating
V
CC
V
RST
COMPARE
. In the disabled mode, the transmission
to V
CON
. The propagation delay through
CON
, the source impedance of the drive
using a 50 Ω driver and a 50 pF
CON
is equivalent to
CON
(see Figure 11). This pull-up turns
OUT
t
rec
generator
RST
V
OUT
E
OUTPUT
CON
CONTROL
E
16/42 Doc ID 10519 Rev 9
E
CON
AI08802
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Operation
Figure 12. Chip enable waveform (STM795)
V
E
RST
E
CC
CON
V
RST
V
BAT
½ tr
ec
t
rec
½ t
10 µs
rec
t
rec
2.8 Power-fail input/output (NOT available on STM795)
The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from
the V
Output (PFO
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 10) to either the unregulated DC input (if it is available) or the regulated output
of the V
below V
804/805/806 or the microprocessor drops below the minimum operating voltage.
comparator). If PFI is less than the power-fail threshold (V
RST
), the Power-Fail
PFI
) will go low. This function is intended for use as an undervoltage detector to
regulator. The voltage divider can be set up such that the voltage at PFI falls
CC
several milliseconds before the regulated VCC input to the STM690/704/795/802/
PFI
AI08855c
During battery backup, the power-fail comparator is turned off and PFO
low (see Figure 13). This occurs after V
drops below VSW (2.4 V). When power returns,
CC
the power-fail comparator is enabled and PFO
should be connected to V
and PFO left unconnected. PFO may be connected to MR on
SS
the STM704/806 so that a low voltage on PFI will generate a reset output.
2.9 Applications information
These supervisor circuits are not short-circuit protected. Shorting V
excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both V
the device as possible.
CC
and V
pins to ground by placing 0.1 µF capacitors as close to
BAT
goes (or remains)
follows PFI. If the comparator is unused, PFI
to ground -
OUT
Doc ID 10519 Rev 9 17/42
Operation STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 13. Power-fail comparator waveform (STM690/704/802/804/805/806)
V
CC
V
RST
VSW (2.4 V )
t
PFO
rec
RST
PFO follows PFI
PFO follows PFI
AI08861a
18/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Operation
2.10 Using a SuperCap™ as a backup power source
SuperCaps™ are capacitors with extremely high capacitance values (e.g., order of 0.47 F)
for their size. Figure 14 shows how to use a SuperCap as a backup power source. The
SuperCap may be connected through a diode to the V
V
while VCC is above the reset threshold, there are no special precautions when using
CC
these supervisors with a Super-Cap.
Figure 14. Using a SuperCap™
5 V
supply. Since V
CC
can exceed
BAT
V
CC
STMXXX
V
BAT
GND
2.11 Negative-going VCC transients
The STM690/704/795/802/804/805/806 supervisors are relatively immune to negative-going
V
transients (glitches). Figure 32 was generated using a negative pulse applied to VCC,
CC
starting at V
(comparator overdrive). The graph indicates the maximum pulse width a negative V
transient can have without causing a reset pulse. As the magnitude of the transient
increases (further below the threshold), the maximum allowable pulse width decreases. Any
combination of duration and overdrive which lies under the curve will NOT generate a reset
signal. Typically, a V
or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible
to the V
CC
+ 0.3 V and ending below the reset threshold by the magnitude indicated
RST
transient that goes 100 mV below the reset threshold and lasts 40 µs
CC
pin provides additional transient immunity.
V
RST
OUT
To external SRAM
To µP
CC
AI08805
Doc ID 10519 Rev 9 19/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
3 Typical operating characteristics
Note: Typical values are at TA = 25 °C.
Figure 15. V
)
on-resistance (
OUT
to V
CC
V
to V
CC
5.0
4.0
3.0
2.0
1.0
0.0
–40 –20
on-resistance vs. temperature
OUT
0 20 40 60 80 100 120
Temperature (°C)
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI10498
Figure 16. V
)
on-resistance (
OUT
to V
BAT
V
to V
BAT
160
140
120
100
80
60
40
20
0
–40 –20 0 20 40 60 80 100 120
on-resistance vs. temperature
OUT
Temperature (°C)
V
V
V
V
BAT
BAT
BAT
BAT
= 2.0 V
= 3.0 V
= 3.3 V
= 3.6 V
AI09140b
20/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 17. Supply current vs. temperature (no load)
30
25
20
A)
µ
15
VCC = 2.7 V
10
Supply current (
5
0
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
VCC = 3.0 V
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
AI09141b
Figure 18. Battery current vs. temperature
1000
100
10
Battery supply current (nA)
1
0.1
–40 –20 0 20 40 60 80 100 120
V
= 2.0 V
BAT
V
= 3.0 V
BAT
V
= 3.6 V
BAT
Temper ature ( °C)
AI10499
Doc ID 10519 Rev 9 21/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 19. V
1.270
1.265
1.260
1.255
1.250
threshold (V)
1.245
PFI
V
1.240
1.235
1.230
1.225
threshold vs. temperature
PFI
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09142b
Figure 20. Reset comparator propagation delay vs. temperature
30
28
26
24
22
20
18
Propagation delay (µ s)
16
14
12
10
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09143b
22/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 21. Power-up t
240
235
230
225
(ms)
rec
t
220
215
210
–40 –20 0 20 40 60 80 100 120
vs. temperature
rec
Temperature (°C)
Figure 22. Normalized reset threshold vs. temperature
1.004
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI09144b
1.002
1.000
0.998
Normalized reset threshold
0.996
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09145b
Doc ID 10519 Rev 9 23/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 23. Watchdog time-out period vs. temperature
1.90
1.85
1.80
1.75
1.70
Watchdog time-out period (s)
1.65
1.60
–40 –20 0 20 40 60 80 100 120
Figure 24. E to E
60
50
)
40
30
on-resistance (
Temperature (°C)
on-resistance vs. temperature
CON
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI09146b
CON
20
E to E
10
0
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
24/42 Doc ID 10519 Rev 9
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI09147b
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 25. PFI to PFO propagation delay vs. temperature
4.0
VCC = 3.0 V
(µs)
3.0
2.0
1.0
PFI to PFO propagation delay
0.0
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
VCC = 3.6 V
VCC = 4.5 V
VCC = 5.5 V
AI09148b
Figure 26. Output voltage vs. load current (VCC = 5 V; V
5.00
4.98
(V)
OUT
V
4.96
4.94
0 1020304050
I
(mA)
OUT
= 2.8 V; TA = 25 °C)
BAT
AI10496
Doc ID 10519 Rev 9 25/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 27. Output voltage vs. load current (VCC = 0 V; V
2.80
2.78
2.76
2.74
(V)
OUT
2.72
V
2.70
2.68
2.66
0.0 0.2 0.4 0.6 0.8 1.0
I
(mA)
OUT
Figure 28. RST output voltage vs. supply voltage
= 2.8 V; TA = 25 °C)
BAT
AI10497
(V)
RST
V
5
V
RST
V
4
CC
3
5
4
3
(V)
CC
2
1
0
500 ms / div
2
1
0
AI09149b
V
26/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 29. RST output voltage vs. supply voltage
5
4
3
(V)
2
RST
V
1
0
500 ms / div
Figure 30. Power-fail comparator response time (assertion)
5V
V
V
RST
CC
5
4
3
2
1
0
AI09150b
(V)
CC
V
PFO
1.3 V
PFI
500 ns / div
1V/div
0V
500 mV / div
0V
AI09153b
Doc ID 10519 Rev 9 27/42
Typical operating characteristics STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 31. Power-fail comparator response time (de-assertion)
5V
PFO
0V
PFI
0V
500 ns / div
Figure 32. Maximum transient duration vs. reset threshold overdrive
6000
5000
1V/div
1.3 V
500 mV / div
AI09154b
4000
Reset occurs
duration (µs)
3000
Transient
2000
1000
0
above the cur ve
Reset comparator ov erdrive, V
RST
28/42 Doc ID 10519 Rev 9
– VCC (V)
0111.010.0100.0
AI09156b
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Typical operating characteristics
Figure 33. E to E
4.0
3.0
2.0
propagation delay (ns)
CON
1.0
E to E
0.0
–40 –20 0 20 40 60 80 100 120
propagation delay vs. temperature
CON
Temperature (°C)
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
AI09157b
Doc ID 10519 Rev 9 29/42
Maximum ratings STM690, STM704, STM795, STM802, STM804, STM805, STM806
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
T
STG
(1)
T
SLD
V
Input or output voltage –0.3 to VCC +0.3 V
IO
V
CC/VBAT
I
Output current 20 mA
O
P
D
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Storage temperature (VCC off) –55 to 150 °C
Lead solder temperature for 10 seconds 260 °C
Supply voltage –0.3 to 6.0 V
Power dissipation 320 mW
30/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 DC and AC parameters
5 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived tests performed under the measurement conditions summarized in
Ta bl e 6 . Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 6. Operating and AC measurement conditions
Parameter
V
CC/VBAT
Ambient operating temperature (T
supply voltage 1.0 to 5.5 V
) –40 to 85 °C
A
Input rise and fall times ≤
STM690/704/795/
802/804/805/806
5
5ns
Input pulse voltages 0.2 to 0.8 V
Input and output timing ref. voltages 0.3 to 0.7 V
Figure 34. E to E
propagation delay test circuit
CON
V
BAT
3.6 V
25
equivalent
source impedance
STM690/704/
795/802/804/
V
CC
V
CC
805/806
GND
E
CON
50
50
E
cable
50
Unit
V
CC
V
CC
50 pF C
(1)
L
1. CL includes load capacitance and scope probe capacitance.
Figure 35. AC testing input/output waveforms
0.8 V
CC
0.2 V
CC
Doc ID 10519 Rev 9 31/42
0.7 V
0.3 V
AI08854
CC
CC
AI02568
DC and AC parameters STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 36. MR timing waveform
MR
t
MLRL
(1)
RST
t
MLMH
1. RST for STM805.
Figure 37. Watchdog timing
V
CC
t
RST
WDI
Alter-
native
Operating voltage T
V
CC
Table 7. DC and AC characteristics
Sym
,
V
CC
(2)
V
BAT
ICC
V
CC
backup mode
I
BAT
(4)
V
BAT
backup mode
rec
Description Test condition
supply current
supply current in battery
supply current in battery
t
rec
= –40 to +85 °C 1.1
A
Excluding I
Excluding I
Excluding I
= 2.0 V, MR = VCC)
V
CC
Excluding I
OUT
t
WD
(1)
(VCC < 5.5 V) 40 60 µA
OUT
(VCC < 3.6 V) 35 50 µA
OUT
(V
OUT
= 2.3 V,
BAT
(V
= 3.6 V) 0.4 1.0 µA
BAT
Min Typ Max Unit
(3)
5.5 V
25 35 µA
AI07837a
AI07891
= 5 mA
I
OUT1
V
V
OUT1
V
V
OUT2
voltage (active)
OUT
voltage (battery backup)
OUT
to V
V
CC
on-resistance 3 4 Ω
OUT
I
I
= 75 mA
OUT1
= 250 µA, VCC > 2.5 V
OUT1
I
= 250 µA, V
OUT2
I
= 1 mA, V
OUT2
32/42 Doc ID 10519 Rev 9
(5)
BAT
= 2.3 V
BAT
= 2.3 V
(5)
V
0.03
V
V
0.0015
V
BAT
CC
CC
0.3
CC
0.1
–
–
–
–
VCC –
0.015
VCC –
0.15
VCC –
0.0006
V
–
BAT
0.034
V
–
BAT
0.14
V
V
V
V
V
STM690, STM704, STM795, STM802, STM804, STM805, STM806 DC and AC parameters
Table 7. DC and AC characteristics (continued)
Sym
I
LI
I
LO
V
IH
V
IL
V
OL
V
OL
V
OH
V
OHB
Alter-
native
Description Test condition
to V
V
BAT
Input leakage current (MR)
on-resistance 100 Ω
OUT
STM704/806 only;
MR = 0 V, VCC = 3 V
Input leakage current (PFI) 0 V < V
Input leakage current (WDI) 0 V < V
Output leakage current
Input high voltage (MR, WDI) V
Input low voltage (MR, WDI) V
Output low voltage (PFO,
, RST, Vccsw)
RST
Output low voltage (E
CON
)
STM804/805/795;
0 V < V
(max) < VCC < 5.5 V 0.7 VCC V
RST
(max) < VCC < 5.5 V 0.3 V
RST
V
= V
CC
= 3.2 mA
I
SINK
VCC = V
= 1.6 mA, E = 0 V
I
OUT
IOL = 40 µA,
= 1.0 V, V
V
CC
Output low voltage (RST)
Output high voltage (RST,
(7)
RST)
Output high voltage (E
Output high voltage (PFO
CON
)
VOH battery backup (Vccsw,
RST)
battery backup (E
V
OH
CON
)
)
TA = 0 °C to 85 °C
= 200 µA,
I
OL
= 1.2 V, V
V
CC
I
SOURCE
= V
V
CC
= V
V
CC
I
= 1.6 mA, E = VCC
OUT
I
SOURCE
V
= V
CC
I
SOURCE
V
= 0 V, V
CC
I
SOURCE
VCC = 0 V, V
< V
IN
CC
< V
IN
CC
< V
IN
CC
(max),
RST
(max),
RST
= VCC,
BAT
= V
BAT
= 1 mA,
(max)
RST
(max),
RST
= 75 µA,
(max)
RST
= 100 µA,
= 2.8 V
BAT
= 75 µA,
= 2.8 V
BAT
(1)
(6)
CC
Min Typ Max Unit
20 75 350 µA
–20 2 +25 nA
–1 +1 µA
–1 +1 µA
V
CC
0.3 V
0.2 V
CC
V
0.3 V
0.3 V
2.4 V
0.8 V
0.8 V
0.8 V
0.8 V
V
CC
V
CC
V
BAT
V
BAT
Power-fail comparator (NOT available on STM795)
STM802/
V
PFI
PFI input threshold
PFI falling
(V
< 3.6 V)
CC
804/806
STM690/
704/805
PFI hysteresis PFI rising (V
PFI to PFO propagation delay 2 µs
t
PFD
< 3.6 V) 10 20 mV
CC
1.212 1.237 1.262 V
1.187 1.237 1.287 V
Doc ID 10519 Rev 9 33/42
DC and AC parameters STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 7. DC and AC characteristics (continued)
Sym
ISC
Alter-
native
Description Test condition
PFO
output short to GND
current
= 3.6 V, PFO = 0 V 0.1 0.75 2.0 mA
V
CC
(1)
Min Typ Max Unit
Battery switchover
> VSW V
V
VSO
Battery backup switchover
(8)(9)
voltage
V
SW
Power-down
Power-up
V
V
V
BAT
BAT
BAT
BAT
< V
> V
< V
SW
SW
SW
SW
V
V
BAT
V
SW
V
V
BAT
2.4 V
Hysteresis 40 mV
Reset thresholds
falling 3.00 3.075 3.15 V
V
STM690T/
704T/795T/ 805T
STM802T/
804T/806T
STM690S/
704S/795S/ 805S
(10)
V
Reset threshold
RST
STM802S/
804S/806S
STM690R/
704R/795R/ 805R
STM802R/
804R/806R
RST pulse width VCC < 3.6 V 140 200 280 ms
t
rec
CC
rising 3.00 3.085 3.17 V
V
CC
V
falling 3.00 3.075 3.12 V
CC
rising 3.00 3.085 3.14 V
V
CC
V
falling 2.85 2.925 3.00 V
CC
rising 2.85 2.935 3.02 V
V
CC
falling 2.88 2.925 3.00 V
V
CC
rising 2.88 2.935 3.02 V
V
CC
V
falling 2.55 2.625 2.70 V
CC
rising 2.55 2.635 2.72 V
V
CC
V
falling 2.59 2.625 2.70 V
CC
rising 2.59 2.635 2.72 V
V
CC
V
V
Push-button reset input (STM704/806)
t
MLMH tMR
t
MLRL tMRD
MR pulse width 100 20 ns
MR to RST output delay 60 500 ns
Watchdog timer (NOT available on STM704/795/806)
t
WD
Watchdog timeout period V
WDI pulse width V
(max) < VCC < 3.6 V 1.12 1.60 2.24 s
RST
(max) < VCC < 3.6 V 100 20 ns
RST
Chip enable gating (STM795 only)
E to E
resistance VCC = V
CON
RST
34/42 Doc ID 10519 Rev 9
(max) 46 Ω
STM690, STM704, STM795, STM802, STM804, STM805, STM806 DC and AC parameters
Table 7. DC and AC characteristics (continued)
Sym
E
ISC E
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = V
2. V
3. V
4. Tested at V
Alter-
native
to E
Reset to E
CON
noted).
supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality,
CC
state of RST
(min). Either VCC or V
(min) = 1.0 V for TA = 0 °C to +85 °C.
CC
and RST tested at V
= 3.6 V, VCC = 3.5 V and 0 V.
BAT
Description Test condition
propagation delay VCC = V
CON
high delay 10 µs
CON
= 3.6 V, disable mode,
V
short circuit current
= 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC
BAT
can go to 0 V if the other is greater than 2.0 V.
BAT
CC
E
RST
CON
RST
(1)
Min Typ Max Unit
(max) 2 7 ns
= 0 V
(max) to 5.5 V; and V
0.1 0.75 2.0 mA
BAT
5. Guaranteed by design.
6. The leakage current measured on the RST pin (STM804/805) or RST
asserted (output high impedance).
pin (STM795) is tested with the reset output not
7. Not valid for STM795/804/805 (open drain).
8. When V
9. When V
> VCC > VSW, V
BAT
> VCC > V
SW
BAT
10. The reset threshold tolerance is wider for V
internal oscillation.
remains connected to VCC until VCC drops below VSW.
OUT
, V
remains connected to VCC until VCC drops below the battery voltage (V
OUT
rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
CC
= 2.8 V (except where
) - 75 mV.
BAT
Doc ID 10519 Rev 9 35/42
Package mechanical data STM690, STM704, STM795, STM802, STM804, STM805, STM806
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
36/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Package mechanical data
Figure 38. SO8 – 8-lead plastic small outline, 150 mils body width,
package mechanical drawing
A2
A
C
B
e
ddd
D
8
E
H
1
Table 8. SO8 - 8-lead plastic small outline, 150 mils body width,
LA1
package mechanical data
mm inches
Symb
Typ Min Max Typ Min Max
A — 1.35 1.75 — 0.053 0.069
A1 — 0.10 0.25 — 0.004 0.010
B — 0.33 0.51 — 0.013 0.020
C — 0.19 0.25 — 0.007 0.010
SO-A
D — 4.80 5.00 — 0.189 0.197
ddd — — 0.10 — — 0.004
E — 3.80 4.00 — 0.150 0.157
e 1.27 — — 0.050 — —
H — 5.80 6.20 — 0.228 0.244
h — 0.25 0.50 — 0.010 0.020
L — 0.40 0.90 — 0.016 0.035
α — 0° 8° — 0° 8°
N 8 8
Doc ID 10519 Rev 9 37/42
Package mechanical data STM690, STM704, STM795, STM802, STM804, STM805, STM806
Figure 39. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline
D
8
1
CP
Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
5
EE1
4
A1
A2A
eb
L
L1
TSSOP8BM
mechanical data
mm inches
Symb
Typ Min Max Typ Min Max
A — — 1.10 — — 0.043
A1 — 0.05 0.15 — 0.002 0.006
c
A2 0.85 0.75 0.95 0.034 0.030 0.037
b — 0.25 0.40 — 0.010 0.016
c — 0.13 0.23 — 0.005 0.009
CP — — 0.10 — — 0.004
D 3.00 2.90 3.10 0.118 0.114 0.122
e 0.65 — — 0.026 — —
E 4.90 4.65 5.15 0.193 0.183 0.203
E1 3.00 2.90 3.10 0.118 0.114 0.122
L 0.55 0.40 0.70 0.022 0.016 0.030
L1 0.95 — — 0.037 — —
α — 0° 6° — 0° 6°
N 8 8
38/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Part numbering
7 Part numbering
Table 10. Ordering information scheme
Example: STM690 T M 6 E
Device type
STM690/704/795/802/804/805/806
Reset threshold voltage
T = STM690/704/795/805 = V
STM802/804/806 = V
RST
S = STM690/704/795/805 = V
STM802/804/806 = V
RST
R = STM690/704/795/805 = V
STM802/804/806 = V
RST
Package
M = SO8
(1)
DS
= TSSOP8
Temperature range
6 = –40 to 85 °C
Shipping method
E = ECOPACK
F = ECOPACK
®
package, tubes
®
package, tape and reel
= 3.00 V to 3.15 V
RST
= 3.00 V to 3.12 V
= 2.85 V to 3.00 V
RST
= 2.88 V to 3.00 V
= 2.55 V to 2.70 V
RST
= 2.59 V to 2.70 V
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 10519 Rev 9 39/42
Part numbering STM690, STM704, STM795, STM802, STM804, STM805, STM806
Table 11. Marking description
Part number Reset threshold Package Topside marking
STM690T 3.075
STM690S 2.925
STM690R 2.625
STM704T 3.075
STM704S 2.925
STM704R 2.625
STM795T 3.075
STM795S 2.925
STM795R 2.625
STM802T 3.075
STM802S 2.925
STM802R 2.625
STM804T 3.075
STM804S 2.925
STM804R 2.625
STM805T 3.075
STM805S 2.925
STM805R 2.625
STM806T 3.075
STM806S 2.925
STM806R 2.625
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
SO8
TSSOP8
690T
690S
690R
704T
704S
704R
795T
795S
795R
802T
802S
802R
804T
804S
804R
805T
805S
805R
806T
806S
806R
40/42 Doc ID 10519 Rev 9
STM690, STM704, STM795, STM802, STM804, STM805, STM806 Revision history
8 Revision history
Table 12. Document revision history
Date Revision Changes
31-Oct-2003 1 Initial release.
22-Dec-2003 2
16-Jan-2004 2.1
Reformatted; update characteristics (Figure 1, 3, 4, 11, 13, 14, 37;
Ta bl e 1 , 3, 4, 7, 9, 11).
Added Typical operating characteristics (Figure 17, 18, 20 to 26, 29,
30 to 34).
07-Apr-2004 2.2 Updated characteristics (Figure 13, 29, 30, Ta b l e 1 , 3, 7)
25-May-2004 3 Update characteristics (Ta b l e 3 , 7)
02-Jul-2004 4
29-Sep-2004 5
25-Feb-2005 6 Update characteristics (
Update package availability, pin description; promote document
(Figure 1, 14; Ta bl e 3 , 10)
Clarify root part numbers, pin descriptions, update characteristics
(Figure 2, to, 11, 13, 14, 35; Tabl e 1 , 3, 6, 7, 10)
Figure 11, 16, to 35; Ta bl e 7 )
05-Apr-2006 7 Update characteristics (Figure 13)
20-Nov-2009 8
Updated Section 1.1.6, Section 1.1.8, Figure 10, 11, 19, Ta bl e 3 , 5, 7;
added text to Section 6.
18-Aug-2010 9 Updated Features, Section 2.4: Backup battery switchover.
Doc ID 10519 Rev 9 41/42
STM690, STM704, STM795, STM802, STM804, STM805, STM806
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42/42 Doc ID 10519 Rev 9
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