ST STM6600, STM6601 User Manual

STM6600, STM6601

Smart push-button on/off controller with Smart Reset™ and power-on lockout

Features

■Operating voltage 1.6 V to 5.5 V

■Low standby current of 0.6 µA

■Adjustable Smart Reset™ assertion delay time driven by external CSRD

■Power-up duration determined primarily by push-button press (STM6600) or by fixed time period, tON_BLANK (STM6601)

■Debounced PB and SR inputs

■PB and SR ESD inputs withstand voltage up to ±15 kV (air discharge) ±8 kV (contact discharge)

■Active high or active low enable output option (EN or EN) provides control of MOSFET, DC-DC converter, regulator, etc.

■Secure startup, interrupt, Smart Reset™ or power-down driven by push-button

■Precise 1.5 V voltage reference with 1% accuracy

Datasheet −production data

TDFN12

Applications

■Portable devices

■Terminals

■Audio and video players

■ Industrial operating temperature –40 to +85 °C

■

Cell phones and smart phones

■ Available in TDFN12 2 x 3 mm package

■

PDAs, palmtops, organizers

Table 1.

Device summary

Device

CSRD

/

EN or

Startup process

RST

PB

SR

EN

INT

must be held low until the

STM6600

open drain(1)

push-pull

open drain(1)

PB

PS

(2)

confirmation

HOLD

STM6601

open drain(1)

push-pull

open drain(1)

PB can be released before the

PS

(2)

confirmation

HOLD

1.External pull-up resistor needs to be connected to open drain outputs.

2.For a successful startup, the PSHOLD (Power Supply Hold) needs to be pulled high within specific time, tON_BLANK.

June 2012

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This is information on a product in full production.

www.st.com

Contents	STM6600, STM6601

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 5
2	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
3	Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
4	Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
5	Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
6	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
7	DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
8	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
9	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
10	Product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51

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STM6600, STM6601	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6. TDFN12 (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 7. Carrier tape dimensions for TDFN12 (2 x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. STM6600 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 9. STM6601 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 10. STM6600 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 11. STM6601 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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List of figures	STM6600, STM6601

List of figures

Figure 1.	Application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 5
Figure 2.	Basic functionality (option with enable deassertion after long push) . . . . . . . . . . . . . . . . .	. 6
Figure 3.	Basic functionality (option with RST assertion after long push) . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 4.	Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 5.	TDFN12 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 6.	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Figure 7.	Successful power-up on STM6600 (PB released prior to tON_BLANK expiration) . . . . . . . .	14
Figure 8.	Successful power-up on STM6600 (tON_BLANK expires prior to PB release) . . . . . . . . . . .	15
Figure 9.	Unsuccessful power-up on STM6600 (PB released prior to tON_BLANK) . . . . . . . . . . . . . .	16
Figure 10.	Unsuccessful power-up on STM6600 (tON_BLANK expires prior to PB release) . . . . . . . . .	17
Figure 11.	Successful power-up on STM6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 12.	Unsuccessful power-up on STM6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 19
Figure 13.	Power-up on STM660x with voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 14.	PB interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 15.	Long push, PB pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 16.	Long push, SR pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 17.	Invalid long push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 18.	Long push (option with RST assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 19.	Long push (option with enable deassertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 20.	Undervoltage detected for <tSRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 21.	Undervoltage detected for >tSRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
Figure 22.	PBOUT output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 23.	Supply current vs. temperature, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 24.	Supply current vs. temperature, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
Figure 25.	Supply current vs. supply voltage, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 26.	Supply current vs. supply voltage, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 27.	Threshold vs. temperature, VTH+ = 3.4 V (typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
Figure 28.	Threshold hysteresis vs. temperature, VHYST = 200 mV (typ.) . . . . . . . . . . . . . . . . . . . . . .	30
Figure 29.	Debounce period vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 30.	CSRD charging current vs. temperature, VCC = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 31.	Output low voltage vs. output low current, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 32.	Output high voltage vs. output high current, TA = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 33.	Output voltage vs. supply voltage, IOUT = 1 mA, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 34.	Input voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 35.	Reference output voltage vs. temperature, VCC = 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 36.	Reference output voltage vs. load current, VCC = 2.0 V, TA = 25 °C . . . . . . . . . . . . . . . . .	34
Figure 37.	Reference output voltage vs. supply voltage, TA = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 38.	Reference startup, IREF = 15 µF, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 39.	Reference response to steps on supply voltage, IREF = 15 µA, TA = 25 °C . . . . . . . . . . . .	36
Figure 40.	Reference response to steps in load current, VCC = 3.6 V, TA = 25 °C . . . . . . . . . . . . . . .	37
Figure 41.	TDFN12 (2 x 3 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Figure 42.	TDFN12 (2 x 3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 43.	Carrier tape for TDFN12 (2 x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45

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STM6600, STM6601	Description

1 Description

The STM6600-01 devices monitor the state of connected push-button(s) as well as sufficient supply voltage. An enable output controls power for the application through the MOSFET transistor, DC-DC converter, regulator, etc. If the supply voltage is above a precise voltage threshold, the enable output can be asserted by a simple press of the button. Factoryselectable supply voltage thresholds are determined by highly accurate and temperaturecompensated references. An interrupt is asserted by pressing the push-button during normal operation and can be used to request a system power-down. The interrupt is also asserted if undervoltage is detected. By a long push of one button (PB) or two buttons (PB and SR) either a reset is asserted or power for the application is disabled depending on the option used.

The device also offers additional features such as precise 1.5 V voltage reference with very tight accuracy of 1%, separate output indicating undervoltage detection and separate output for distinguishing between interrupt by push-button or undervoltage.

The device consumes very low current of 6 µA during normal operation and only 0.6 µA current during standby.

The STM6600-01 is available in the TDFN12 package and is offered in several options among features such as selectable threshold, hysteresis, timeouts, output types, etc.

Figure 1. Application hookup

		$# $# CONVERTER
		POWER -/3&%4
		REGULATOR ETC
2
	6##					6$$
,%$		%. %.	2	2	2
	6##,/		234			234
						) /
	0"	03(/,$
		34-	).4			.-)-OR ).4
		34-				) /
		0"/54
	32		62%&			-#5
		#32$				#05
	'.$					"!3%"!.$
			#2%&
		#32$
						!-V

1.A resistor is required for open drain output type only. A 10 kΩ pull-up is sufficient in most applications.

2.Capacitor CREF is mandatory on VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended.

3.For the STM6601 the processor has to confirm the proper power-on during the fixed time period, tON_BLANK. This failsafe feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive microprocessor.

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Description									STM6600, STM6601
	Figure 2. Basic functionality (option with enable deassertion after long push)
					POWER-UP(1)		INTERRUPT		POWER-DOWN
							(short push)		(long push)
		PB

SR

EN
INT	interrupt	interrupt

AM00243v1

1. For power-up the battery voltage has to be above VTH+ threshold.

Figure 3. Basic functionality (option with RST assertion after long push)

POWER-UP(1)	INTERRUPT	POWER-DOWN
	(short push)	(long push)
PB
SR
RST
INT	interrupt	interrupt
		AM00243bv1

1. For power-up the battery voltage has to be above VTH+ threshold.

Figure 4.

Logic diagram

VCC

EN

(EN)

PB

RST

SR

STM6600

INT

PS

STM6601

PBOUT

HOLD

CSRD

VCCLO

VREF

GND

AM00236v1

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STM6600, STM6601

Description

Table 2.

Pin descriptions

Pin number

Symbol

Function

1

VCC

Power supply input

2

Smart Reset™ button input

SR

3

VREF

Precise 1.5 V voltage reference

4

PSHOLD

PSHOLD input

5

CSRD

Adjustable Smart Reset™ delay time input

6

Push-button input

PB

7

LO

Output for high threshold comparator output (VTH+)

VCC

8

OUT

Status of

push-button input

PB

PB

9

EN or

Enable output

EN

10

Reset output

RST

11

Interrupt output

INT

12

GND

Ground

Figure 5. TDFN12 pin connections

VCC	1	12	GND
SR	2	11	INT
VREF	3	10	RST
PSHOLD	4	9	EN (EN)
CSRD	5	8	PBOUT
PB	6	7	VCCLO

AM00245v1

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Description	STM6600, STM6601

Figure 6. Block diagram

		VCCLO	VCC	EN (EN)
		+	+		RST
VCC	VCC	–	–		tREC
				generator
(1)	(2)	VTH+	VTH–		PSHOLD
RPB	RSR
				Smart
PB		Glitch immunity		logic	(3)
					RPSHOLD
		Edge detector debounce
SR					INT
		Glitch immunity
		Edge detector debounce			VREF
GND				SRD logic	1.5 V
			PBOUT	CSRD
					AM00237v3

1.Internal pull-up resistor connected to PB input (see Table 5 for precise specifications).

2.Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications and Table 10 for detailed device options).

3.Internal pull-down resistor is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18).

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STM6600, STM6601	Pin descriptions

2 Pin descriptions

VCC - power supply input

VCC is monitored during startup and normal operation for sufficient voltage level. Decouple the VCC pin from ground by placing a 0.1 µF capacitor as close to the device as possible.

SR - Smart Reset™ button input

This input is equipped with voltage detector with a factory-trimmed threshold and has ±8 kV HBM ESD protection.

Both PB and SR buttons have to be pressed and held for tSRD period so the long push is recognized and the reset is asserted (or the enable output is deasserted depending on the

option) - see Figure 15, 16, and 17.

Active low SR input is usually connected to GND through the momentary push-button (see Figure 1) and it has an optional 100 kΩ pull-up resistor. It is also possible to drive this input using an external device with either open drain (recommended) or push-pull output. Open drain output can be connected in parallel with push-button or other open drain outputs, which is not possible with push-pull output. SR input is monitored for falling edge after power-up and must not be grounded permanently.

VREF - external precise 1.5 V voltage reference

This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has proper output voltage as soon as the reset output is deasserted (i.e. after tREC expires) and it is disabled when the device enters standby mode. A mandatory capacitor needs to be connected to VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended.

PSHOLD input

This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to confirm correct power-up of the device (if EN or EN is not asserted) or to initiate a shutdown (if EN or EN is asserted).

Forcing PSHOLD high during power-up confirms the proper start of the application and keeps enable output asserted. Because most processors have outputs in high-Z state before initialization, an internal pull-down resistor is connected to PSHOLD input during startup (see

Figure 7, 8, 9, 10, 11, 12, 13, and 18).

Forcing the PSHOLD signal low during normal operation deasserts the enable output (see Figure 14). Input voltage on this pin is compared to an accurate voltage reference.

CSRD - Smart Reset™ delay time input

A capacitor to ground determines the additional time (tSRD) that PB with SR must be pressed and held before a long push is recognized. The connected CSRD capacitor is charged with ISRD current. Additional Smart Reset™ delay time tSRD ends when voltage on the CSRD capacitor reaches the VSRD voltage threshold. It is recommended to use a low ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the CSRD pin open. If no capacitor is connected, there is no tSRD and a long push is recognized right after tINT_Min expires (see Figure 18 and 19).

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Pin descriptions

STM6600, STM6601

- power ON switch

PB

This input is equipped with a voltage detector with a factory-trimmed threshold and has

± 8 kV HBM ESD protection.

When the

button is pressed and held, the battery voltage is detected and EN (or

is

PB

EN)

asserted if the battery voltage is above the threshold VTH+ during the whole tDEBOUNCE

period (see Figure 13).

A short push of the push-button during normal operation can initiate an interrupt through

debounced

INT

output (see Figure 14) and a long push of

PB

and

SR

simultaneously can

either assert reset output

RST

(see Figure 18) or deassert the EN or

EN

output (see

Figure 19) based on the option used.

Note:

A switch to GND must be connected to this input (e.g. mechanical push-button, open drain

output of external circuitry, etc.), see Figure 1. This ensures a proper startup signal on

PB

(i.e. a transition from full VCC below specified VIL).

PB

input has an internal 100 kΩ pull-up

resistor connected.

VCCLO - high threshold detection output

During power-up, VCCLO is low when VCC supply voltage is below the VTH+ threshold. After successful power-up (i.e. during normal operation) VCCLO is low anytime undervoltage is detected (see Figure 13).

Output type is active low and open drain by default. Open drain output type requires a pullup resistor. A 10 kΩ is sufficient in most applications.

VCCLO is floating when STM660x is in standby mode.

PBOUT - PB input state

If the push-button PB is pressed, the pin stays low during the tDEBOUNCE time period. If PB is asserted for the entire tDEBOUNCE period, PBOUT will then stay low for at least

tINT_Min. If PB is asserted after tINT_Min expires, PBOUT will return high as soon as PB is deasserted (see Figure 22). PBOUT ignores PB assertion during an undervoltage condition.

At startup on the STM6601 PBOUT will respond only to the first PB assertion and any other

assertion will be ignored until tON_BLANK expires. This output is active low and open drain by default. Open drain output type requires a pull-up resistor. A 10 kΩ is sufficient in most

applications.

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STM6600, STM6601	Pin descriptions

EN or EN - enable output

This output is intended to enable system power (see Figure 1). EN is asserted high after a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed

and held for tDEBOUNCE or more and VCC > VTH+ voltage level has been detected - see Figure 13). EN is released low if any of the conditions below occur:

a)the push-button is released before PSHOLD is driven high (valid for STM6600, see Figure 9) or tON_BLANK expires before PSHOLD is driven high during startup (valid for both STM6600 and STM6601, see Figure 10 and 12).

b)PSHOLD is driven low during normal operation (see Figure 14).

c)an undervoltage condition is detected for more than tSRD + tINT_Min + tDEBOUNCE

(see Figure 21).

d)a long push of the buttons is detected (only for the device with option “EN

deasserted by long push” - see Figure 19) or PSHOLD is not driven high during tON_BLANK after a long push of the buttons (only for the device with option “RST asserted by long push” - see Figure 18).

Described logic levels are inverted in case of EN output. Output type is push-pull by default.

RST - reset output

This output pulls low for tREC:

a)during startup. PB has been pressed (falling edge on the PB detected) and held

for at least tDEBOUNCE and VCC > VTH+ (see Figure 7, 8, 9, 10, 11, 12 and 13 for more details).

b)after long push detection (valid only for the device with option “RST asserted by

long push”). PB has been pressed (falling edge on the PB detected) and held for more than tDEBOUNCE + tSRD (additional Smart Reset™ delay time can be adjusted by the external capacitor CSRD) - see Figure 18.

Output type is active low and open drain by default. Open drain output type requires a pullup resistor. A 10 kΩ is sufficient in most applications.

INT - interrupt output

While the system is under normal operation (PSHOLD is driven high, power for application is

asserted), the INT is driven low if:

a)VCC falls below VTH- threshold (i.e. undervoltage is detected - see Figure 20 and

21).

b)the falling edge on the PB is detected and the push-button is held for tDEBOUNCE or more. INT is driven low after tDEBOUNCE and stays low as long as PB is held. The INT signal is held high during power-up.

The state of the PBOUT output can be used to determine if the interrupt was caused by

either the assertion of the PB input, or was due to the detection of an undervoltage condition on VCC.

INT output is asserted low for at least tINT_Min.

Output type is active low and open drain by default. Open drain output type requires a pullup resistor. A 10 kΩ is sufficient in most applications.

GND - ground

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Operation	STM6600, STM6601

3 Operation

The STM6600-STM6601 simplified smart push-button on/off controller with Smart Reset™ and power-on lockout enables and disables power for the application depending on pushbutton states, signals from the processor, and battery voltage.

Power-on

Because most of the processors have outputs in high-Z state before initialization, an internal

pull-down resistor is connected to PSHOLD input during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18).

To power up the device the push-button PB has to be pressed for at least tDEBOUNCE and VCC has to be above VTH+ for the whole tDEBOUNCE period. If the battery voltage drops below VTH+ during the tDEBOUNCE, the counter is reset and starts to count again when VCC >

VTH+ (see Figure 13). After tDEBOUNCE the enable signal is asserted (EN goes high, EN goes low), reset output RST is asserted for tREC and then the startup routine is performed

by the processor. During initialization, the processor sets the PSHOLD signal high.

On the STM6600 the PSHOLD signal has to be set high prior to push-button release and tON_BLANK expiration, otherwise the enable signal is deasserted (EN goes low, EN goes high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the

maximum time allowed for the system to power up and initialize the circuits driving the

PSHOLD input. If the PSHOLD signal is low at push-button release, the enable output is deasserted immediately, thus turning off the system power. If tON_BLANK expires prior to

push-button release, the PSHOLD state is checked at its expiration. This safety feature disables the power and prevents discharging the battery if the push-button is stuck or it is held for an unreasonable period of time and the application is not responding (see Figure 8 and 10). PB status, INT status and VCC undervoltage detection are not monitored until power-up is completed.

On the STM6601 the PSHOLD signal has to be set high before tON_BLANK expires, otherwise the enable signal is deasserted - see Figure 11 and 12. In this case the tON_BLANK period is the maximum time allowed for the power switch and processor to perform the proper power-

on. If the PSHOLD signal is low at the end of the blanking period, the enable output is

released immediately, thus turning off the system power. PB status, INT status and VCC undervoltage detection are not monitored during the entire tON_BLANK period. This failsafe feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive microprocessor.

Push-button interrupt

If the device works under normal operation (i.e. PSHOLD is high) and the push-button PB is pressed for more than tDEBOUNCE, a negative pulse with minimum tINT_Min width is

generated on the INT output. By connecting INT to the processor interrupt input (INT or NMI) a safeguard routine can be performed and the power can be shut down by setting PSHOLD low - see Figure 14.

Forced power-down mode

The PSHOLD output can be forced low anytime during normal operation by the processor and can deassert the enable signal - see Figure 14.

Undervoltage detection

If VCC voltage drops below VTH- voltage threshold during normal operation, the INT output is driven low (see Figure 20 and Figure 21).

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STM6600, STM6601	Operation

If an undervoltage condition is detected for tDEBOUNCE + tINT_Min + tSRD, the enable output is deasserted (see Figure 21).

Hardware reset or power-down while system not responding

If the system is not responding and the system hangs, the PB and SR push-buttons can be pressed simultaneously longer than tDEBOUNCE + tINT_Min + tSRD, and then

a)either the reset output RST is asserted for tREC and the processor is reset (valid only for the device with option “RST asserted by long push”) – see Figure 18

b)or the power is disabled by EN or EN signal (valid only for the device with option “EN deasserted by long push”) – see Figure 19

The tSRD is set by the external capacitor connected to the CSRD pin. SR input is monitored for falling edge after power-up and must not be grounded permanently.

Standby

If the enable output is deasserted (i.e. EN is low or EN is high), the STM660x device enters standby mode with low current consumption (see Table 5). In standby mode PB input is only monitored for the falling edge. The external 1.5 V voltage reference is also disabled in standby mode.

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Waveforms	STM6600, STM6601

4 Waveforms

Figure 7. Successful power-up on STM6600 (PB released prior to tON_BLANK expiration)

					PB released prior to t ON_BLANK
					expiration
Push-button pressed and		processor			PSHOLD state detected as high
PB connected to GND		sets PSHOLD			EN remains asserted
PB(1)	VCC undervoltage detection
		ignored
	PSHOLD
	ignored
(2)	internal	pull-down resistor
PSHOLD	connected to PSHOLD input

EN(3)

RST

tDEBOUNCE tREC

tON_BLANK

Note: INT signal is held high during power-up (i.e. until PB release in this case).

VCC is considered VCC > VTH+.

AM00247v3

1.PB detection on falling and rising edges.

2.Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.

3.EN signal is high even after PB release, because processor sets PSHOLD signal high before PB is released.

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STM6600, STM6601							Waveforms
Figure 8. Successful power-up on STM6600 (tON_BLANK expires prior to							release)
						PB
					tON_BLANK expired prior to PB
					release
Push-button pressed and		processor			PSHOLD state detected as high
					EN remains asserted
PB connected to GND		sets PSHOLD					PB released
PB(1)	VCC undervoltage detection
		ignored
	PSHOLD
	ignored
(2)	internal	pull-down resistor
PSHOLD	connected to PSHOLD input
EN(3)

RST

tDEBOUNCE tREC

tON_BLANK

Note: INT signal is held high during power-up (i.e. until tON_BLANK expires in this case). VCC is considered VCC > VTH+.

AM00247bv2

1.PB detection on falling and rising edges.

2.Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.

3.tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration.

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Waveforms	STM6600, STM6601

Figure 9. Unsuccessful power-up on STM6600 (PB released prior to tON_BLANK)

	PB released
Push-button pressed and	PSHOLD state detected as low
PB connected to GND	EN deasserted

		(1)	VCC undervoltage detection			PB status
	PB
			ignored			ignored
			PSHOLD
			ignored
(2)			internal pull-down resistor
PSHOLD			connected to PSHOLD input
EN(3)

RST

tDEBOUNCE

tREC

tEN_OFF

tON_BLANK

Note: INT signal is held high during power-up (i.e. until PB release in this case).

VCC is considered VCC > VTH+.

AM00248v3

1.PB detection on falling and rising edges.

2.Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up.

3.EN signal goes low with PB release, because processor did not force PSHOLD signal high.

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